CN1430258A - Method of integrated manufacturing high-voltage element and low voltage element - Google Patents
Method of integrated manufacturing high-voltage element and low voltage element Download PDFInfo
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- CN1430258A CN1430258A CN 02124780 CN02124780A CN1430258A CN 1430258 A CN1430258 A CN 1430258A CN 02124780 CN02124780 CN 02124780 CN 02124780 A CN02124780 A CN 02124780A CN 1430258 A CN1430258 A CN 1430258A
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Abstract
A method for integral manufacturing high-voltage element and low-voltage element includes such steps as providing a substrate with a patterned insulating layer, generating a first and a second isolating reginos between high-voltage and low-voltage elements, generating patterned photoresist layer, generating doped region in substrate under the exposed insulating layer, generating recess in the second isolating region, sequentially removing patterned photoresist layer and patterned insulating layer, generating join region, generating the first and the second grid structure in the high-voltage and low-voltage element regions, generating light doped drain region in the low-voltage element region, generating partion wall on grid walls, and generating heavy doped source/drain regions.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, and be particularly related to the method for a kind of integrated manufacturing high voltage device and low voltage component.
Background technology
Generally speaking, on the logical circuit of low pressure, its interface needs high voltage device and changes required voltage to various electronic installations.Therefore, on integrated circuit (IC) design, need the very compatible manufacture process of low pressure and high voltage device manufacturing,, can also reach the required different magnitudes of voltage of the various electronic installations of driving except reducing the manufacturing cost.
Existing high voltage devices is in substrate, form polysilicon gate earlier, utilize polysilicon gate very to cover curtain then, to aim at (Self-align) mode voluntarily, in substrate, form and have double-diffused drain electrode (double diffused drain, DDD) source/drain regions of structure.Generally carrying out light ion doping below the isolated area with below the source/drain regions, and carry out high temperature and become into (drive in) step, to form the double-diffused drain electrode structure, in order to alleviate thermoelectronic effect (Hot Electron Effect), improve the breakdown voltage that source/drain regions connects electricity thus, make high voltage device under high-tension situation, still can normal operation.Yet, in the integrated manufacture process of high voltage device and low voltage component, because low voltage component is different with the structure of high voltage device, the required heat budget of manufacture process neither with, therefore existingly in substrate, form bonding land (grade region) with alignment so voluntarily, when the high temperature of rowland of going forward side by side becomes into step, can make the undesired drift of electrical generation of low voltage component to cause the electrically unstable problem of low voltage component.
Summary of the invention
Therefore the present invention is exactly in the method that a kind of integrated manufacturing high voltage device and low voltage component are provided, the method process description is as follows: the substrate that is formed with one deck patterned insulation layer is provided, then, in the substrate that patterned insulation layer exposed, form first isolated area and second isolated area, wherein, first isolated area is isolated a high voltage device district and a low voltage component district, and second isolated area then is arranged in a cutting area of substrate.Afterwards, above substrate, form the patterning photoresistance, the patterned insulation layer of the part substrate top in the exposed high voltage device district of this patterning photoresistance and second isolated area of cutting area.Subsequently, form a doped region in the substrate below the insulating barrier that the patterning photoresistance is exposed.Subsequently, in second isolated area of cutting area, form a groove.Afterwards, divest this patterning photoresistance and patterned insulation layer successively, then, carry out becoming, this doped region is diffused to form a bonding land in this substrate into step.Subsequently, be alignment mark with the groove, in the substrate in high voltage device district and low voltage component district, form a first grid structure and a second grid structure respectively.After this, form a lightly mixed drain area in this substrate of the both sides of the second grid structure in the low voltage component district.Thereupon, on a sidewall of first and second grid structure, form a clearance wall.At last, in this substrate that the clearance wall and first isolation structure of first and second grid structure exposed, form a heavily doped region and source respectively, heavily doped region and this bonding land form a double-diffused drain electrode structure.Wherein, before forming first and second grid structure, be alignment mark with the groove, carry out one and adjust the implantation manufacture process.
The present invention utilizes same patterning photoresistance to aim at the doped region in formation high voltage device district and the groove of cutting area voluntarily, therefore, adjust when implanting manufacture process and forming first and second grid structure follow-up, can be with the groove of cutting area as an alignment mark, and obtain optimum alignment accuracy.Moreover, because before the source/drain regions that forms first and second grid structure and low voltage component, form doped region earlier in the high voltage device district, and become into step formation bonding land, therefore, formed low voltage component can not become into step because of the high temperature of bonding land, causes its electrically problem of drift.
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularly one optimum embodiment, and in conjunction with the accompanying drawings, do following detailed description.
Description of drawings
Shown in Figure 1A to Fig. 1 E, be a kind of integrated manufacturing high voltage device of the one optimum embodiment according to the present invention and the method flow generalized section of low voltage component.
Embodiment
Shown in Figure 1A to Fig. 1 D, be a kind of integrated manufacturing high voltage device of the one optimum embodiment according to the present invention and the method flow generalized section of low voltage component.
Please refer to Figure 1A, at first, provide a substrate 100, in substrate 100, form an insulation layer patterned 106.This insulating barrier 106 for example is with Low Pressure Chemical Vapor Deposition (low pressurechemical vapor deposition, LPCVD) formed silicon nitride layer.This insulating barrier 106 is to expose the part substrate 100 that forms isolated area in subsequent manufacturing processes.Then, carry out an oxidation manufacture process, form isolated area 104 and 104a with substrate 100 oxidations of the part substrate 100 that exposed at insulating barrier 104 respectively and cutting area 102c, and by isolated area 104 isolated high-voltage element region 102a and low voltage component district 102b.Wherein, isolated area 104 comprises the growth of carrying out oxide layer with wet oxidation process with the formation method of 104a, to form a field oxide in substrate 100.
Afterwards, please refer to Figure 1B, above substrate 100, form one deck patterning photoresistance 107.The insulating barrier 106 of substrate 100 tops of these patterning photoresistance 107 exposed predetermined formation bonding lands and the part isolated area 104a of cutting area 102c, and the substrate 100 of protection low voltage component district 102b.Wherein, patterning photoresistance 107 is at the pattern of high voltage device district 102a, and the high voltage device that visual institute desire forms is adjusted for symmetrical or asymmetric high voltage device.Then, carry out an ion and implant manufacture process, form a doped region 108 with 100 surfaces of the substrate below the insulating barrier 106 that is exposed at patterning photoresistance 107.Subsequently, with insulating barrier 106 is cover curtain layer, in cutting area 102c, the part isolated area 104a that patterning photoresistance 107 is exposed goes up and forms a groove 104b, and in the follow-up little shadow manufacture process of the depth visual of this groove 104b, little shadow board can identification the degree of depth and change, preferably its degree of depth upper limit is decided by the material of the isolated area 104a Material Selection ratio to insulating barrier 106, and groove 104b does not penetrate isolated area 104a.Since doped region 108 and groove 104b be utilize same patterning photoresistance 107 aim at voluntarily form, therefore, when the formed groove 104b of cutting area 102c can be at follow-up formation grid structure, as an alignment mark (alignment mark) and cursor (vernier), so that the grid structure of follow-up formation has optimum alignment accuracy (alignment accuracy).
Then, please refer to Fig. 1 C, strip pattern photoresistance 107 and insulation layer patterned 106 successively, wherein, the method of strip pattern photoresistance 107 for example is wet etching or dry-etching method, and the method for strip pattern insulating barrier 106 for example is a wet etch method.Subsequently, become,, form bonding land 108a to diffuse in the substrate 100 downwards by high temperature the dopant ion in the above-mentioned doped region 108 and side diffuses in the part substrate 100 of isolated area 104 belows into (drive in) step.Wherein, the temperature of the step that becomes is about between 1000 to 1200 degree Celsius, and preferably temperature is about 1100 degree Celsius.Afterwards, utilize the groove 104b of cutting area 102c to be alignment mark, carry out one and adjust implantation (adjustimplantation) manufacture process, this adjustment implantation manufacture process system comprises resisting wears ion implantation (anti-punching through ion implantation) and starting voltage adjustment ion implantation (threshold voltage ion implantation).
Because before at the source/drain regions 118b (please refer to Fig. 1 E) of the grid structure 112 (please refer to Fig. 1 D) that forms high voltage device district 102a and low voltage component district 102b and low voltage component, form doped region 108 at high voltage device district 102a earlier, and become into step formation bonding land 108a, therefore, formed low voltage component, can not become into step, cause its electrically problem of drift because of the high temperature of bonding land 108a.
Continuing it, please refer to 1D figure, is alignment mark and cursor with the groove 104b of cutting area 102c, forms the grid structure 112 with gate oxide 110a and gate electrode 110b in substrate 100.Wherein, the grid structure 112 of high voltage device district 102a is in the substrate between the 108a of bonding land 100, with bonding land, cover part 108a.And substrate 100 tops that the method that forms grid structure 112 is included among high voltage device district 102a and the low voltage component district 102b form a layer insulating (not illustrating) and one deck conductive layer (not illustrating) successively, then, groove 104b with cutting area 102c is alignment mark and cursor, patterned conductive layer and insulating barrier are to form the grid structure 112 with gate oxide 110a and gate electrode 110b in substrate.Wherein, the material of gate electrode 110b comprises polysilicon.Since bonding land 108a and groove 104b system utilize same patterning photoresistance 107 aims at voluntarily form, therefore, formed grid structure 112 has the alignment accuracy of optimum in high voltage device district 102a.
Then, please refer to Fig. 1 E, in grid structure 112 substrate on two sides 1 00 of low voltage component district 102b, form a lightly doped drain (lightly doped drain, LDD) district 114, wherein, the ion doping dosage (dose) in the lightly mixed drain area 114 is about 1 * 10
13/ cm
2To 5 * 10
13/ cm
2Subsequently, sidewall in grid structure 112 forms clearance wall 116, the formation method of this gap wall 116 is included in substrate 100 tops and forms an insulating barrier (not illustrating), then, (anisotropicetching) divests partial insulative layer with anisotropic etching, forms clearance wall 116 with the sidewall at grid structure.Continue, in the clearance wall 116 both sides substrates 100 respectively at high voltage device district 102a and low voltage component district 102b, form heavily doped region 118a and source/drain regions 118b, and heavily doped region 118a among the high voltage device district 102a and bonding land 108a form a double-diffused drain electrode structure.Wherein, the dopant dose among heavily doped region 118a and the source/drain regions 118b is about 5 * 10
15/ cm
2Then, carry out a tempering manufacture process to recover the crystalline texture of substrate surface.
Among the present invention, aim at the doped region in formation high voltage device district and the groove of cutting area voluntarily owing to utilize same patterning photoresistance, therefore, when adjusting implantation manufacture process and formation grid structure subsequently, can so that implanting the grid structure of manufacture process and formation, the adjustment of carrying out subsequently have best alignment accuracy with the groove of cutting area as an alignment mark and cursor.Moreover, because before the source/drain regions of grid structure that forms high voltage device district and low voltage component district and low voltage component, form doped region earlier in the high voltage device district, and become into step formation bonding land, therefore, formed low voltage component can not become into step because of the high temperature of bonding land, causes its electrically problem of drift.
Though the present invention discloses as above with an optimum embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing various changes and modification, thus protection scope of the present invention when with appended claim the person of being defined be as the criterion.
Claims (12)
1. the manufacture method of a high voltage device comprises:
One substrate is provided, and this substrate has a cutting area and a high voltage device district, is formed with an isolated area in this cutting area, is formed with an insulating barrier in this high voltage device district in this substrate;
Above this substrate, form a patterning photoresistance, this insulating barrier of this substrate top of the part in exposed this high voltage device district of this patterning photoresistance and this isolated area of this cutting area;
Form a doped region in this substrate below this insulating barrier that this patterning photoresistance is exposed;
In this isolated area of this cutting area, form a groove;
Divest this patterning photoresistance and this insulating barrier successively;
Carry out becoming, this doped region is diffused to form a bonding land in this substrate into step;
With this groove is alignment mark, in this substrate between this bonding land, forms a grid structure;
On a sidewall of this grid structure, form a clearance wall; And
In this substrate that clearance wall and this isolation structure exposed of this grid structure, form a heavily doped region, this heavily doped region and this bonding land form a double-diffused drain electrode structure.
2. the manufacture method of high voltage device as claimed in claim 1, wherein carrying out this temperature that becomes into step is 1000 to 1200 degree Celsius.
3. the manufacture method of high voltage device as claimed in claim 1 wherein forms this grid structure and comprises that also with this groove be alignment mark before, carries out one and adjusts the implantation manufacture process.
4. the manufacture method of high voltage device as claimed in claim 3, wherein this adjustment is implanted manufacture process and is comprised that one resists and wears ion and implant manufacture process.
5. the manufacture method of high voltage device as claimed in claim 3, wherein this adjustment is implanted manufacture process and is comprised that an initial voltage ion implants manufacture process.
6. the manufacture method of high voltage device as claimed in claim 1 after forming this heavily doped region, also comprises and carries out a tempering manufacture process.
7. the method for integrated manufacturing high voltage device and low voltage component comprises:
One substrate is provided, is formed with a patterned insulation layer in this substrate;
In this substrate that this patterned insulation layer exposed, form one first isolated area and one second isolated area, wherein, this first isolated area is isolated a high voltage device district and a low voltage component district, and this second isolated area is arranged in a cutting area of this substrate;
Above this substrate, form a patterning photoresistance, this patterned insulation layer of this substrate top of the part in exposed this high voltage device district of this patterning photoresistance and this second isolated area of this cutting area;
Form a doped region in this substrate below this insulating barrier that this patterning photoresistance is exposed;
In this second isolated area of this cutting area, form a groove;
Divest this patterning photoresistance and this patterned insulation layer in regular turn;
Carry out becoming, this doped region is diffused in this substrate and in this substrate of part of this first isolated area below form a bonding land into step;
With this groove is alignment mark, in this substrate in this high voltage device district and this low voltage component district, form a first grid structure and a second grid structure respectively, this first grid structure is in this substrate between this bonding land, and this bonding land, cover part;
Form a lightly mixed drain area in this substrate of the both sides of this second grid structure in this low voltage component district;
This first with a sidewall of this second grid structure on, form a clearance wall; And
This first with this clearance wall of this second grid structure and this substrate that this first isolation structure is exposed in, form a heavily doped region and source respectively, this heavily doped region and this bonding land form a double-diffused drain electrode structure.
8. the method for integrated manufacturing high voltage device as claimed in claim 7 and low voltage component, wherein carrying out this temperature that becomes into step is 1000 to 1200 degree Celsius.
9. the method for integrated manufacturing high voltage device as claimed in claim 7 and low voltage component, wherein form this first with this second grid structure before, comprise that also with this groove be alignment mark, carry out one and adjust to implant manufacture process.
10. the method for integrated manufacturing high voltage device as claimed in claim 9 and low voltage component, wherein this adjustment is implanted manufacture process and is comprised that one resists and wears ion and implant manufacture process.
11. the method for integrated manufacturing high voltage device as claimed in claim 9 and low voltage component, wherein this adjustment implantation manufacture process comprises an initial voltage ion implantation manufacture process.
12. the method for integrated manufacturing high voltage device as claimed in claim 7 and low voltage component wherein forms after this heavily doped region and this source/drain regions, also comprises carrying out a tempering manufacture process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/888,909 | 2001-06-25 | ||
| US09/888,909 US6509243B2 (en) | 1999-06-05 | 2001-06-25 | Method for integrating high-voltage device and low-voltage device |
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| Publication Number | Publication Date |
|---|---|
| CN1430258A true CN1430258A (en) | 2003-07-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02124780 Pending CN1430258A (en) | 2001-06-25 | 2002-06-25 | Method of integrated manufacturing high-voltage element and low voltage element |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416800C (en) * | 2005-05-24 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Method of forming dual gate variable VT device |
| CN102280383A (en) * | 2010-06-14 | 2011-12-14 | 富士电机株式会社 | Method of manufacturing super-junction semiconductor device |
| CN101996926B (en) * | 2009-08-13 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for self aligned contact of integrated circuit |
| CN112582408A (en) * | 2020-12-09 | 2021-03-30 | 长江先进存储产业创新中心有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN113611670A (en) * | 2020-11-16 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Device including gate oxide layer and alignment mark and method of forming the same |
-
2002
- 2002-06-25 CN CN 02124780 patent/CN1430258A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416800C (en) * | 2005-05-24 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Method of forming dual gate variable VT device |
| CN101996926B (en) * | 2009-08-13 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for self aligned contact of integrated circuit |
| CN102280383A (en) * | 2010-06-14 | 2011-12-14 | 富士电机株式会社 | Method of manufacturing super-junction semiconductor device |
| CN102280383B (en) * | 2010-06-14 | 2016-05-11 | 富士电机株式会社 | Manufacture the method for super junction-semiconductor device |
| CN113611670A (en) * | 2020-11-16 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Device including gate oxide layer and alignment mark and method of forming the same |
| CN112582408A (en) * | 2020-12-09 | 2021-03-30 | 长江先进存储产业创新中心有限责任公司 | Semiconductor device and manufacturing method thereof |
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