KR100278424B1 - Thin active layer semiconductor device with high breakdown voltage - Google Patents

Abstract

The silicon substrate 1 carries an insulating silicon oxide layer 2 and a very weakly negatively doped (n) monocrystalline silicon wafer 3. The device portion 4 is limited by the insulating layer 5 at the wafer. It has a base portion (B) coated with a bipolar transistor (PIP1) of the device portion with a positive coating (P), and this portion (B) is high with a positively coated (P ⁺ ) base connection (B1). constitutes the applied (n ⁺⁾ emitter (E1). transistor (BIP1) has a base portion (B) has a PN- junction to the side below, and the coated (n ⁺⁾ to very high negative drain connection (D1) It is connected in series with the field effect transistor JFET 1. The device portion 4 is very weakly doped, and the distance from the PN junction 9 to the silicon oxide layer 2 is small, so that the voltage V _E , When V _B , V _D is applied to transistors BIP1, JFET1, portion DP1 is easily depleted by the charge carriers, which prevents breakdown of current between base B and drain connection D1. Transistors BIP1, JFET1 withstand high voltages and have only half the space of substrate 1 where a corresponding previously known transistor is needed.

Description

Thin active layer semiconductor device with high breakdown voltage

1 is a cross-sectional view of a bipolar transistor and a field effect transistor.

2 is a cross-sectional view showing the electric field lines of the transistor shown in FIG.

3 is a schematic representation of the transistors of FIGS. 1 and 2.

4 is a schematic diagram of two series connected transistors.

5 is a cross-sectional view of the transistor of FIG.

6 is a view of the transistor of FIG.

7 is a cross-sectional view showing electric field lines relating to the transistor of FIG.

FIG. 8 shows electric field lines relating to the transistor of FIG. 4. FIG.

9 is a diagram of current-voltage characteristics of the transistor device of FIG.

10 is a graph showing comparative curves for known and inventive transistors.

11 through 14 are cross-sectional views illustrating various steps of fabricating the transistor shown in FIG.

* Explanation of symbols for main parts of the drawings

1,2,4a, 21,22,24a, 24b: semiconductor body 4,24: device part

5,10,25 Separation layer 9,29 PN junction

8,26: electrical connection BIP1, BIP2: bipolar transistor

E1, E2 emitter part G3: projecting part

The present invention relates to a thin active layer semiconductor device having a high breakdown voltage, wherein the semiconductor device having a charge carrier depletion portion for reducing electric field strength comprises: a semiconductor body; An element region of the semiconductor material formed in the semiconductor main body, the upper region having an upper surface lightly doped with a doping material of the first aspect (n); An insulating layer separating the semiconductor body and the bottom of the elemental component; An electrical separation layer extending along the remaining surface of the device portion in contact with the semiconductor body; A doped material (P) of the second form, which is opposite to the doped material of the first form, having a low concentration and having a chip-shaped portion in the element portion extending from the upper surface of the element portion; A PN-junction on the face of the chip portion separating the device portion and the region of the remaining portion; One or more semiconductor devices in the device portion; With one or more semiconductor elements in the device portion, the portion of the reduced field strength is applied to the electrical connection to deplete the charge carriers, and the first charge carrier depletion portion is at least below the insulating layer at the PN-junction. And at least two electrical contacts formed in the device region.

Semiconductor circuits must be able to withstand high voltage applications. This application applies to subscriber line circuits in telephone exchanges. For older switch telephone exchanges, the subscriber line requires 48 volts of applied voltage, which is also applied to current subscriber line circuits in semiconductor technology. In other countries, ie Germany, higher voltages, 68 volts, are applied, and in other applications of semiconductor circuits more than 400 volts.

One problem with very high voltages is that the field strength may exceed the critical field of the semiconductor material in any region of the substrate. If the current is not limited, this breakdown can cause current breakdown to destroy the semiconductor material. Due to the high field strength, the above problems can occur in micro circuits and metal semiconductors for output circuits. Even if these devices are connected to low voltage, i.e. 3-5 volts, the field strength is high by making the devices slightly larger.

In some applications, the problem of high field strength arises on the surface of semiconductor devices (see IEEE, Proceedings from IEDM, 1979, pages 238-241, by JA Appels and HMJ Vaes “High Voltage Thin Layer). Devices (Resurf Devices) ”is included in the description of the present invention. The semiconductor device has a surface layer, which includes a PN junction, in which the critical field strength of the material is close to a predetermined applied voltage. This surface layer is very weakly doped on one side of the PN-junction, and this weakly doped portion makes the surface layer very thin, allowing charge carriers to deplete. In addition to the electric field, the applied voltage is distributed over a long distance along the surface of the device to adopt a value below the maximum field strength breakdown field. This principle is known in semiconductor technology and is disclosed in the RESURF (Reduces Surface Field), a personal weakness, and the resurf technique is described in the following paper. [Philips J, Res. 35, 1-13, 1980, J.A. Apples, et al: “Thin Layer High-Voltage Devices”] are also included in this paper.

U.S. Patent No. 4,409,606 describes a resurf technique applied to transistors. A very thin semiconductor layer on which a transistor is formed is embedded on a semiconductor substrate. The substrate and the layer form a PN-junction, with the very heavily doped regions of the PN-junction arranged under one transistor connection. This PN-junction is reverse biased and the thin semiconductor layer depletes the charge carriers to the top layer surface along an extended passage between the very heavily doped portion and the second transistor connection. If this passage is very long, good stability to current breakdown is obtained. Application of this resurf technique prevents the occurrence of breakdown voltage due to current amplification, often common base amplification (α ₀ ). Similar devices are also described in US Patent Application No. 4,639,761.

European patent application A1-0,086,010 discloses a transistor similar to the transistors described in the two aforementioned United States patent applications. However, this transistor lacks a very strongly doped portion of the PN-junction, and the layer on which the transistor is formed has a high doping concentration. Thus, it is difficult to completely deplete the charge carriers in the bilayer, and the insulating electrode is placed above this region where the charge carriers will be depleted to achieve full depletion.

In the case of the two United States patent specifications and the European patent application described above, the transistor is connected to the semiconductor substrate of the device via the PN-junction described above. Deep, heavily doped portions with reverseviral PN-junctions limit the transistor to both. Thus, a problem with limited transistors is that the transistors occupy space in the substrate. This problem is solved by using a device according to European Patent Application No. A1-0,418,737 which describes transistors on a common substrate which are historically insulated from one another. The surface of the semiconductor substrate is oxidized to form an insulating layer embedded with a very thin wafer of epitaxial semiconductor material. An etched groove is formed in the axial etch wafer, which extends under the etched insulating layer. This groove is filled with polycrystalline semiconductor material. The devices are formed in an insulated box-shaped area. These devices have external connections, which are connected to the highly doped connection layers under each device at the bottom of the box in direct contact with the insulating oxide layer.

European patent application A2-0,391,056 describes another method of forming a semiconductor substrate with an insulating area as an insulator. The insulating region is formed by repeatedly etching the substrate and coating the semiconductor material. This separation consists of oxidized semiconductor materials. This region has a very lightly doped region in which the actual device is formed and a very highly doped layer located below the device and positioned against the insulating layer.

Three US patent specifications 4,587,545, 4,587,655 and 4,608,590 disclose high voltage semiconductor switches. These switches are gate-providing diodes formed in the insulating regions of very weakly doped semiconductor materials. The anode and the cathode are spread on the face of the insulated part, and the electrical connection between them can be broken by the gate of the face of the part. The anode and the cathode have a doping type opposite to that of the insulating region. The area around the anode and cathode is de-energized by the charge carriers depleted by the resurf technique by applying the appropriate voltage to the switch, resulting in a very large resistance in the cutoff state.

In accordance with the present invention, this patent relates to the use of the resurf technique in the area of the electrically restricted element relative to the other types of devices in the electrically restricted region. In particular, the present invention includes a bipolar transistor connected in series with a field effect transistor. This transistor device is formed in an element portion having an insulating layer on the bottom surface. The bipolar transistor has a base portion extending downward from the top surface of the device portion. The PN-junction between the base region and the electrically insulating layer constrains the base region and becomes reverse virus so that the area between the base region and the insulating layer is depleted by the telephone carrier. This depletion occurs at the collector voltage of several volts and can be easily formed because the device portion is very weakly doped and the depletion region below this base region is much thinner than known bipolar transistors. Even if this portion below the base portion is thin, the transistor device can withstand high voltage because the voltage is broken on both sides by the element portion below the charge carrier depletion base portion. Transistor devices have a series of resistors, which are normalized for bipolar transistors and cannot be expected because the device is accompanied by a strongly doped collector portion below the base portion. The features of the transistor device are much thinner than the corresponding known devices and occupy less part of the semiconductor substrate than the devices of the prior art.

The invention is characterized by the following claims.

1 is a cross-sectional view of the bipolar NPN transistor BIP1 of the present invention connected in series with the field effect transistor JFET1. The semiconductor substrate 1, in this case a silicon substrate, has an oxidized top surface to form an electrically insulating silicon oxide layer. A thin wafer 3 of monocrystalline silicon is embedded in the upper surface 2, which is an active layer of the transistor devices BIP1 and JFET1. This active layer has a low concentration n of negative charge carriers. The mono crystalline wafer 3 has a thickness A1 of 4 mu m in the illustrated embodiment. The device region 4 is separated from the neighboring portions 4a and 4b of the wafer 3 by a separation layer 5 composed of silicon oxide and polycrystalline silicon. The isolation layer 5 extends below the insulating layer 2 at the surface of the mono crystalline wafer 3 to completely surround the transistors BIP1 and JFET1. Thus, the device region 4 is completely electrically insulated from the substrate 1 and the peripheral portions 4a and 4b of the mono crystal line wafer 3. The transistor BIP1 constitutes a region B doped with a positive charge carrier P. The base B has a connection area B1 which interacts with an external electrical connection device, which is P ⁺ doped with a positive charge carrier. The base portion of transistor BIP1 includes emitter E1 strongly doped with negative charge carrier n ⁺ . In addition, the collector portion K1 of the transistor BIP1 is located in the element region 4. The gate connection point G1 of the transistor JFETI is common with the base connection point B1, and the source portion S1 of the transistor is common with the collector portion K1 of the transistor BIP1. The region D1 strongly doped with n ⁺ forms the drain connection point of the transistor JFET1.

The element portion 4 is covered with a silicon oxide insulating layer 6, which is formed with holes 7 for external electrical connection points 8. These connection points are respectively connected to the areas of the base B1, the emitter E1, and the drain D1. The configuration of such external electrical connection points is known and is not shown in detail in FIG. 1 for the sake of simplicity.

3 schematically shows the series connection transistors BIP1 and JFET1. The base connection point B1 is connected to the gate connection point G1, and the collector K1 is connected to the source region S1. Each base B1, emitter E1 and drain D1 has one of the external connection points 8.

In normal operation, transistors BIP1 and JFET1 are connected to the next voltage.

Drain Voltage V _D = + 70V

Emitter Voltage VE = OV (Earth)

Base and Gate Voltage V _B = 0.6V

Transistor BIP1 has a PN-junction 9 at the bottom of base portion B, which is reverse biased and depleted of charge carriers in a general manner using an applied voltage. According to the invention, the portion DP1 between the PN-junction 9 and the insulating layer 2 is very lightly doped and the thickness A2 is only 2 μm. Therefore, the charge carriers are depleted in the entire area DP1, and the voltages of most of the electricity between the base portion B and the drain portion D1 are distributed over the very long passage L. Therefore, the values of the electric field strength E _D in the depletion portion DP1 are all set low by the resurf technique, as described in the reference for thickness. [Reference: “High Voltage Thin Layer Device” by JA Appels and HMJ Vase, and “Thin Layer High-Voltage Devices” by JA Appels, et al.] The field strength in the region (DP1) is maintained below the critical strength (E _CR ) of silicon, that is, about 3.10 ⁵ V / cm This prevents surges in current I in this region.

In particular, it should be noted that the entire area DP1 of the transistor BIP1 of the present invention directly below the insulating layer 2 is composed of a very weakly doped material in which charge carriers are easily depleted. Many known transistors include a very highly doped layer located below the base portion of the transistor, so-called buried layer, unlike the above mentioned layer, and the distance of the buried layer between the base portion PN-junction and the very highly doped layer. It is long so that known transistors can withstand high voltages. This very heavily doped layer can completely destroy the resurf effect of transistor device BIP1 and JFET1 of the present invention in FIG. Very strongly doped layers are difficult to deplete charge carriers, and the field strength of these layers can reach the breakdown field strength E _CR even at very low voltages between the drain portion D1 and the emitter E1. In the drain portion D1, the charge carriers are also depleted even in the drain voltage V _D of the male bond.

FIG. 2 is an enlarged portion of FIG. 1. FIG. 2 is a portion of the base region B having the insulating layer 2, the device portion 4, the connection portions B1, G1 and the emitter E1, and the drain. The part D1 and the depletion part DP1 are shown. 2 also includes a group of curves C for the electric field E _D. This curve has 0.5 · 10 ⁵ , 1 · 10 ⁵ . It contains a curve labeled 2.5 · 10 ⁵ and the field strength along this curve is constant. This value is given numerically for each curve (unit is Volt / cm), for example, the electric field along the outermost side in the figure has a value of 0.5 · 10 ⁵ V / cm. Field strength appears when the device is connected to the operating voltage described above. The curve group (C) is based on arithmetic forms to produce very accurate values. It can be seen that the surging of the current I is prevented because the electric field strength of the depletion region DP1 is low. In addition, it can be seen that the electric field E _D is very large on the surface of the element region 4 in the vicinity of the insulating layer 6. At the steady-state voltages of the transistors BIP1 and JFET1, no current flows through the portion of the element portion 4, and no current surge occurs. However, the very high field strength limits the voltage that can be applied to transistor devices BIP1 and JFET1.

In the case of the embodiment of FIG. 1, the device region 4 is surrounded by an insulated separating layer 5. In another embodiment, the isolation layer surrounds the device portion 4 and comprises a very strongly positively P ⁺ doped region extending below the insulating layer 2 in terms of the mono crystalline layer 3. . The isolation layer has a PN-junction applied with a reverse voltage to electrically separate the device region 4 and the peripheral portions 4a and 4b.

Another embodiment of the present invention will be described with reference to FIGS. 4, 5 and 6. 4 schematically shows a bipolar transistor BIP2 connected in series to a field effect transistor JFET2. Transistor BIP2 has base B2 connected to emitter E2 and gate G2 of field effect transistor JFET2. This transistor has a source connection 52 connected to the drain D2 and the collector of the transistor BIP2.

5 is a cross-sectional view of an embodiment of transistors BIP2 and JFET2. This cross section taken the line A-A of FIG. The top surface of the silicon substrate 21 is oxidized to produce the insulating layer 22, and a light n-doped mono crystalline wafer 23 is mounted on the layer 22. The wafer 23 has a thickness of 4 m as in the previous embodiment. The device portion 24 is separated from the mono crystal line wafer 23 by a separation layer 25 surrounding the device portion 24. A trench is formed in the monocrystalline line wafer 23, and the sides of the trench are converted to form an electrically insulating layer, and the remaining trenches are filled with polycrystalline silicon. The device portion 24 is electrically insulated from the peripheral portions 24a and 24b of the mono crystal line wafer 23. The bipolar transistor BIP2 and the field effect transistor JFET2 are arranged in the element portion 24. For clarity, the protective surface layer with holes for the external connection 26 is not shown in the figures. Only the connection point 26 is shown schematically.

Transistor BIP2 has a connection region B2 that is very lightly P-doped and very strongly P ⁺ positively. Emitter E2 of transistor BIP2 is located in base region B3 and is heavily doped with n ⁺ . The base portion B3 extends below the PN-junction 29 below the base region B3 from the top surface of the element region 24. A region DP2 which is not affected by the doping of the base portion is located between the PN-junction 29 and the insulating layer 22. The collector region K2 of the transistor BIP2 is located on one side of the base region B3 as indicated by the dotted line in the figure. In the case of the embodiment of the invention shown in FIG. 5, high overall strength is prevented in the entire collector portion K2, as described in detail below. The gate connection point G2 of the transistor JFET2 is common with the base connection point B2. The active gate is composed of two P-doped regions G3 protruding from the base region B3 in the form of separated protrusions extending along the side of the separation layer 25. The configuration of the gate portion is shown in great detail in FIG. 7, which shows wafer transistors BIP2 and JFET2. 5 shows the gate portion G3 as a dotted line. The branch protrusion G3 extends under the device portion 24 to the same depth as the base portion 53, but may extend directly under the insulating layer 22. The source region 52 of the transistor JFET2 is common with the collector region K2 of the transistor BIP2. The drain junction D2 of transistor JFET2 constitutes a very strongly negatively n ⁺ doped region.

6 shows regions different from transistors BIP2 and JFET2. The device portion 241 is completely surrounded by the separation layer 25, and the base region B3 extends laterally the device portion that is caged at one end of the region. The base connection point B2 and the emitter connection point E2 include an elongated region extending laterally of the element region 24. The branch protrusion G3 protruding from the base region B3, that is, the gate of the transistor JFET, extends in the longitudinal direction of the device region 24 along each side of the isolation layer 25 and the device region. The drain connection point D2 is located at the other end of the element portion. The figure also illustrates another embodiment of the gate connection point G2. A strong, positively P ⁺ doped molecular portion G4 extends into the protrusion G3 to enhance electrical contact with the protrusion. Although the protrusion G3 of the illustrated embodiment has a constant thickness, it may be of other shapes and Y-shaped, for example, shown by the dotted line L1 in the figure.

The electric field and depletion portion of the element portion 24 will be described with reference to FIGS. 7 and 8. The figure is an enlarged view of FIGS. 5 and 6. The region DP2, which is a depletion portion, is in contact with the PN-junction 29 under the base portion B3. The corresponding depletion portion DP1 of the transistor BIP1 has been described in detail with reference to FIGS. 1 and 2. The field effect transistor JFET2 forms a depletion layer DP3 extending between the protrusions G3 as shown by the dotted line. The dotted line in the area DP3 can be displaced by appropriately selecting the voltage applied to the connection 26 of the transistor JFET2. In line AA, this displacement occurs in the direction indicated by the double arrow. As shown in the figure, the depletion layer DP3 extends partially to the protrusion G at the end of the protrusion G3. It can be seen that both gate protrusions G3 of the field effect transistor JFET2 extend below the region from the surface of the device portion 24. Similarly, the depletion portion DP3 extends downward from the surface of the element portion. The electric field strength of the device region is indicated by the curve G2. When the emitter E2 and the base connection B2 are earthed and the drain connection D2 is connected to a voltage of +100 V, the numerical value 1 · 10 ⁵ is Volt / cm applied to the blocking state of the transistor device. Display the field strength along the curve of.

Such electric field strength can be accurately represented by a group of curves similar to the electric field strength shown in FIG. 2, but the curve C2 is shown so that the drawings are not unnecessarily complicated. It can be seen from FIG. 7 that the electric field strength is low in the depletion region DP2 between the depletion portion DP2 and the protrusion G3 under the transistor BIP2. Curve C2 of FIG. 8 shows the electric field strength of the surface of the element portion 24. The curve C2 shown is based on the evaluation of the field strength because it is difficult to make reliable measurements and is attached to the examples shown in FIGS. 5-8.

A very strong electric field strength at the edge of the base region B of FIG. 2, that is, 2.5 · 10 ⁵ V / cm, is prevented in the embodiments of the present invention of FIGS. This means that the series connected transistors BIP2 and JFET2 provide a device that can withstand very strong resistance. Since the protrusion stage can be depleted in charge carriers, another embodiment including the Y-shaped protrusion G3 of FIG. 6 greatly improves the voltage composition. Since the distance between the protrusions G3 is continuously widened toward the drain connection, the series of resistances of the transistor device between the source region S2 and the drain region D1 can be kept low.

Data relating to transistor devices BIP1 and JFET1 shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 9 and 10 and compared with known transistors. In FIG. 9, the drain contact voltage V _D , denoted Volt, is given in the abscissa, and the normalization value of the current I, expressed in mA, is given in the ordinate. 4 mu of the solid line represents the transistor device shown in the drawing, which is formed on the mono crystal line wafer 3 having a thickness of A1 = 4 mu m. The dotted curves 4.5 μ and 5 μ represent the characteristics of the transistor devices formed on mono crystal line wafers of 4.5 and 5 μm thickness. The dotted curve μ shows the characteristics of which the signal processing surface is ideal. The thinner the mono crystalline wafer 3, the closer the characteristic of the transistor device is to the desired ideal curve μ.

FIG. 10 is a graph in which the voltage V _B denoted Volt is given in the abscissa, and the normalized current value expressed in amperes is given in the ordinate. The solid curve IC shows how the above-mentioned current I varies with the voltage V _B at the drain voltage V _b of 7.5 volts. It can be seen that the current curve of the transistor of the previously known structure agrees well with the transistor of the present invention, the two curves being hardly distinguishable in the coordinates. The difference is that the transistor of the present invention generates a slightly lower current only when the voltage V _B is below 0.20 volts. The solid curve IB1 is the base current for the transistor BIP1 of the present invention, and the dotted curve IBO shows the base current for the known transistor just mentioned.

As mentioned above, the transistor BIP1 of the present invention is formed on a wafer having a thickness of A1 = 4 mu, which will be compared with the above-mentioned known transistor formed on a mono crystalline wafer having a thickness of 25 mu m. Known transistors have a strongly doped layer underneath the base portion and the length between this wafer and the base region of the transistor should be very long to prevent breakdown current. Thus, the mono crystalline layer must be thick, which presents a serious drawback. In the case of the present technology, it is not possible to form an isolation layer corresponding to layer 5 in a very thick mono crystalline layer. Known transistors are therefore separated by a separation layer containing a long, heavily doped diffusion, thus requiring space for it. This means that known transistors take up very easy space in the mono crystalline layer.

The method for producing the above-mentioned device will be briefly described with reference to FIGS. 11 to 14. As shown in FIG. 11, the initial material is a so-called adhesive wafer, which comprises a silicon substrate 1, a separated oxide layer 2, and a mono crystalline silicon wafer 3. For example, such bonded wafers are disclosed in the above mentioned European patent application A1-0,418,737 and are commercially available. The upper surface of the wafer is covered with a photoresist layer 31, and the photoresist layer has a predetermined shape, and holes 32 are formed in the photoresist layer 3. The deep trench 33 is etched into the plasma through this hole down to the separation layer 2 and the photoresist layer 31 is removed. The sides of the trench are oxidized to form a silicon oxide layer 34, and the remaining trenches 33 are filled with polycrystalline silicon 33 as shown in FIG. The element part 4 is separated in this way. The wafer 3 is covered with a new photoresist mask 36 with holes 37. This hole is doped with a positive doping material to obtain the base portion B of FIG. The mask 36 is removed and another photoresist mask 38 is attached, which has holes 39 which negatively dop the emitter E1 and the drain connection D1. . The mask 38 is removed and a new photoresist mask is affixed so that the base connection B1 is positively doped through the mask. This manufacturing process is not shown in the drawings. This final photoresist mask is removed and, as shown in FIG. 14, the surface of the wafer 3 is oxidized to produce the insulating silicon oxide layer 6. The layer 6 is covered with a mask 40 with holes 41 through which the connecting holes 7 are etched in the layer 6. The mask 46 is removed and the device is provided with an external connection device and a protective layer, not shown.

As mentioned above, I explained that the bipolar transistor BIP1 is connected in series with the field effect transistor JFET1, and how to make it. The base portion B3 of the transistors BIP2 and JFET2 and the protrusion G3 of the base portion can be formed simply by changing the shape of the hole 37 of the mask 36. The bipolar transistors BIP2 and JFET2 described are NPN transistors, but the claims employ PNP transistors.

The introduction mentioned that large field strengths can occur in devices for calculation or calculation circuits connected to voltages of 3-5 volts. These devices are very fast and have a high concentration of doping material and a small size. For example, the device is about 0.5 μm thick, corresponding to the distance A1 in FIG. 1. The present invention is used in these devices with high connection voltages for these sizes. In the case of this thin device, the above-mentioned separation layer 5 can replace the layer formed by so-called local oxidation (LOCOS) in which the insulation procedure is simple.

Although the present invention is exemplified by silicon, other semiconductor materials such as germanium or gallium arsenide may be used.

The device of the present invention provides several advantages besides voltage permanence. By using the resurf technique in the manner described above, the applied voltage is distributed to most devices. Thus, the device occupies only a very small surface portion of the substrate, as described above. In addition, the device is made very thin, so that the device is insulated from both sides of the above-mentioned insulation isolation layers 5 and 25, respectively. Thus, the space required for the substrate is further reduced. When the present invention is practiced, the required cross-sectional area of the semiconductor substrate producing a high number of elements can be at least half that of known techniques. This is suitable for the subscriber line circuit of the telephone apparatus where each subscriber has its own line circuit. Another advantage of the present invention is that the devices can be made easily because the devices are formed in the finishing mono crystalline semiconductor layer and their shape is determined by selecting a photoresist mask.

Claims (4)

A semiconductor device having a thin active layer having a breakdown voltage and having a charge carrier depletion portion DP1 (DP2, DP3) that reduces the electric field strength (E _D ) is a semiconductor body (1, 2, 4a; 21, 22, 24a). , 24b); An element region (4; 24) of the semiconductor material formed in the semiconductor main body, the upper region having an upper surface lightly doped with a doping material of the first form (n); Insulating layers 2 and 22 separating the semiconductor body and the lower surface of the element portions 4 and 24; An electrical separation layer 5; 10; 25 extending along the remaining surface of the device portions 4; 24 in contact with the semiconductor bodies 1, 2, 4a; 21, 22, 24a, 24b, A second type doping material (P) opposite to the doping material, having a very low concentration and having a chip-shaped portion (B; B3; G3) in the element portion (4; 24) extending from the upper surface of the element portion; A PN-junction (9; 29) formed on the surface of the chip portion separating the device portion from the remaining portion and the region; One or more semiconductor elements BIP1, JFET1; BIP2, JFET2 formed in the element portions 4, 24; In the areas DP1, DP2 and DP3 of the reduced electric field strength, the charge carriers are depleted by the electric voltages V _E , V _B , and V _D applied to the electrical connections 8 and 26, and the first charge carrier depletion portion ( DP1; DP2 extend from the PN-junction 9; 29 to the insulating layer 2; 22, at least below the portion of the chip-like portions B; B3; G3, and the element portions 4; In a semiconductor device comprising two or more electrical connections (8; 26) formed, the semiconductor element includes a bipolar transistor (BIP1; BIP2) connected in series with a second semiconductor element (JFET1; JFET2), wherein the chip-shaped portion is A base portion B; B3 of the bipolar transistors BIP1 and BIP2; The base portions B; B3 are strongly doped (n ⁺ ) with the doping material of the first type and surround the emitter region connected to one of the electrical connection points 8; The base portions B; B3 are strongly doped (P ⁺ ) with the doping material of the second aspect, and are connected to the other electrical connection points (8; 26); The base connection portions B1 and B2 include connection regions G1 and G2 for the second elements JFET1 and JFET2 connected in series; The second semiconductor element (JFET1; JFET2) has a connection region (D1; D2) strongly doped (n ⁺ ) to the rest of the element portion (4; 24) together with the third electrical connection points (8; 26). A semiconductor device, characterized in that the electric field strength (E _D ) of the first depletion regions (DIP1, DP2) is equal to or less than the reciprocating electric field strength (E _CR ) of the semiconductor material. The semiconductor according to claim 1, wherein the second semiconductor elements JFET1 and JFET2 are field effect transistors, and the connection regions D1 and D2 of the transistors are doped with a doping material n of the first type. Device. 3. The isolation layer (25) according to claim 1 or 2, wherein the isolation layer (25) has an insulating wall opposite to each other on the opposite side of the device portion (24), and the chipped portion is opposed to each other of the insulation isolation layer (25). A semiconductor device, characterized in that it has two protrusions (G3) extending along the wall, and the second charge carrier depletion portion (DP3) extends between the protrusions (G3). 4. A semiconductor device according to claim 3, wherein the end of the protrusion (G3) adjacent to the base portion (B3) has a larger cross width than the other end of the protrusion.