KR940018999A - A SEMICONDUCTOR DEVICE IN A THIN ACTIVE LAYER WITH HIGH BREAK-DOWN VOLTAGE - Google Patents

A SEMICONDUCTOR DEVICE IN A THIN ACTIVE LAYER WITH HIGH BREAK-DOWN VOLTAGE Download PDF

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Publication number
KR940018999A
KR940018999A KR1019940001282A KR19940001282A KR940018999A KR 940018999 A KR940018999 A KR 940018999A KR 1019940001282 A KR1019940001282 A KR 1019940001282A KR 19940001282 A KR19940001282 A KR 19940001282A KR 940018999 A KR940018999 A KR 940018999A
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semiconductor
jfet1
bip1
doped
doping material
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KR1019940001282A
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Korean (ko)
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KR100278424B1 (en
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리트윈 안드레즈
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에르링 블롬메, 타게 뢰브그렌
테레포오낙티이에보라겟 엘엠 엘리크썬(Telefonaktiebolaget Lm Ericsson)
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Priority claimed from SE9300210A external-priority patent/SE500814C2/en
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Publication of KR940018999A publication Critical patent/KR940018999A/en
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Publication of KR100278424B1 publication Critical patent/KR100278424B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors

Abstract

실리콘 기판(1)은 절연실리콘 산화층(2)과, 매우 약하게 음으로 도프(n)된 모노크리스탈라인 실리콘 웨이퍼(3)를 운반한다. 소자부분(4)은 웨이퍼에서 절연층(5)에 의해 제한된다. 소자부분의 쌍극 트랜지스터((BIPI)을 양으로 도프(PBB1)을 양으로 도프(P)된 베이스 접속(B1)과 높게 음으로 도프(n+)된 에미터(E1)를 구성한다. 트랜지스터(BIP1)는 이 베이스부분(B) 아래측에 PN-접합을 지니고 있으며 매우 높게 음으로 도프(n+)된 드레인접속(D1)을 지닌 전계효과 트랜지스터(JFET1)와 직렬로 접속되어 있다. 소자부분(4)은 매우 약하게 도프되어 있으며, PN-접합(9)에서 실리콘 산화층(2)까지의 거리가 작아, 전압(VE,VB,VD)를 트랜지스터(BIP1,JFET1)에 인가할때, 부분(DP1)은 전하 방송자가 쉽게 공핍이 된다. 이것은 베이스(B)와 드레인접속(D1) 사이의 전류의 항복을 방지한다. 트랜지스터(BIP1,JFET1)은 높은 전압에 견디며, 상응하는 전에 공지된 트랜지스터가 필요한 기판(1)의 공간이 반에 불과하다.The silicon substrate 1 carries an insulating silicon oxide layer 2 and a very weakly negatively doped (n) monocrystalline silicon wafer 3. The device portion 4 is limited by the insulating layer 5 at the wafer. A bipolar transistor (BIPI) of the device portion constitutes a base connection (B1) positively doped (PBB1) and a highly negatively doped (n + ) emitter (E1). BIP1) has a PN-junction underneath this base portion B and is connected in series with a field effect transistor JFET1 with a very high negatively doped (n + ) drain connection D1. (4) is very lightly doped, and the distance from the PN junction 9 to the silicon oxide layer 2 is small, when the voltages V E , V B , V D are applied to the transistors BIP1, JFET1. The part DP1 is easily depleted by the charge broadcaster, which prevents the breakdown of the current between the base B and the drain connection D1.The transistors BIP1 and JFET1 withstand high voltage and are known before. Only half of the space of the board | substrate 1 in which the transistor is needed is needed.

Description

높은 항복 전압을 지닌 얇은 능동층의 반도체 장치(A SEMICONDUCTOR DEVICE IN A THIN ACTIVE LAYER WITH HIGH BREAK-DOWN VOLTAGE)A SEMICONDUCTOR DEVICE IN A THIN ACTIVE LAYER WITH HIGH BREAK-DOWN VOLTAGE

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 쌍극 트랜지스터와 전계 효과 트랜지스터의 단면도.1 is a cross-sectional view of a bipolar transistor and a field effect transistor.

Claims (4)

항복 전압을 지닌 얇은 능동층에 있으며, 전기장 세기(ED)를 감소시키는 전하 반송자 공핍부분(DP1;DP2,DP3)를 지닌 반도체 장치는 반도체 몸체 (1,2,4a;21,22,24a,24b)와; 이 반도체 몸체에 의해 운반되며 부분이 제1형태의 도핑재료(n)로 약하게 도프된 반도체 재료의 소자부분(4;24)과; 이 반도체 몸체로 부터의 소자부분(4;24)의 하면을 제한하는 절연층(2;22)과; 반도체 몸체 (1,2,4a;21,22,24a,24b)와 접촉하는 소자부분(4;24)의 나머지 면을 따라 연장된 전기 제한분리층(5;10;25)과; 제1형태의 도핑재료와는 달리 제2형태 도핑재료(P)의 농도가 매우 낮으며, 소자부분과 상면에서 연장한 소자부분(4;24)에 있는 칩상부분(B;B3;G3)과; 나머지 부분의 소자부분에서 상기 부분을 제한하는 칩상부분의 면에 형성된 PN-접합(9;29)과; 이 소자부분(4;24)에 형성된 하나 이상의 반도체 소자(BIP1,JFET1;BIP2,JFET2)와; 이 소자부분(4;24)에 형성된 두개 이상의 전기접속(8;26)을 포함하며, 감소한 전기장 세기의 부분(DP1;DP2,DP3)은 전기 접속(8;26)에 인가된 전기 전압 (VE,VB,VD)에 의해 전하 반송자가 공핍되며, 제1전하 반송자 공핍부분(DP1;DP2)은 PN-접합(9;29)에서 절연층(2;22)까지, 적어도 칩상부분(B;B3;G3)의 부분 아래로 연장되어 있는 것에 있어서, 반도체 소자는 제2반도체 소자(JFET1;JFET2)에 직렬로 접속된 쌍극 트랜지스터(BIP1;BIP2)를 포함하여, 칩상부분을 쌍극 트랜지스터(BIP1;BIP2)의 베이스부분(B;B3)를 포함하며;베이스부분(B;B3)은 제1형태의 도핑재료로 높게 도프(n+)되어 있으며, 전기접속(8;26)중 하나에 접속된 에미터부분을 포위하며;베이스부분(B;B3;은 제2형태의 도핑재료로 높게 도프(P+)되어 있으며 다른 전기 접속에 접속된 베이스 접속부분(B1;B2)은 직렬로 접속된 제2소자(JFET1;JFET2)용 접속부분(G1;G2)을 포함하며; 제2반도체 소자(JFET1;JFET2)는 제3전기접속(8;26)을 지닌 소자부분(4;24)의 나머지 부분에 높게 도프(n+)된 접속부분(D1;D2)을 지니고 있어서, 제1공핍부분(DIP1;DP2)의 전기장 세기(ED)가 반도체 재료용 항복장 세기(ECR) 이하가 되는 것을 특징으로 하는 반도체 정치.The semiconductor device, which is in a thin active layer with a breakdown voltage and has a charge carrier depletion portion DP1; DP2, DP3, which reduces the electric field strength E D , is a semiconductor body (1, 2, 4a; 21, 22, 24a). , 24b); An element portion 4; 24 of the semiconductor material carried by the semiconductor body and partially doped with the doping material n of the first form; An insulating layer (2; 22) for limiting the lower surface of the device portion (4; 24) from the semiconductor body; An electrical limiting isolation layer (5; 10; 25) extending along the other side of the device portion (4; 24) in contact with the semiconductor bodies (1, 2, 4a; 21, 22, 24a, 24b); Unlike the doping material of the first form, the concentration of the doping material P of the second form is very low, and the chip top portions B; B3; G3 in the element portion and the element portion 4; ; A PN-junction (9; 29) formed on the surface of the chip portion that restricts the portion in the element portion of the remaining portion; One or more semiconductor devices BIP1, JFET1; BIP2, JFET2 formed in the device portion 4; 24; Two or more electrical connections 8; 26 formed in the element portions 4; 24, the portions DP1; DP2, DP3 of reduced electric field strength being the electrical voltages V applied to the electrical connections 8; 26. The charge carriers are depleted by E , V B , and V D , and the first charge carrier depletion portions DP1 and DP2 extend from the PN junction 9; 29 to the insulating layer 2; In extending below the portion of (B; B3; G3), the semiconductor element includes a bipolar transistor (BIP1; BIP2) connected in series to the second semiconductor element (JFET1; JFET2), and the chip-shaped portion is formed on the dipole transistor. A base portion (B; B3) of (BIP1; BIP2); the base portion (B; B3) is highly doped (n + ) with a doping material of the first type, and one of the electrical connections (8; 26) Surrounds the emitter portion connected to the base portion; base portion (B; B3) is highly doped (P + ) with the doping material of the second type, and base connection portion (B1; B2) connected to the other electrical connection is in series Connected second A connecting portion G1; G2 for the ruler JFET1; JFET2; the second semiconductor element JFET1; JFET2 is connected to the remaining portion of the device portion 4; 24 having the third electrical connection 8; 26. It has a highly doped (n + ) connection portion (D1; D2), the electric field strength (E D ) of the first depletion portion (DIP1) DP2 is less than the yield strength (E CR ) for semiconductor materials Semiconductor politics. 제1항에 있어서, 제2반도체 소자(JFET1;JFET2)는 전계 효과 트랜지스터이고, 상기 트랜지스터의 접속부분(D1,D2)은 제1형태의 도핑재료(n)로 도프되어 있는 것을 특징으로 하는 반도체 장치.2. A semiconductor according to claim 1, wherein the second semiconductor elements JFET1 and JFET2 are field effect transistors, and the connection portions D1 and D2 of the transistors are doped with a doping material n of the first type. Device. 제1항 또는 제2항에 있어서, 분리층(25)은 소자부분(24)의 대향측에서 두개가 서로 대항하는 절연벽을 지니는데 있어서, 칩상부분은 절연분리층(25)의 서로 대향하는 벽을 따라 연장한 두개의 돌출부(G3)를 지니며, 제2전하 반송자 공핍부분(DP3)은 이 돌출부(G3) 사이에 연장되어 있는 것을 특징으로 하는 반도체 장치.The isolation layer (25) according to claim 1 or 2, wherein the isolation layer (25) has an insulating wall that opposes each other on the opposite side of the device portion (24), wherein the chip-shaped portions face each other of the insulation isolation layer (25). A semiconductor device, characterized in that it has two protrusions (G3) extending along the wall, and the second charge carrier depletion portion (DP3) extends between the protrusions (G3). 제3항에 있어서, 베이스부분(B3)과 인접한 돌출부(G3)의 단은 상기 돌출부의 타단 보다 더 큰 교차 폭으로 하는 것을 특징으로 하는 반도체 장치.4. A semiconductor device according to claim 3, wherein the end of the protrusion (G3) adjacent to the base portion (B3) has a crossing width larger than the other end of the protrusion. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001282A 1993-01-25 1994-01-25 Thin active layer semiconductor device with high breakdown voltage KR100278424B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9300210A SE500814C2 (en) 1993-01-25 1993-01-25 Semiconductor device in a thin active layer with high breakthrough voltage
SE9300210-3 1993-01-25

Publications (2)

Publication Number Publication Date
KR940018999A true KR940018999A (en) 1994-08-19
KR100278424B1 KR100278424B1 (en) 2001-02-01

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KR1019940001282A KR100278424B1 (en) 1993-01-25 1994-01-25 Thin active layer semiconductor device with high breakdown voltage

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KR (1) KR100278424B1 (en)
DE (1) DE69411450T2 (en)
MY (1) MY111643A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020094588A (en) * 2001-06-12 2002-12-18 주식회사 하이닉스반도체 Semiconductor devicd and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020094588A (en) * 2001-06-12 2002-12-18 주식회사 하이닉스반도체 Semiconductor devicd and method for manufacturing the same

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Publication number Publication date
DE69411450T2 (en) 1998-11-12
KR100278424B1 (en) 2001-02-01
MY111643A (en) 2000-10-31
DE69411450D1 (en) 1998-08-13

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