JP2007035736A - Semiconductor device and electrical apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and an electrical apparatus for simultaneously realizing high-speed switching operation and reduction in energy loss, and ensuring superior resistance for concentration of current, based on the back electromotive force due to the inductance load of electrical apparatus. <P>SOLUTION: The semiconductor device 100 comprises a semiconductor layer 3 formed of a first conductivity-type wide-band gap semiconductor, a transistor cell 101T where a vertical field effect transistor 102 is formed for moving charged carrier in the thickness direction of the semiconductor layer 3, and a diode cell 31 is formed where a Schottky diode 103, formed with Schottky junction of a Schottky electrode 9 to the semiconductor layer 3. On the semiconductor layer 3, a plurality of square sub-regions 101 are defined in the plan view, through an arrangement such that sub-regions are allocated in the two directions crossing with each other with virtual boundary lines. Moreover, the transistor cell 101T formed of the remaining portions of the sub-regions 101 and the diode cell 31 formed of the cut-away portions are also defined, in such a manner as to cut away the four corners of sub-regions 101. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an electric device, and more particularly, to an improvement technique of a power semiconductor device used for inverter control of various electric devices.

  Wide band gap semiconductors (for example, silicon carbide; SiC) have attracted attention as semiconductor materials that break the limits of existing Si power field effect transistors (hereinafter referred to as “Si-MISFETs”) from the viewpoint of reducing energy loss. .

  The drift region of a power field effect transistor (hereinafter referred to as “SiC-MISFET”) made of an SiC semiconductor has a high bandgap because it has a high band gap, and this ensures a constant breakdown voltage. However, it is possible to reduce the thickness of the drift region that plays an important role in improving conduction loss due to a decrease in on-resistance (Ron) per unit area of the semiconductor device.

  That is, since the on-resistance of the SiC-MISFET uses a wide band gap semiconductor, the Si-MISFET has a resistance value that is much smaller than the on-resistance of the Si-MISFET and has a resistance value lowered by an order of magnitude or more. -Expected to be lower than the on-resistance of the IGBT, which makes it possible for the SiC-MISFET to suppress the heat generation during its on-operation and keep the conduction loss low compared to these existing switching elements.

  Moreover, since the switching performance of such a SiC-MISFET is a unipolar device, it is advantageous in speeding up compared to a bipolar device (for example, IGBT).

  However, even in the SiC-MISFET, in the switching from the ON state of the parasitic diode at the time of reverse bias to the OFF state of the SiC-MISFET due to the parasitic diode constituted by the P-type region and the n-type region PN junction in the semiconductor device There may be a delay in reverse recovery time.

  For example, when a positive voltage as a back electromotive force generated by an inductance load when the switching element is turned off is applied to the source electrode, holes as minority carriers are injected into the n-type region via the parasitic diode, The reverse recovery time will be delayed.

  Accordingly, the inventors of the present invention have previously developed a semiconductor device in which the semiconductor region of the Schottky diode and the drift region of the MISFET are made of SiC material and the Schottky diode and the MISFET are incorporated as one chip (Patent Document 1). reference).

  According to the semiconductor device described in Patent Document 1 (hereinafter referred to as “conventional semiconductor device”), an n-type epitaxial growth layer is formed on the surface of an n-type epitaxial growth layer existing between P-type wells of adjacent MISFETs. A metal electrode for Schottky bonding is disposed. In this conventional semiconductor device, even when a positive voltage is applied to the source electrode and holes as minority carriers are injected into the n-type region, a shot is performed at the moment when the negative voltage is applied to the source electrode. The key diode can quickly absorb minority carriers (holes), and the reverse recovery time by the parasitic diode can be shortened.

  In this conventional semiconductor device, the forward rising voltage (about 1 V) of the Schottky diode is lower than the forward rising voltage (3 V) of the parasitic diode (PN junction). As a result, when a positive voltage is applied to the source electrode, a forward current flows preferentially to the Schottky diode (Schottky electrode has the same voltage as the source electrode), resulting in minority carriers via the parasitic diode. Injection is less likely to occur.

Furthermore, since this conventional semiconductor device can integrate the Schottky diode and the MISFET on a single chip, the space of the semiconductor device can be reduced.
JP 2002-203967 A (FIGS. 1 and 2)

  By the way, when the conventional semiconductor device is used as a switching element constituting a specific inverter power supply circuit (for example, an inverter power supply circuit for a three-phase motor such as an air conditioner compressor), such a switching element is put to practical use. The following issues have become apparent.

  The layout area of the Schottky junction metal electrode (Schottky electrode) does not cause a major obstacle to speeding up switching of the semiconductor device, but a forward voltage is applied to both the parasitic diode and the Schottky diode existing in the MISFET. Considering the situation where current flows, it can be said that this is an important design item from the viewpoint of securing an appropriate current-carrying capacity.

  Actually, when the technique described in Patent Document 1 is applied to an inverter power supply circuit for a three-phase motor, the current concentrated on the Schottky electrode is triggered by the counter electromotive force based on the inductance load when the switching element is turned off. The possibility that the resulting element was destroyed was found.

  In addition, the Schottky electrode described in Patent Document 1 is arranged in a grid pattern connected to a thin wiring so as to surround the field effect transistor region in a plan view. For this reason, the disconnection of the fine wiring is likely to be induced during the manufacturing of the semiconductor device, which may be a cause of deterioration in the manufacturing yield of the semiconductor device.

  The present invention has been made in view of such circumstances, and is a semiconductor device that can achieve both high-speed switching operation and energy loss reduction, and has excellent current concentration tolerance based on counter electromotive force caused by an inductance load of an electric device. And to provide electrical equipment.

  In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor layer made of a wide band gap semiconductor of a first conductivity type and a vertical field effect transistor that moves charge carriers in the thickness direction of the semiconductor layer. And a diode cell in which a Schottky diode having a Schottky junction formed on the semiconductor layer is formed, and the semiconductor layer intersects with each other by a virtual boundary line in a plan view. A plurality of quadrangular sub-regions arranged in two directions, and the transistor cell and the cut-out portion comprising the remainder of the sub-region so as to cut out the four corners of the sub-region A device in which the diode cell is divided.

  The plurality of sub-regions may be arranged in a matrix in two directions orthogonal to each other.

  Further, the corner of the sub-region may be cut out linearly.

  Further, the diode cell may be partitioned into a quadrangular shape having four sides as boundaries with the transistor cell.

  According to the semiconductor device configured as described above, a field effect transistor (switching element) made of a wide band gap semiconductor and a Schottky diode (built-in diode) using a wide band gap semiconductor are used. High speed can be realized as compared with a bipolar device (IGBT).

  In addition, the on-resistance of a field effect transistor made of a wide band gap semiconductor is sufficiently smaller than that of an existing switching element (Si-MISFET or IGBT), thereby suppressing heat generation during on-operation of this field effect transistor. Therefore, conduction loss can be kept low.

  Furthermore, since the Schottky electrode can occupy almost the entire area of the diode cell, for example, when the switching element is turned off, the back electromotive force based on the inductance load of the three-phase motor is used as a trigger. It is possible to appropriately deal with the destruction of the element due to the current concentrated on the Schottky electrode. Therefore, the Schottky electrode is preferably formed in a quadrangular shape so as to occupy almost the entire area of the diode cell.

The transistor cell may be divided into an octagon having a boundary line between the boundary line and the diode cell as a side. Here, the field effect transistor is a second conductive layer provided on a surface of the semiconductor layer. A well of a type, a region of a first conductivity type provided inside the well, a drift region as the semiconductor layer excluding the well and the region, and provided in contact with the region and the well A first source / drain electrode; a gate electrode disposed on the well via an insulating layer; and a second source / drain electrode connected ohmic to the back surface of the drift region. It may be a thing.

  Note that the expression “source / drain electrode” means that such an electrode can function as a source electrode or a drain electrode of a transistor.

  The ratio of the area of the transistor cell in plan view to the area of the subregion in plan view may be more than 0.5 and 0.99 or less. In other words, the ratio of the area of the diode cell in plan view to the area of the sub-region in plan view may be more than 0.01 and 0.5 or less.

  Even when the ratio of the area of the diode cell in plan view to the area of the sub-region in plan view is set to 0.01 (1%) and 0.5 (50%), the conventional PN junction diode While it is demonstrated that the loss can be reduced as compared with the semiconductor device adopting the semiconductor device, the current value flowing through the Schottky diode is likely to exceed the allowable current value when this value is in the range of 0.01 or less. In the range exceeding 0.5, the on-resistance tends to increase due to a decrease in the area occupancy of the field effect transistor.

  Further, the present invention can be applied to a semiconductor device that constitutes an inverter power supply circuit of the AC drive device, for example, a device in which the semiconductor device is incorporated as an arm module.

  According to such an electrical device, the conduction loss of the semiconductor device corresponds to the value obtained by multiplying the current by the voltage (current × voltage), so that the forward voltage of the Schottky diode is larger than the forward voltage of the conventional PN junction diode. Can be kept low, the loss of the semiconductor device is improved as compared with an existing semiconductor device employing a PN junction diode.

  Furthermore, the switching speed of the semiconductor device from the on-state to the off-state is fast, which can reduce the switching loss.

  The voltage applied to the parasitic diode of the field effect transistor and the Schottky diode based on the back electromotive force generated by the inductance load in the AC drive device is larger than the rising voltage in the forward direction of the Schottky diode, and The parasitic diode may be configured to have a voltage lower than the forward voltage in the forward direction.

  Moreover, an example of the AC drive device is an AC motor driven by the inverter power supply circuit, and, for example, a compressor of an air conditioner is driven by the AC motor.

  ADVANTAGE OF THE INVENTION According to this invention, the high-speed switching operation | movement and energy loss reduction can be achieved, and the semiconductor device and electric equipment excellent in the current concentration tolerance based on the counter electromotive force by the inductance load etc. of an electric equipment are obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a plan view showing a configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device at a portion along line AA in FIG. In the following description, “n” or “p” indicates a conductivity type, and the layer or region in which these are written means that electrons or holes are carriers. “+” Means that the impurity concentration is high, and “−” means that the impurity concentration is low.

  As shown in FIGS. 1 and 2, in a plan view of semiconductor device 100, SiC layer 3 (semiconductor layer) intersects each other by a boundary line 30 including virtual horizontal boundary line 30a and vertical boundary line 30b (here, orthogonal). A plurality of quadrangular (here, square) sub-regions 101 that are equally divided (equal area) in a matrix form in two directions are arranged.

  Further, a transistor cell 101T in which a vertical field effect transistor 102 (hereinafter referred to as “SiC-MISFET 102”; see FIG. 2) that moves electrons in the thickness direction of the SiC layer 3 is formed in a quadrangular shape (here, a square shape). ) Are formed so as to cut out the four corners of the sub-region 101, and are joined to the SiC layer 3 (drift region 3a; see FIG. 2). A Schottky electrode 9 is disposed in the diode cell 31. That is, the transistor cell 101T that is the remaining portion of the sub-region 101 obtained by cutting out the four corners of the sub-region 101 and the diode cell 31 that is formed of the cut-out portion are partitioned by the SiC layer 3. .

  Note that the boundary line 30 indicated by a two-dot chain line in FIG. 1 is drawn for convenience so as to pass through the center of the sub-regions 101 that are in contact with each other for the purpose of facilitating the explanation of the scope of the claims and the description. The imaginary line is not actually present in the product embodying the present technology, and the illustration of the boundary line 30 is appropriately changed depending on the shape of the SiC-MISFET 102.

  However, even if the sub-region 101 is partitioned by such imaginary lines, the sub-region 101 has a SiC-MISFET 102 formed for each sub-region 101, and its extension is easily understood from FIG. Can be specified by the shape of the gate electrode 8.

  More specifically, as an arrangement example of the transistor cell 101T and the diode cell 31, as shown in a partially enlarged view of FIG. 1, adjacent transistor cells 101T at a base point 32 on a boundary line 30 between adjacent transistor cells 101T are arranged. The diode cells 31 between the adjacent transistor cells 101T are separated from each other.

  Adjacent transistor cells 101T are configured to be separated from each other so as to cut out the sub-region 101T from the base point 32 on the boundary line 30 to the boundary line 30 in the diagonally reverse direction (inclination angle: 45 °). Therefore, the diode cell 31 is divided into rectangles (squares) each having four sides of the boundary line with the transistor cell 101T and four base points 32 having four corners. On the other hand, the transistor cell 101T has a boundary line with the diode cell 31 and a virtual boundary line 30 as sides, and each of the two base points 32 scattered on each of the four virtual boundary lines 30 has eight corners. Is divided into octagons.

  With the arrangement example of the transistor cells 101T and the diode cells 31, the diode cells 31 can be evenly and uniformly arranged surrounded by the transistor cells 101T. As a result, the total occupied surface area of the diode cells 31 (including the Schottky diode 103) The surface area of the region is appropriately adjusted with respect to the total occupied surface area of the transistor cell 101T (surface area of the region including the SiC-MISFET 102).

  More specifically, in this semiconductor device 100, as shown in FIG. 1, the width dimension of the sub-region 101 is set to “L”, and the direction of the boundary line 30 (lateral boundary line 30 a in FIG. 1) on one side of the diode cell 31. When the width dimension in the direction parallel to L is S, the relational expression between L and S is L / 10√2 <S ≦ L / in view of the balance with the conduction loss of the semiconductor device 100 described later. The ratio of the occupied surface area of the transistor cell 101T and the diode cell 31 is set so as to be in the range of 2.

The SiC-MISFET 102 includes an n ⁺ -type semiconductor substrate 2 made of SiC semiconductor and a predetermined surface of the semiconductor substrate 2 by an epitaxial growth method, as shown in the partial enlarged view of FIG. 1 and FIG. An n ⁻ -type SiC layer 3 formed to a thickness of 10 μm (for example, 10 μm), and an octagonal shape (part of FIG. 1) provided immediately below the surface of the SiC layer 3 and implanted with an acceptor such as aluminum ions. a p-type well 4 of the reference enlarged view), in the region of the p-type well 4, the nitrogen ions donors were injected, the n ⁺ -type octagonal and circular in plan view (see partially enlarged view of FIG. 1) Around the periphery of the source region 5, the drift region 3 a composed of portions other than the source region 5 and the p-type well region 4 of the SiC layer 3, and the source region 5 of the p-type well 4 The channel region 4c, which is an octagonal and annular shape (see the partially enlarged view of FIG. 1), which covers the channel region 4c, extends across the outer periphery of the source region 5 and extends inside the source region 5. A gate insulating film 7 made of SiO ₂ material deposited so as to cover a part of the source region 5, and an aluminum metal (Al) formed over the entire surface of the gate insulating film 7 so as to face the channel region 4c. ) And the central portion of the p-type well 4 (portion located in the central opening of the source region 5), and extends inside the source region 5 across the inner periphery of the source region 5. A part of the source region 5 is covered with an octagon and an annular shape, and is connected ohmically to the octagonal (see partially enlarged view of FIG. 1) source electrode 6 and the back surface of the drain region 3a in plan view. It is configured to include a drain electrode 10 formed on the entire back surface of the sea urchin semiconductor substrate 2, a. For example, nickel metal (Ni) is used as the material of the drain electrode 10 and the source electrode 6.

  As can be easily understood from FIGS. 1 and 2, a large number of SiC-MISFETs 102 are integrated and arranged in one chip in common, sharing the drift region 3 a and the drain electrode 10.

Here, as indicated by a dotted arrow 201 in FIG. 2, electrons moving from the n ⁺ -type source region 5 to the drain electrode 10 have a portion that moves in the lateral direction (horizontal direction) in the vicinity of the p-type well 4. Therefore, the surface area of the p-type well 4 is configured to be smaller than the surface area of the sub-region 101 in order to secure such an electron movement space.

  Gate insulating film 7 and gate electrode 8 are formed over the entire surface of SiC layer 3 except for contact holes H1 and H2. On the other hand, the contact hole H1 is formed in the gate insulating film 7 so as to be located in the transistor cell 101T, and the source electrode 6 is provided therein.

  The source electrode 6 and the drain electrode 10 and the semiconductor (SiC layer 3) are ohmically connected by the source region 5, the p-type well 4, and the semiconductor substrate 2, respectively.

  Here, the SiC layer 3 (SiC band gap: 3.02 eV) is a wide band cap semiconductor wider than the band cap of a silicon semiconductor (band gap: 1.11 eV) or a GaAs semiconductor (band gap: 1.43 eV). It is configured.

  A wide band gap semiconductor is a semiconductor whose energy band gap, which is a material parameter that characterizes the properties of a semiconductor, is larger than that of a silicon semiconductor or GaAs semiconductor. In this specification, for example, a band gap of 2 eV or more is used. The semiconductor materials are collectively referred to.

Examples of the wide band gap semiconductor material include group nitrides such as GaN (band gap: 3.39 eV) or AlN (band gap: 6.30 eV), and diamond in addition to SiC.

  Further, as shown in FIG. 2, the Schottky diode 103 is formed in the gate insulating film 7 so that the contact hole H2 is located in the diode cell 31, and the SiC layer 3 (drift of the diode cell 31) is formed therein. The Schottky electrode 9 (anode side) made of Ni having a rectangle (here square) in the plan view shown in FIG. 1 is formed so as to cover the entire surface of the region 3a). The rectangular Schottky electrode 9 may have rounded corners from the viewpoint of avoiding electric field concentration.

  Here, since the current from the Schottky electrode 9 toward the drain electrode 10 flows in the vertical direction (vertical direction) over the entire area of the diode cell 31, the surface area of the Schottky electrode 9 is almost equal to the surface area of the diode cell 31. They are equally configured to allow a large amount of current to flow.

  Of course, in order to further increase the area of the Schottky electrode 9, the Schottky electrode 9 is placed on the surface of the SiC layer 3 corresponding to these boundary lines 30 along the direction of the four boundary lines 30 connected to the diode cell 31. The plurality of square Schottky electrodes 9 may be connected to each other via Schottky electrodes (not shown) arranged along the boundary line 30.

  The drain electrode 10 extends from the transistor cell 101T to the back surface of the semiconductor substrate 2 facing the diode cell 31 so as to straddle the diode cell 31. A voltage is applied to the semiconductor (SiC layer 3) on the cathode side of the Schottky diode 103 via the drain electrode 10.

  In addition, the electrical connection between the source electrodes 6 and the electrical connection between the source electrode 6 and the Schottky electrode 9 are performed by connecting the first wiring 11 (for example, an appropriate interlayer insulating layer (not shown) and an appropriate contact hole (not shown). The source electrode 6 and the Schottky electrode 9 are connected to the ground potential (minus voltage) of the power source via the source terminal S provided at an appropriate position of the semiconductor package (not shown). ) Side is connected.

  That is, the Schottky electrode 9 is electrically connected to the source electrode 6 by the first wiring 11.

  Further, in a plan view, the gate electrode 8 formed in a cross-beam shape over almost the entire surface of the SiC layer 3 except for the regions of the contact holes H1 and H2 (see FIG. 2) is connected to the gate wiring 12 (for example, the interlayer insulating layer). A predetermined control signal voltage is applied between the source electrode 6 through a layer, an appropriate contact hole (not shown), and a gate terminal G provided at an appropriate position of the semiconductor package.

  Further, the drain electrode 10 is connected to the switching voltage (plus voltage) side of the power supply via the drain terminal D provided at an appropriate position of the semiconductor package.

  In the SiC-MISFET 102 of the semiconductor device 100 as described above, by applying a positive voltage to the gate electrode 8 with respect to the source electrode 6, electrons are attracted to the channel region 4c and the portion is inverted to n-type, As a result, a channel is formed, and thereby the SiC-MISFET 102 is turned on. Electrons traveling from the source region 5 to the drain electrode 10 through the channel region 4c and the SiC layer 3 mainly move along a path indicated by a dotted arrow 201 in FIG. 2, and as a result, the drift current is generated in the SiC layer 3. Flows vertically in the interior.

Further, a parasitic diode (a diode based on a PN junction between the p-type well 4 and the n ⁻ -type SiC layer 3) and a Schottky diode 103 (between the source terminal S and the drain terminal D) existing in the SiC-MISFET 102. For example, when a forward voltage based on a counter electromotive force due to an inductance load of a three-phase motor is applied, the forward rising voltage (about 1 V) of the Schottky diode 103 is equal to the forward rising voltage of the parasitic diode (PN junction) ( 3V), it is possible to appropriately avoid the injection of minority carriers (holes) into the SiC layer 3 by flowing a forward current through the Schottky diode 103 preferentially.

  For the same reason, when an instantaneous overvoltage such as a surge voltage is applied to the semiconductor device 100, it is possible to reduce the overvoltage by preferentially causing a leakage current due to the overvoltage to flow through the Schottky diode 103. As a result, the dielectric breakdown of the SiC-MISFET 102 can be prevented beforehand.

  Further, by adopting a configuration in which the diode cell 31 (Schottky electrode 9) is provided in a portion where the four corners of the sub-region 101 are notched, the dielectric strength performance of the semiconductor device 100 is improved as described below.

  When a voltage is applied between the source electrode 6 and the drain electrode 10 provided on the front and back surfaces of the semiconductor substrate 2 to keep the SiC-MISFET 102 in the off state, the front surface (source electrode 6) and the back surface of the semiconductor substrate 2 A high voltage is applied between (drain electrode 10). In such a state, it is required as a basic performance of the power device not to cause dielectric breakdown based on a high voltage.

  Here, it is assumed that a plurality of rectangular sub-regions 101 partitioned in a matrix form in two directions intersecting each other by a virtual horizontal boundary line 30a and a vertical boundary line 30b are formed in a transistor cell without providing the diode cell 31. In the case of 101T, when the high voltage is applied, the electric field concentration based on the high voltage increases at the four corners of the sub-region 101, particularly in the vicinity of the intersection of the horizontal boundary line 30a and the vertical boundary line 30b. In the vicinity of this intersection, the gate electrode 8 is disposed on the surface of the drift region 3 a with the gate insulating film 7 interposed therebetween, so that dielectric breakdown is easily generated between the gate electrode 8 and the gate electrode 8. That is, such breakdown of the semiconductor device often occurs near the intersection of the vertical and horizontal boundary lines 30b and 30a.

  In contrast, in the semiconductor device 100 according to the present embodiment, as described above, the four corners of the sub-region 101 are notched, and the Schottky electrode 9 is introduced here, so that the dielectric breakdown easily occurs ( The vicinity of the intersection) is covered with a Schottky electrode 9. With this configuration, the semiconductor device 100 can hardly withstand breakdown with the gate electrode 8, so that the withstand voltage can be increased. Specifically, according to the semiconductor device 100 according to the present embodiment, the dielectric strength (about 600 V) of the conventional semiconductor device in which the four corners of the sub-region 101 are not cut out and this portion is the transistor cell 101T is higher. An insulation breakdown voltage (about 700 V) was obtained.

  Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described with reference to FIG.

  However, illustration in the middle of each manufacturing process is omitted here. For this reason, in the description of this manufacturing method, the reference numerals of the constituent parts in the course of the manufacturing process are substituted with the reference numerals of the finished product shown in FIG. 2 for convenience.

First, the semiconductor substrate 2 having an [11-20] direction 4 degree off-cut surface of an n ⁺ -type 4H—SiC (0001) Si surface doped with nitrogen so that the nitrogen concentration becomes 3 × 10 ¹⁸ cm ^−3. Is prepared.

Next, after the semiconductor substrate 2 is cleaned, a SiC layer 3 as a nitrogen-doped n ⁻ type epitaxial growth layer adjusted to a concentration of 1.3 × 10 ¹⁶ cm ^{−3 is formed on the} off-cut surface by a CVD method. Is adjusted to a thickness of 10 μm.

Then, a mask (not shown) that opens an appropriate position on the surface of the SiC layer 3 is arranged, and four stages of ion energies within a range of 30 to 700 keV are appropriately selected toward the surface of the SiC layer 3, and 2 Aluminum ions are implanted through the opening at a dose of × 10 ¹⁴ cm ^-2 concentration. By this ion implantation, a p-type well 4 having a depth of about 0.8 μm is formed in an island shape on the surface layer of the SiC layer 3.

Then, using another mask (not shown) that opens an appropriate position on the surface of the p-type well 4, the energy of the p-type well 4 is 30 to 180 keV and is 1.4 × 10 ¹⁵ cm ^−2. Nitrogen ions are implanted at a concentration dose, and an n ⁺ -type source region 5 is formed.

  Subsequently, the semiconductor substrate 2 is exposed to an Ar atmosphere and kept at a temperature of 1700 ° C. and subjected to heat treatment for about 1 hour, and the ion implantation region is activated.

  Next, the semiconductor substrate 2 is wet-oxidized for 3 hours while maintaining a temperature of 1100 ° C. in an oxidation treatment furnace. By this oxidation treatment, a silicon oxide film having a thickness of 40 nm (finally, this film functions as the gate insulating film 7) is formed on the entire surface of the SiC layer 3.

  Contact holes H1 and H2 are formed in the silicon oxide film by patterning using a photolithography technique and an etching technique.

  A source electrode 6 made of Ni is provided on the surface of the SiC layer 3 inside the contact hole H 1, and a drain electrode 10 made of Ni is provided on the back surface of the semiconductor substrate 2. After the Ni layer is deposited, an appropriate heat treatment is performed, whereby the source region 5 and the p-type well 4 and the semiconductor substrate 2 are formed between the electrodes 6 and 10 and the semiconductor (SiC layer 3). Is connected through an ohmic connection.

  A gate electrode 8 and a gate wiring 12 made of Al are selectively formed on the surface of the silicon oxide film.

  Further, a Schottky electrode 9 made of Ni is selectively patterned on the surface of the SiC layer 3 exposed at the bottom of the contact hole H2.

  In this way, the semiconductor device 100 (700V withstand voltage, current value 20A rating at 3mm □) is obtained.

  Here, an example will be described in which the semiconductor device 100 according to the present embodiment is applied to an inverter power supply circuit as a power electronics control device of an electric device.

  FIG. 3 is a diagram showing a configuration example of an inverter motor drive system in which the semiconductor device according to the present embodiment is applied to drive a three-phase motor of an air conditioner compressor.

  According to FIG. 3, the inverter motor drive system 105 includes a three-phase inverter power supply circuit 106 and a three-phase (AC) motor 107 (AC drive device).

  The three-phase inverter power supply circuit 106 includes six upper and lower arm modules 100H, L configured by integrating a circuit formed by connecting the SiC-MISFET 102 and the Schottky diode 103 in antiparallel to one chip. (Semiconductor device).

  More specifically, the three-phase inverter power supply circuit 106 has a source terminal S (see FIG. 2) of the upper arm module 100H and a drain terminal D (see FIG. 2) of the lower arm module 100L connected in series in two upper and lower stages. Thus, three arm module pairs 108 (hereinafter referred to as “phase switching circuit 108”) are connected in parallel.

  In each of the phase switching circuits 108, the drain terminal D of the upper arm module 100H is connected to the high-voltage power supply terminal 21, and the source terminal S of the lower arm module 100L is connected to the ground terminal 22.

  Further, each of the connection portions (middle points) 110 connecting the source terminal S of the upper arm module 100H and the drain terminal D of the lower arm module 100L is connected to each of the three input terminals 20 of the three-phase motor 107. Yes.

  Note that the gate terminals G (see FIG. 2) of the upper and lower arm modules 100H and 100L are connected to a control circuit (not shown) including an appropriate inverter microcomputer.

  In the inverter motor drive system 105, the ON / OFF timing of the upper arm module 100H and the lower arm module 100L provided in each of the phase switching circuits 108 is adjusted to correspond to the midpoint of each of the phase switching circuits 108. It is possible to modulate the voltage of the connecting portion 110 to be connected.

  In short, if the lower arm module 100L is turned on and the upper arm module 100H is turned off, the voltage of the connection portion 110 becomes the ground potential, the lower arm module 100L is turned off, and the upper arm module 100H is turned on. Then, a predetermined high voltage is obtained.

  In this way, the power supply frequency of the three-phase motor 107 fed by the three-phase inverter power supply circuit 106 via the connection portion 110 can be changed according to the on / off switching frequency of the upper and lower arm modules 100H and 100L. Thus, the motor rotation speed of the three-phase motor 107 can be changed freely, continuously, and efficiently.

  According to such an inverter motor drive system 105, since the SiC-MISFET 102 (switching element) and the Schottky diode 103 (built-in diode) are used, the speed is increased compared to the existing bipolar device (IGBT). it can.

  Therefore, the upper and lower arm modules 100H and 100L are switched from on to off in a short time, thereby eliminating the restriction on the upper frequency limit of the three-phase inverter power supply circuit 106 and the three-phase inverter power supply circuit 106. Switching loss is improved.

  As an example of specific data, a high frequency switching operation of 100 kHz in these upper and lower arm modules 100H and 100L (700V withstand voltage, current value 20A rating at 3mm □) was confirmed, and the switching loss in this case is 5% or less. there were.

  Further, the on-resistance of the SiC-MISFET 102 is sufficiently smaller than that of existing switching elements (Si-MISFET and IGBT), thereby suppressing the heat generation during the on-operation of the SiC-MISFET 102 in the inverter motor drive system 105. Conduction loss can be kept low.

  Further, in the Schottky diode 103 built in the upper and lower arm modules 100H and 100L, since the Schottky electrode 9 can occupy the entire area of the diode cell 31 broadly, the three-phase motor when the switching element is turned off. Using the back electromotive force based on the inductance load 107 as a trigger, it is possible to appropriately deal with the element destruction caused by the current concentrated on the Schottky electrode 9.

  Next, an operation example of the upper and lower arm modules 100H and 100L in which the loss of the inverter motor drive system 105 is verified when the width dimensions “L” and “S” are changed will be described.

(When S = L / 10√2)
In the case of S = L / 10√2, the ratio of the area of the diode cell 31 in plan view to the area of the sub-region 101 in plan view is approximately 0.01.

  In other words, in this case, the ratio of the area of the transistor cell 101T in plan view to the area of the sub region 101 in plan view is about 0.99.

The on-resistance per unit area of the Schottky diode 103 in the upper and lower arm modules 100H and 100L (700V withstand voltage, current value 20A rating at 3mm □) is about ² mΩcm ² .

  Further, the SiC layer 3 located immediately below the P well 4 of the SiC-MISFET 102 does not sufficiently function as a current-carrying region as indicated by a dotted arrow 201 in FIG. 2, while being directly below the Schottky electrode 9 of the Schottky diode 103. The located SiC layer 3 functions as an energization region over the entire region. For this reason, the averaged on-resistance in terms of unit area of the SiC-MISFET 102 shows a value (10 mΩ) that is about one digit larger than that of the Schottky diode 103.

  The contact resistance between the Schottky electrode 9 and the SiC layer 3 is about two orders of magnitude smaller than the on-resistance of the Schottky diode 103, and this value can be ignored.

When the current that can be passed through the SiC-MISFET 102 and the Schottky diode 103 is estimated from the on-resistance of the SiC-MISFET 102 and the Schottky diode 103 described above, S = L / 10√2 (surface area of the diode cell 31: surface area of the sub-region 101) When the forward voltage V _f of the Schottky diode 103 is about 3 V including the forward rising voltage (about 1 V) by the Schottky barrier, the Schottky diode 103 has It becomes possible to flow a current of about 20 A / cm ^{2 in} terms of the current density of the entire device.

The voltage value (3 V) corresponds to the lowest forward voltage (that is, the voltage drop due to the junction barrier of the PN junction) when a current flows in the forward direction through the PN junction parasitic diode built in the SiC-MISFET 102. For this reason, when the forward voltage V _f is maintained at 3 V or less when a current is passed through the Schottky diode 103 in the forward direction, the current flows preferentially through the Schottky diode 103.

At this time, since the conduction loss of the upper and lower arm modules 100H and 100L corresponds to a value obtained by multiplying the current by voltage (current × voltage), the Schottky diode 103 is compared with the forward voltage V _f of the conventional PN junction diode. By keeping the forward voltage V _f of the low voltage, the loss of the upper and lower arm modules 100H and 100L is expected to be improved as compared with the existing arm module employing a PN junction diode.

  More specifically, when S = L / 10√2 is set (surface area of the diode cell 31: surface area of the sub-region 101≈1: 100), the switching speed is reduced because the off-speed increases. The loss reduction of about 2% is confirmed compared with the existing arm module adopting the PN junction diode, and even if the Schottky diode 103 occupies a small percentage (1%), the inverter motor drive system 105 The loss improvement effect is demonstrated.

However, during the continuous operation experiment of the upper and lower arm modules 100H and 100L, the operations of the upper and lower arm modules 100H and 100L may not be stable due to heat generated by the upper and lower arm modules 100H and 100L. This is presumed to be caused by the value of the current flowing through the Schottky diode 103 exceeding the allowable current value (20 A / cm ² ). For this reason, it is desirable to set S> L / 10√2.

(When S = L / 2√5)
In the case of S = L / 2√5, the ratio of the area of the diode cell 31 in plan view to the area of the sub-region 101 in plan view is 0.1.

  In other words, in this case, the ratio of the area of the transistor cell 101T in plan view to the area of the sub-region 101 in plan view is 0.90.

When S = L / 2√5 (the surface area of the diode cell 31: the surface area of the sub-region 101≈1: 10), the allowable value of the current flowing through the Schottky diode 103 is calculated in terms of the current density of the entire device. This is about 200 A / cm ² , so that the problem caused by the insufficient current allowable amount of the Schottky diode 103 is solved. In this case, a loss reduction of about 5% is confirmed as compared with an arm module employing a PN junction diode, and a sufficient loss improvement effect of the inverter motor drive system 105 is exhibited.

(When S = L / 2)
When S = L / 2, the ratio of the area of the diode cell 31 in plan view to the area of the sub-region 101 in plan view is 0.5.

  In other words, in this case, the ratio of the area of the transistor cell 101T in plan view to the area of the sub-region 101 in plan view is 0.5.

  When S = L / 2 (the surface area of the diode cell 31: the surface area of the sub-region 101 = 50: 100) is set, a loss reduction of about 1% is confirmed as compared with an arm module employing a PN junction diode. Even if the Schottky diode 103 occupies a large proportion (50%), the loss improvement effect of the inverter motor drive system 105 is exhibited.

  However, when S> L / 2 is set, an increase in on-resistance due to a decrease in the area occupancy of the SiC-MISFET is seen, and there is a concern about an increase in the losses of the upper and lower arm modules 100H and 100L. .

Further, since stable operation is expected when the current flowing through the Schottky electrode 9 is 200 to 600 A / cm ² in terms of the current density of the entire device, a desirable range of the ratio of the area is 0.1 to 0.3. It is.

  Although the SiC-MISFET has been described by taking the N-channel MISFET as an example, the semiconductor device 100 (arm module) according to the present embodiment can also be constructed using a P-channel MISFET in which the source electrode and the drain electrode are reversed. .

  In the description of the above embodiment, the example in which the gate electrode is made of aluminum metal has been described. However, the gate electrode may be made of polysilicon or molybdenum (Mo) instead. Even in the case of a polysilicon gate electrode and a molybdenum gate electrode, the same effect as described above can be obtained.

  The semiconductor device according to the present invention can achieve both high-speed switching operation and energy loss reduction, and is excellent in current concentration tolerance based on counter electromotive force due to inductance load of an electric device, for example, a high-speed inverter power supply circuit of an electric device. Applicable for use.

It is the top view which showed one structural example of the semiconductor device by embodiment of this invention. It is sectional drawing of the semiconductor device of the part along the AA line of FIG. It is the figure which showed one structural example of the inverter motor drive system which applied the semiconductor device by this Embodiment to the drive of a three-phase motor.

Explanation of symbols

2 Semiconductor substrate 3 SiC layer 4 P well 4c Channel region 5 Source region 6 Source electrode 7 Gate insulating film 8 Gate electrode 9 Schottky electrode 10 Drain electrode 11 First wiring 12 Gate wiring 20 Input terminal 21 High voltage power supply terminal 22 Ground terminal 100 Semiconductor Device 100H Upper Arm Module 100L Lower Arm Module 101 Subregion 101T Transistor Cell 30 Boundary Line 30a Horizontal Boundary Line 30b Vertical Boundary Line 31 Diode Cell 32 Base Point 102 SiC-MISFET
103 Schottky diode 105 Inverter motor drive system 106 Three-phase inverter power supply circuit 107 Three-phase motor 108 Phase switching circuit 110 Connection part G Gate terminal S Source terminal D Drain terminals H1, H2 Contact hole

Claims (12)

A semiconductor layer made of a wide band gap semiconductor of the first conductivity type;
A transistor cell in which a vertical field effect transistor for moving charge carriers in the thickness direction of the semiconductor layer is formed;
A diode cell having a Schottky diode formed by Schottky junction of a Schottky electrode to the semiconductor layer, and
In the semiconductor layer, a plurality of quadrangular sub-regions arranged in two directions intersecting each other by a virtual boundary line in a plan view are partitioned, and the four corners of the sub-region are notched so as to be cut out. A semiconductor device in which the transistor cell composed of the remaining portion of the sub-region and the diode cell composed of the notched portion are partitioned.   The semiconductor device according to claim 1, wherein the plurality of sub-regions are arranged in a matrix in two directions orthogonal to each other.   The semiconductor device according to claim 1, wherein a corner portion of the sub-region is cut out linearly.   4. The semiconductor device according to claim 3, wherein the diode cell is partitioned into quadrangular shapes having four sides as boundaries with the transistor cell. 5.   The semiconductor device according to claim 4, wherein the Schottky electrode is formed in a quadrangular shape so as to occupy substantially the entire area of the diode cell.   5. The semiconductor device according to claim 4, wherein the transistor cell is partitioned into an octagon having a boundary line between the boundary line and the diode cell as a side.   The field effect transistor includes: a second conductivity type well provided on a surface of the semiconductor layer; a first conductivity type region provided inside the well; and the semiconductor layer excluding the well and the region. A drift region, a first source / drain electrode provided in contact with the region and the well, a gate electrode disposed in the well via an insulating layer, and an ohmic contact on the back surface of the drift region The semiconductor device according to claim 1, further comprising a second source / drain electrode connected to the first and second electrodes.   2. The semiconductor device according to claim 1, wherein a ratio of the area of the transistor cell in plan view to the area of the sub-region in plan view exceeds 0.5 and is 0.99 or less.   2. The semiconductor device according to claim 1, wherein the ratio of the area of the diode cell in plan view to the area of the sub-region in plan view exceeds 0.01 and is 0.5 or less. An AC drive device and a semiconductor device according to any one of claims 1 to 9 constituting an inverter power supply circuit of the AC drive device,
An electric device in which the semiconductor device is incorporated as an arm module.   The voltage applied to the parasitic diode of the field effect transistor and the Schottky diode based on the back electromotive force generated by the inductance load in the AC drive device is larger than the rising voltage in the forward direction of the Schottky diode, and The electric device according to claim 10, wherein the electric device is configured to be smaller than a rising voltage in a forward direction of the parasitic diode. The electrical apparatus according to claim 10, wherein the AC drive device is an AC motor driven by the inverter power supply circuit.

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