CN109698228A - A kind of super-junction device and manufacturing method - Google Patents
A kind of super-junction device and manufacturing method Download PDFInfo
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- CN109698228A CN109698228A CN201710985615.8A CN201710985615A CN109698228A CN 109698228 A CN109698228 A CN 109698228A CN 201710985615 A CN201710985615 A CN 201710985615A CN 109698228 A CN109698228 A CN 109698228A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 26
- 230000002146 bilateral effect Effects 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 12
- 108091006146 Channels Proteins 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 230000002542 deteriorative effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Abstract
The invention belongs to ic manufacturing technology fields, it provides a kind of super-junction device and manufacturing method, super-junction device provided by the invention includes at least: semiconductor substrate, epitaxial layer, drift region, super junction P rod structure, source region, channel region, ion implanted region, oxide skin(coating), polysilicon gate；The super junction P rod structure is multi-segment structure, including one or more first super junction P rod structures and one or more second super junction P rod structures, the first super junction P rod structure and the channel region contacts, the second super junction P rod structure is contacted with the epitaxial layer in the semiconductor substrate, is not in contact with each other between the first super junction P rod structure and the second super junction P rod structure.The output capacitance of super-junction device under low pressure can be greatly reduced by introducing multiple non-touching super junction P rod structures in drift region.
Description
Technical field
The present invention relates to ic manufacturing technology field more particularly to a kind of super-junction device and manufacturing methods.
Background technique
Currently, super-junction device is a kind of power device that purposes is very extensive, source and drain the two poles of the earth are located at device
Two sides, electric current vertically circulates in device inside at work, increases current density, improves rated current, and its unit
The conducting resistance of area also very little.
Traditional VDMOS device has the advantages that bipolar junction transistor and common MOS device simultaneously, with bipolar junction transistor
It compares, the features such as its switching speed is fast, and switching loss is small, and input impedance is high, and driving power is small, and the linearity is high.Super junction device
Part (as shown in Figure 1) is compared with traditional VDMOS device, due to the presence of P column, so that P column can be realized laterally with N-type drift region
It exhausts, the doping concentration of N-type drift region can be significantly increased in the case where not reducing breakdown voltage, so that device be greatly reduced
The ratio conducting resistance of part.Therefore, the output capacitance at 0V for increasing meeting and greatly increasing super-junction device of P column, but
Under high pressure, since P column and N-type drift region have all been depleted, output capacitance can be greatly reduced.Therefore the output of super-junction device
Capacitor has a characteristic that compared to traditional VDMOS
1, for output capacitance when low pressure, especially 0V, output capacitance is big.Output capacitance is small under high pressure.
2, output capacitance is non-linear big.
Super-junction device capacity ratio VDMOS when 0V (low pressure) is much larger.Progress and device architecture with technique
Optimization, the ratio conducting resistance of super-junction device constantly reducing.In the case where same resistance, the area of super-junction device is not
Disconnected to reduce, the cost of device constantly reduces.The input capacitance of device constantly reduces, the output capacitance of device to energy it is equivalent not
It is disconnected to reduce.But the output capacitance of super-junction device is held essentially constant the equivalent of time.Here it is because the output of 0V is electric
Hold excessive.How super-junction device output capacitance at 0V is reduced to further decreasing super-junction device output capacitance to the time
Equivalent have very important effect.
In addition, output capacitance when reducing super-junction device 0V (low pressure), helps to reduce super-junction device output electricity
That holds is non-linear, this reduces voltage overshoot of the device in switching process, there is great help to the EMI for improving device.
Summary of the invention
The purpose of the present invention is to provide super-junction devices, defeated at 0V to solve super-junction device in the prior art
Capacitor is larger out while the too small problem of output capacitance under high pressure.The present invention also provides a kind of systems of super-junction device thus
Make method.
In order to solve the above technical problem, the present invention provides super-junction device include at least:
Semiconductor substrate, epitaxial layer, drift region, super junction P rod structure, source region, channel region, ion implanted region, oxide
Layer, polysilicon gate；
The super junction P rod structure is multi-segment structure, including one or more first super junction P rod structures and one or more
A second super junction P rod structure, the first super junction P rod structure and the second super junction P rod structure are respectively positioned on drift region
Interior, the first super junction P rod structure and the channel region contacts, the second super junction P rod structure and the semiconductor serve as a contrast
Epitaxial layer contact on bottom, is not in contact with each other between the first super junction P rod structure and the second super junction P rod structure.
It preferably, further include one or more third super junction P rod structures, the third super junction P in the drift region
Rod structure is surrounded by the drift region.
Preferably, the first super junction P rod structure and the second super junction P rod structure are bilateral symmetry, described
Third super junction P rod structure is between the symmetrical first super junction P rod structure, and the third super junction P column
Structure is located on the second super junction P rod structure.
The depth of the third super junction P rod structure is identical as the depth of the first super junction P rod structure.
Preferably, the volume of the first super junction P rod structure accounts for the 50% of super junction P rod structure volume.
Preferably, the depth of the first super junction P rod structure is identical as the depth of the second super junction P rod structure.
Preferably, the volume of the first super junction P rod structure accounts for the 30% of super junction P rod structure volume, and described second
The volume of super junction P rod structure accounts for the 70% of super junction P rod structure volume.
Preferably, the semiconductor substrate is doped with the first conduction type element.
Preferably, the super junction P rod structure is doped with the second conduction type element.
Preferably, the first conduction type element or the second conduction type element are selected according to user
It selects.
Preferably, the first conduction type element is N-type element, and the second conduction type element is p-type element.
In order to solve the above-mentioned technical problem, in addition, the present invention also provides a kind of manufacturing methods of super-junction device, including
Following steps:
Step 1: face forms epitaxial layer on a semiconductor substrate；
Step 2: growth forms drift region on said epitaxial layer there；
Step 3: forming the super of multi-segment structure by deep etching method or multiple epitaxial growth method in the drift region
P rod structure is tied, the super junction P rod structure includes that one or more first super junction P rod structures and one or more the second surpass
Grade knot P rod structure, the second super junction P rod structure are contacted with the epitaxial layer in the semiconductor substrate, and described first is super
It is not in contact with each other between knot P rod structure and the second super junction P rod structure；
Step 4: forming ion implanted region and source region on the drift region, make the first super junction P rod structure and institute
State source contact；
Step 5: forming oxide skin(coating) and polysilicon gate above the ion implanted region.
Preferably, in the step 3, multi-segment structure is formed by multiple epitaxial growth method in the drift region
Super junction P rod structure specifically:
Step 1: defining the position of super junction P rod structure in drift region by the first mask plate, make mask plate will be super
Tie the partial occlusion other than P post structure locations；
Step 2: by being epitaxially-formed super junction P rod structure；
Step 3: blocking the super junction P rod structure formed in step 2 by the second mask plate, continue to be epitaxially-formed
Drift region；
Step 4: according to Step 1: the sequence of step 2 and step 3 is repeated several times Step 1: Step 2: step 3
Technique, to form multiple first super junction P rod structures, multiple second super junction P rod structures.
Preferably, the super junction P rod structure of multi-segment structure is formed by deep etching method in the drift region specifically:
Step 1: the position of super junction P rod structure is defined in drift region by mask plate, in the super junction P column knot
The position of structure performs etching to form deep trench；
Step 2: filling p type single crystal silicon in deep trench using the filling mode of selective epitaxial, P column is formed.
Preferably, the ion implanting of the first conduction type element is carried out after step 3.
It preferably, further include one or more third super junction P rod structures, the third super junction P in the drift region
The drift region that rod structure is doped with the first conduction type element is surrounded.
Preferably, the first super junction P rod structure and the second super junction P rod structure are bilateral symmetry, described
Third super junction P rod structure is between the symmetrical first super junction P rod structure, and the third super junction P column
Structure is located on the second super junction P rod structure.
Preferably, the depth of the third super junction P rod structure is identical as the depth of the first super junction P rod structure.
Preferably, the volume of the first super junction P rod structure accounts for the 50% of super junction P rod structure volume.
Preferably, the volume of the first super junction P rod structure accounts for the 30% of super junction P rod structure volume, and described second
The volume of super junction P rod structure accounts for the 70% of super junction P rod structure volume.
Preferably, the first super junction P rod structure and the second super junction P rod structure bilateral symmetry.Preferably,
The semiconductor substrate is doped with the first conduction type element.
Preferably, the super junction P rod structure is doped with the second conduction type element.
Preferably, the first conduction type element or the second conduction type element are selected according to user
It selects.
Preferably, the first conduction type element is N-type element, and the second conduction type element is p-type element.
Preferably, the photolithography plate used in the deep etching can be used in the ion implanting.
In super-junction device provided by the invention and manufacturing method, super-junction device is included at least: semiconductor substrate, extension
Layer, drift region, super junction P rod structure, source region, channel region, ion implanted region, oxide skin(coating), polysilicon gate；The super junction
P rod structure is multi-segment structure, including one or more first super junction P rod structures and one or more second super junction P column knots
Structure, the first super junction P rod structure and the second super junction P rod structure are respectively positioned in drift region, the first super junction P
Rod structure and the channel region contacts, the second super junction P rod structure are contacted with the epitaxial layer in the semiconductor substrate, institute
It states and is not in contact with each other between the first super junction P rod structure and the second super junction P rod structure.It is multiple mutual by being introduced in drift region
The output capacitance of super-junction device under low pressure, while the new structure can be greatly reduced in discontiguous super junction P rod structure
The breakdown voltage of super-junction device is compared with traditional structure super-junction device there is no deteriorating, can also basis than conducting resistance
Design needs to compensate.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of traditional super-junction device；
Fig. 2 is the first super junction device structure schematic diagram in the embodiment of the present invention；
Fig. 3 is second of super junction device structure schematic diagram in the embodiment of the present invention；
Fig. 4 is the third super junction device structure schematic diagram in the embodiment of the present invention；
Fig. 5 is the output capacitance of the super-junction device and conventional Super junction device in the embodiment of the present invention one with the pass of voltage
System's figure.
Fig. 6 is the semiconductor substrate structure schematic diagram in the super-junction device manufacturing method provided in the embodiment of the present invention；
Fig. 7 is the formation extension on a semiconductor substrate in the super-junction device manufacturing method provided in the embodiment of the present invention
The structural schematic diagram of layer；
Fig. 8 is to carry out the first deep trouth in epitaxial layer in the super-junction device manufacturing method provided in the embodiment of the present invention nine
Structural schematic diagram after etching and P-type silicon filling；
Fig. 9 is to carry out the first deep trouth in epitaxial layer in the super-junction device manufacturing method provided in the embodiment of the present invention nine
Second of outer structural schematic diagram delayed is carried out after etching and P-type silicon filling；
Figure 10 is to carry out the first deep etching in the super-junction device manufacturing method provided in the embodiment of the present invention nine
In second of extension followed by carry out second of deep etching and P-type silicon filling after structural schematic diagram；
Figure 11 is to carry out deep etching in epitaxial layer in the super-junction device manufacturing method provided in the embodiment of the present invention nine
With the structural schematic diagram after P-type silicon filling；
Figure 12 is to carry out deep etching in epitaxial layer in the super-junction device manufacturing method provided in the embodiment of the present invention nine
The structural schematic diagram delayed outside second is carried out with after P-type silicon filling；
Figure 13 is to be followed by the super-junction device manufacturing method provided in the embodiment of the present invention nine in second of extension of progress
Carry out second of deep etching and P-type silicon filling after structural schematic diagram；
Appended drawing reference:
1: polysilicon gate；2: oxide skin(coating)；3: source region；
4: heavily doped region；5: channel region；
6: super junction P rod structure；6a: the first super junction P rod structure；
6b: the second super junction P rod structure；6c: third super junction P rod structure；
7: drift region；8: epitaxial layer；
9: semiconductor substrate；10: ion implanted region.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In the description of the present invention, it is to be understood that, term " first ", " second " are used for description purposes only, and cannot
It is interpreted as indication or suggestion relative importance or implicitly indicates the quantity of indicated technical characteristic.Define as a result, " the
One ", the feature of " second " can explicitly or implicitly include one or more of the features.
The embodiment of the present invention one provides a kind of super-junction device.Super-junction device in the present embodiment includes at least: more
Polysilicon gate 1, oxide skin(coating) 2, source region 3, heavily doped region 4, channel region 5, super junction P rod structure 6a, super junction P rod structure 6b,
Drift region 7, epitaxial layer 8, semiconductor substrate 9, ion implanted region 10；First super junction P rod structure 6a is contacted with channel region 5, the
Two super junction P rod structure 6b are contacted with the epitaxial layer in semiconductor substrate, and the first super junction P rod structure 6a and described second is super
It is not in contact with each other between knot P rod structure 6b.
In embodiments of the present invention, epitaxial layer 8 is located in semiconductor substrate 9, and drift region 7 is above epitaxial layer 8, super junction
P rod structure 6a, super junction P rod structure 6b are distributed in drift region 7.First super junction P rod structure 6a and the second super junction P column knot
The volume and depth of structure 6b can need to be configured according to user.Semiconductor substrate 9, epitaxial layer 8 are mixed in drift region 7
Miscellaneous to have the first conduction type element, the doping concentration in usual drift region 7 is between 1e15/cm3~5e16/cm3, by adjusting and reforming
Become the breakdown voltage of the adjustable super-junction device of thickness of drift region, the doping concentration of semiconductor substrate 9 is higher, adulterates dense
Degree is greater than 1e19/cm3, and by the highly doped resistance for reducing substrate, epitaxial layer 8 can prevent the thermal process of technique, highly doped
The atom of substrate is diffused into drift region, causes the doping concentration of drift region to increase, so as to cause the breakdown voltage of super-junction device
It reduces.
Source region 3 is doped with the first conduction type element, according to p-type member between source region 3 and the first super junction P rod structure 6a
The doping concentration difference of element can be divided into channel region 5 and heavily doped region 4, and the p-type doping concentration of heavily doped region 4 is higher, be used for shape
At the collecting region in hole, the doping concentration of channel region 5 is usually between 5e13/cm3~1e14/cm3, by changing dopant dose
To adjust the threshold voltage of super-junction device.Drift region injection ion between source region 3 forms ion implanted region to reduce conducting
Resistance forms the isolation that oxide skin(coating) 2 realizes grid and channel on ion implanted region, forms polysilicon gate 1 on oxide.
Super-junction device in the present embodiment, the second super junction P rod structure 6b are contacted with epitaxial layer 8, outside current potential and N-type
It is identical to prolong layer 8, the current potential of N-type semiconductor substrate 9.
Fig. 5 is the pass between the voltage and output capacitance of the super-junction device and traditional super-junction device in the present embodiment
System's figure, horizontal axis is drain voltage in Fig. 5, and grid voltage 0V, the longitudinal axis is logarithmic coordinates, omits specific numerical value here,
It is high from, it can be found that output capacitance only has original 60% under the voltage of 0V, low pressure output capacitance is drastically reduced in Fig. 5
It presses output capacitance slightly to improve, but improves and be not obvious, the non-linear reduction of output capacitance.
Super-junction device in the present embodiment includes at least: semiconductor substrate, the extension in the semiconductor substrate
Layer, drift region, super junction P rod structure, source region, ion implanted region, oxide skin(coating), the polysilicon gate on the oxide skin(coating)
Pole, the super junction P rod structure include doped with P between the super junction P rod structure and the source region doped with p-type element
The P-type channel area of type element carries out the p-type heavily doped region of p-type element heavy doping, and the super junction P rod structure is multi-segment structure,
Including the first super junction P rod structure 6a of one or more and the second super junction P rod structure 6b of one or more, described first is super
Knot P rod structure 6a contacted with the P-type channel area, the second super junction P rod structure with it is described in the semiconductor substrate
Epitaxial layer contact, is not in contact with each other between the first super junction P rod structure and the second super junction P rod structure.
Super-junction device can be greatly reduced under low pressure by the super junction P rod structure 6b of the floating in the embodiment of the present invention
Output capacitance, as shown in Figure 5；And compared with the existing technology, the breakdown voltage of the new structure super-junction device is with tradition
Structure super-junction device compare there is no deteriorate, although decrease than conducting resistance, but can according to the design needs into
Row compensation.
As a preferred embodiment of the present invention, as shown in Fig. 2, the first super junction P rod structure 6a bilateral symmetry, second is super
Knot P rod structure 6b is located at the axis line position of left end the first super junction P rod structure and right end super junction P rod structure.
As a preferred embodiment of the present invention, the depth of the first super junction P rod structure and the second super junction P column
The depth of structure is identical.
As a preferred embodiment of the present invention, as shown in figure 3, the first super junction P rod structure 6a and the second super junction P column knot
It is not in contact with each other, and the first super junction P rod structure 6a and the second super junction P rod structure 6b bilateral symmetry, passes through between structure 6b
Symmetrical lateral super junction P rod structure, can exhaust with drift region, to realize higher doping concentration and high breakdown
Voltage.
Based on the various embodiments described above, which can also include one or more third super junction P rod structures, Duo Ge
It is not in contact with each other between three super junction P rod structures, third super junction P rod structure and the first super junction P rod structure, the second super junction P
Rod structure does not also contact.In addition, the volume of multiple third super junction P rod structures can be arbitrary, each third super junction P
It is to be surrounded doped with the drift region 7 of N-type conductive element around rod structure.
As a preferred embodiment of the present invention, the third super junction P rod structure is located at symmetrical described the first surpass
Between grade knot P rod structure, and the third super junction P rod structure is located on the second super junction P rod structure.
As a preferred embodiment of the present invention, as shown in figure 4, the third super junction P rod structure is positioned at symmetrical
Axis line position between the first super junction P rod structure.
Further, third super junction P rod structure is also with left end the first super junction P rod structure 6a and right end super junction P
The central axes of rod structure are axis bilateral symmetry.
As a preferred embodiment of the present invention, the volume of the first super junction P rod structure accounts for super junction P rod structure volume
50%.
As a preferred embodiment of the present invention, the first conduction type element is N-type element, the second conduction type element is P
Type element.
It is worth noting that the volume of the first super junction P rod structure is interpreted as the first super junction P of one or more herein
The summation of the volume of rod structure, super junction P rod structure volume are interpreted as all first super junction P rod structures, the second super junction P
The volume summation of rod structure, third super junction P rod structure.
A kind of manufacturing method of super-junction device is provided in the embodiment of the present invention.Super-junction device provided in this embodiment
Manufacturing method the following steps are included:
Step 1: face forms epitaxial layer (as shown in Figure 6) on a semiconductor substrate；
Step 2: growth forms drift region (as shown in Figure 7) on epitaxial layer；
Step 3: the super junction P rod structure of multi-segment structure is formed by deep etching method in the drift region, it is described super
Grade knot P rod structure includes one or more first super junction P rod structures and one or more second super junction P rod structures, described
Second super junction P rod structure is contacted with the epitaxial layer in the semiconductor substrate, the first super junction P rod structure and described the
It is not in contact with each other between two super junction P rod structures；It can also be needed to form the by deep etching method according to user in drift region
Three super junction P rod structures, which can be one or more, and be not in contact with each other, third super junction
The drift region that structure periphery is doped N-type conductive element surrounds；
Step 4: forming ion implanted region and source region on the drift region, make the first super junction P rod structure and institute
State source contact；
Step 5: forming oxide skin(coating) and polysilicon gate above the ion implanted region.
As a preferred embodiment of the present invention, prepared using the first deep etching in super-junction device as shown in Figure 2,
The super junction P rod structure of multi-segment structure is formed using deep etching method in the drift region specifically:
Step 1: defining the position of the second super junction P rod structure 6b, the super junction P in drift region by mask plate
The position of rod structure is located at drift district center, performs etching to form deep trench in the position of the super junction P rod structure of definition；
Step 2: filling p type single crystal silicon in deep trench using the filling mode of selective epitaxial, it is super to form second
It ties P rod structure 6b (as shown in Figure 8)；
Step 3: carrying out being epitaxially-formed drift region (as shown in Figure 9)；
Step 4: second of deep etching of progress and P-type silicon are inserted to form the first super junction P rod structure 6a, first is super
Knot P rod structure is distributed in drift region left and right ends, and bilateral symmetry, is not in contact with each other with the second super junction P rod structure, it is intermediate by
Separated drift regions (as indicated by 10).
As a preferred embodiment of the present invention, prepared using second of deep etching in super-junction device as shown in Figure 3,
The super junction P rod structure of multi-segment structure is formed using deep etching method in the drift region specifically:
Step 1: define the position of the second super junction P rod structure in drift region by the first mask plate, this is second super
P rod structure bilateral symmetry is tied, and is contacted with epitaxial layer 8, performs etching to be formed in the position of the second super junction P rod structure
Deep trench；
Step 2: filling p type single crystal silicon in deep trench using the filling mode of selective epitaxial, it is super to form second
Tie P rod structure, the second super junction P rod structure bilateral symmetry (as shown in figure 11)；
Step 3: carrying out growth is epitaxially formed drift region (as shown in figure 12)；
Step 4: by the second mask plate in the position for defining the first super junction P rod structure in drift region, described super
The position of grade knot P rod structure performs etching to form deep trench, and p type single crystal silicon is filled in deep trench, forms the second super junction P
Column, the second super junction P column bilateral symmetry (as shown in figure 13).
As a preferred embodiment of the present invention, third super junction P can also be defined in drift region by third mask plate
Then the position of rod structure carries out deep etching and P-type silicon is inserted to form third super junction P rod structure, third super junction P column knot
Structure can be one or more.
As a preferred embodiment of the present invention, a N can also be carried out after drift region and super junction P rod structure are formed
The ion implanting of type, can reduce the ratio conducting resistance of device after progress N-type ion injection, which can early entire device
Also the property of can choose carries out on part surface, or the ion implanting of N-type is carried out using the photolithography plate of deep etching.The N-type
Ion implanting can be to be carried out under the voltage of 60KeV, and the ion concentration of injection is 2e12/cm3.
In manufacturing method provided in an embodiment of the present invention, it is formed with epitaxial layer, drift region in semiconductor substrate, by outside
Prolonging the multiple deep etching of layer progress and P-type silicon is inserted to form super junction P rod structure, the super junction P rod structure is multi-segment structure,
Including the first super junction P rod structure and the second super junction P rod structure, the first super junction P rod structure and the source contact,
The second super junction P rod structure is contacted with the epitaxial layer in the semiconductor substrate, the first super junction P rod structure
It is not in contact with each other between the second super junction P rod structure.By introducing multiple non-touching super junction P column knots in drift region
The output capacitance of super-junction device under low pressure, while the breakdown voltage of the new structure super-junction device can be greatly reduced in structure
It compares with traditional structure super-junction device there is no deteriorating, can also be compensated according to the design needs than conducting resistance.
As a preferred embodiment of the present invention, super-junction device can also be manufactured using multiple epitaxial growth method.This implementation
Example provide super-junction device manufacturing method the following steps are included:
Step 1: face forms epitaxial layer on a semiconductor substrate；
Step 2: being epitaxially-formed drift region；
Step 3: defining the position of super junction P rod structure in drift region by the first mask plate, make mask plate will be super
Tie the partial occlusion other than P post structure locations；
Step 4: by being epitaxially-formed super junction P rod structure；
Step 5: blocking the super junction P rod structure formed in step 2 by the second mask plate, continue to be epitaxially-formed
Drift region；
Step 6: according to Step 1: the sequence of step 2 and step 3 is repeated several times Step 1: Step 2: step 3
Technique, to form multiple first super junction P rod structures, multiple second super junction P rod structures.
Traditionally method prepares complete super-junction device to remaining step.
As a preferred embodiment of the present invention, after step 2 forms drift region, it is fixed in drift region by the first mask plate
Justice goes out the position of the second super junction P rod structure, makes mask plate by the partial occlusion other than the second super junction P post structure locations, into
Row is repeatedly epitaxially-formed the second super junction P rod structure doped with p-type element, replaces mask plate, passes through the second mask plate
Second super junction P rod structure is blocked, multiple epitaxial growth is carried out in non-shield portions and forms the drift doped with N-type element
Area；Mask plate is replaced, the position of the first super junction P rod structure is defined using third mask plate, keeps mask plate super by first
The partial occlusion other than P post structure locations is tied, carries out repeatedly being epitaxially-formed the first super junction P column doped with p-type element
Structure；Mask plate is replaced, the first super junction P rod structure is blocked by the 4th mask plate, multiple epitaxial growth is carried out and is not hiding
Stopper point forms the drift region doped with N-type element.
As a preferred embodiment of the present invention, the position of the position of the first super junction P rod structure and the second super junction P rod structure
Set bilateral symmetry.
As a preferred embodiment of the present invention, being repeatedly epitaxially-formed the first super junction P rod structure and second super
The position that third super junction P rod structure can also be defined between knot P rod structure by the 5th mask plate, carries out epitaxial growth shape
At the third super junction P rod structure doped with p-type element.
As a preferred embodiment of the present invention, a N can also be carried out after drift region and super junction P rod structure are formed
The ion implanting of type, can reduce the ratio conducting resistance of device after progress N-type ion injection, which can early entire device
Also the property of can choose carries out on part surface, or the ion implanting of N-type is carried out using the photolithography plate of deep etching.The N-type
Ion implanting can be to be carried out under the voltage of 60KeV, and the ion concentration of injection is 2e12/cm3.
In manufacturing method provided in this embodiment, it is formed with epitaxial layer in semiconductor substrate, is epitaxially-formed drift region
The position of super junction P rod structure is defined in drift region by mask plate, makes mask plate will be other than super junction P post structure locations
Partial occlusion, by being repeatedly epitaxially-formed drift region and super junction P rod structure, the super junction P rod structure is multistage knot
Structure, including the first super junction P rod structure and the second super junction P rod structure, the first super junction P rod structure and the channel region
Contact, the second super junction P rod structure are contacted with the epitaxial layer in the semiconductor substrate, the first super junction P column knot
It is not in contact with each other between structure and the second super junction P rod structure.By introducing multiple non-touching super junction P columns in drift region
The output capacitance of super-junction device under low pressure, while the breakdown potential of the new structure super-junction device can be greatly reduced in structure
Pressure is compared with traditional structure super-junction device there is no deteriorating, and can also be compensated according to the design needs than conducting resistance.
As an embodiment of the present invention, the super-junction device is planar gate structure.
As an embodiment of the present invention, the super-junction device is trench gate structure.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of super-junction device, which is characterized in that include at least: semiconductor substrate, epitaxial layer, drift region, super junction P column knot
Structure, source region, channel region, ion implanted region, oxide skin(coating), polysilicon gate；
The super junction P rod structure is multi-segment structure, including one or more first super junction P rod structure and one or more the
Two super junction P rod structures, the first super junction P rod structure and the second super junction P rod structure are respectively positioned on the drift region
Interior, the first super junction P rod structure and the channel region contacts, the second super junction P rod structure and the semiconductor serve as a contrast
Epitaxial layer contact on bottom, does not connect mutually between the first super junction P rod structure and the second super junction P rod structure
Touching.
2. super-junction device as described in claim 1, which is characterized in that further include one or more thirds in the drift region
Super junction P rod structure, the third super junction P rod structure are surrounded by the drift region.
3. super-junction device as claimed in claim 2, which is characterized in that the first super junction P rod structure and described second
Super junction P rod structure is bilateral symmetry, and the third super junction P rod structure is located at the symmetrical first super junction P
Between rod structure, and the third super junction P rod structure is located on the second super junction P rod structure.
4. super-junction device as claimed in claim 3, which is characterized in that the depth of the third super junction P rod structure and institute
The depth for stating the first super junction P rod structure is identical.
5. super-junction device as described in claim 1, which is characterized in that the volume of the first super junction P rod structure accounts for institute
State the 50% of super junction P rod structure volume.
6. super-junction device as described in claim 1, which is characterized in that the depth of the first super junction P rod structure and institute
The depth for stating the second super junction P rod structure is identical.
7. a kind of manufacturing method of super-junction device, which comprises the following steps:
Step 1: face forms epitaxial layer on a semiconductor substrate；
Step 2: growth forms drift region on said epitaxial layer there；
Step 3: the super junction P of multi-segment structure is formed by deep etching method or multiple epitaxial growth method in the drift region
Rod structure, the super junction P rod structure include one or more first super junction P rod structures and one or more second super junctions
P rod structure, the second super junction P rod structure are contacted with the epitaxial layer in the semiconductor substrate, and described first is super
It is not in contact with each other between knot P rod structure and the second super junction P rod structure；
Step 4: forming ion implanted region and source region on the drift region, make the first super junction P rod structure and the source
Area's contact；
Step 5: forming oxide skin(coating) and polysilicon gate above the ion implanted region.
8. the method for claim 7, which is characterized in that in the step 3, by multiple in the drift region
The super junction P rod structure of epitaxial growth method formation multi-segment structure specifically: Step 1: by the first mask plate in drift area definition
The position of super junction P rod structure out makes mask plate by the partial occlusion other than super junction P post structure locations；
Step 2: by being epitaxially-formed super junction P rod structure；
Step 3: blocking the super junction P rod structure formed in step 2 by the second mask plate, continue to be epitaxially-formed drift
Area；
Step 4: according to Step 1: the sequence of step 2 and step 3 be repeated several times Step 1: Step 2:
The technique of step 3.
9. the method for claim 7, which is characterized in that form multistage knot by deep etching method in the drift region
The super junction P rod structure of structure specifically:
Step 1: the position of super junction P rod structure is defined in drift region by mask plate, in the super junction P rod structure
Position performs etching to form deep trench；
Step 2: filling p type single crystal silicon in deep trench using the filling mode of selective epitaxial, super junction P column knot is formed
Structure.
10. the method for claim 7, which is characterized in that carried out after step 3 the first conduction type element from
Son injection.
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| CN116031303A (en) * | 2023-02-09 | 2023-04-28 | 上海功成半导体科技有限公司 | Super junction device, manufacturing method thereof and electronic device |
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| US20140306283A1 (en) * | 2013-04-16 | 2014-10-16 | Rohm Co., Ltd. | Superjunction semiconductor device and manufacturing method therefor |
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