CN105321946A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN105321946A CN105321946A CN201510098177.4A CN201510098177A CN105321946A CN 105321946 A CN105321946 A CN 105321946A CN 201510098177 A CN201510098177 A CN 201510098177A CN 105321946 A CN105321946 A CN 105321946A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 201
- 239000012535 impurity Substances 0.000 claims abstract description 125
- 230000005684 electric field Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004645 scanning capacitance microscopy Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of fourth semiconductor regions, a fifth semiconductor region, and a gate electrode. An impurity concentration of the first conductivity type in the second semiconductor region is higher than an impurity concentration of the first conductivity type in the first semiconductor region. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region.
Description
[related application]
Subject application enjoys the priority of application case based on No. 2014-156048, Japanese patent application case (applying date: on July 31st, 2014).Subject application comprises the full content of basic application case by referring to this basic application case.
Technical field
Following execution mode is broadly directed to a kind of semiconductor device.
Background technology
MOSFET (MetalOxideSemiconductorFieldEffectTransistor, mos field effect transistor) or the semiconductor device such as IGBT (InsulatedGateBipolarTransistor, insulated gate bipolar transistor) be widely used in the power conversion apparatus or electric control appliance etc. of domestic electric appliance, communication equipment, motor for automobile etc.In most cases, these semiconductor devices are required to the reverse prevention characteristic (withstand voltage) of high speed switching characteristic or tens of ~ hundreds of volts.
The conducting resistance of these semiconductor devices depends on the resistance of drift region significantly.The resistance of drift region depends on the impurity concentration of drift region.The limit of the impurity concentration of drift region is the withstand voltage of the p-n junction formed according to base region and drift region and determines.That is, if improve the impurity concentration of drift region, then withstand voltage reduction, if improve withstand voltage, then the impurity concentration of drift region reduces.Therefore, between withstand voltage and conducting resistance, there is the relation of choice.
Keep withstand voltage one side to reduce one of method of conducting resistance as one side, have the method using super junction structure at drift region.Super junction structure direction is alternately arranged multiple p-type post area and multiple N-shaped post area in substrate surface.This super junction structure is by making the impurity level contained by p-type post area equal with the impurity level contained by N-shaped post area, and can simultaneously keep withstand voltage one side to improve the impurity concentration of drift region.
But require that one side suppresses the increase of conducting resistance to semiconductor device, one side makes the technology of withstand voltage further lifting always.
Summary of the invention
Embodiments of the present invention provide a kind of increase that simultaneously can suppress conducting resistance, and one side makes the semiconductor device of withstand voltage further lifting.
The semiconductor device of execution mode possesses the first semiconductor regions, multiple second semiconductor regions, multiple 3rd semiconductor regions, multiple 4th semiconductor regions, the 5th semiconductor regions and gate electrode.
First semiconductor regions is the semiconductor regions of the first conductivity type.
Second semiconductor regions is the semiconductor regions of the first conductivity type be optionally arranged on the first semiconductor regions.Second semiconductor regions has the impurity concentration of first conductivity type higher than the impurity concentration of the first conductivity type of the first semiconductor regions.Second semiconductor regions extends in a first direction.Second semiconductor regions is mutually separated by the second direction orthogonal with first direction and arranges.
3rd semiconductor regions comprises Part I and Part II.3rd semiconductor regions extends in a first direction.3rd semiconductor regions is the semiconductor regions of the second conductivity type.
Part I is arranged between the second adjacent semiconductor regions.The impurity level of the second conductivity type of Part I is larger than the impurity level of the first conductivity type contained by the second adjacent semiconductor regions.
Part II is arranged in the first semiconductor regions.The impurity level of the second conductivity type of Part II is less than the impurity level of the first conductivity type contained by the first adjacent semiconductor regions.
4th semiconductor regions is arranged on the 3rd semiconductor regions.4th semiconductor regions is the semiconductor regions of the second conductivity type.
5th semiconductor regions is arranged in the 4th semiconductor regions.
Gate electrode is arranged on across gate insulating film on the 4th semiconductor regions.
Accompanying drawing explanation
Fig. 1 is the three-dimensional cutaway view of a part for the semiconductor device representing the first execution mode.
Fig. 2 A ~ D is the step cutaway view of the manufacturing step of the semiconductor device representing the first execution mode.
Fig. 3 is the three-dimensional cutaway view of a part for the semiconductor device representing the second execution mode.
Fig. 4 is the three-dimensional cutaway view of a part for the semiconductor device of the change case representing the second execution mode.
Embodiment
Below, one side is with reference to accompanying drawing, and various embodiments of the present invention will be described for one side.
In addition, accompanying drawing is model utility or conceptual figure, and ratio of the thickness of each several part and the size between the relation of width, part etc. may not be identical with actual things.In addition, even if when representing with a part, also with good grounds accompanying drawing and the situation that represent different with mutual size or ratio.
In addition, in this case specification and each figure, close the figure proposed, to the element annotation same-sign identical with described content, and suitably omit detailed description.
(the first execution mode)
Fig. 1 is the three-dimensional cutaway view of a part for the semiconductor device representing the first execution mode.
In present embodiment, for the first conductivity type be N-shaped, the second conductivity type is that the situation of p-type is described.But, also the first conductivity type can be set to p-type, the second conductivity type is set to N-shaped.
Semiconductor device 100 is such as MOSFET.
Semiconductor device 100 possesses the first semiconductor regions of the first conductivity type, the second semiconductor regions of multiple first conductivity type, the 3rd semiconductor regions of multiple second conductivity type, the 4th semiconductor regions of the second conductivity type, the 5th semiconductor regions and gate electrode of the first conductivity type.
First semiconductor regions is such as n-type semiconductor region 2.Second semiconductor regions is such as n post area 3.3rd semiconductor regions is such as p post area 4.4th semiconductor regions is such as p base region 5.5th semiconductor regions is such as source region 6.
N-type semiconductor region 2 is arranged on drain region 1.The impurity concentration of the first conductivity type of n-type semiconductor region 2 is lower than the impurity concentration of the first conductivity type of drain region 1.
N post area 3 is optionally arranged in n-type semiconductor region 2.The impurity concentration of the first conductivity type of n post area 3 is higher than the impurity concentration of the first conductivity type of n-type semiconductor region 2.The impurity concentration of the first conductivity type of n post area 3 is lower than the impurity concentration of the first conductivity type of drain region 1.N post area 3 extends in the direction y (the first direction).N post area 3 to be mutually separated by the Z-direction (second direction) orthogonal with Y-direction and to arrange multiple.
P post area 4 is arranged in n-type semiconductor region 2 with the way selection between adjacent n post area 3.That is, multiple n post area 3 is alternately arranged in z-direction with multiple p post area 4.The impurity concentration of the second conductivity type of p post area 4 is higher than the impurity concentration of the first conductivity type of n-type semiconductor region 2.P post area 4 extends in the Y direction.P post area 4 is mutually separated by z-direction and arranges multiple.
N-type semiconductor region 2 comprises part 2a.
N post area 3 comprises part 3a.
P post area 4 comprises part 4a (Part I) and part 4b (Part II).
Between the n post area 3 that the part 4a of p post area 4 is arranged on and part 4a is adjacent.Part 4a is arranged on the degree of depth identical with the part 3a of n post area 3.That is, part 4a and part 3a is arranged side by side in z-direction.
The part 4b of p post area 4 is arranged in n-type semiconductor region 2.But p post area 4 does not arrive drain region 1.That is, between p post area 4 and drain region 1, there is n-type semiconductor region 2.Part 4b is arranged on the degree of depth identical with the part 2a of n-type semiconductor region 2.That is, part 4b and part 2a is arranged side by side in z-direction.
Size in the Z-direction of n post area 3 is successively decreased in the X-direction orthogonal with Y-direction and Z-direction.Therefore, the size in the Z-direction on the top of n post area 3 is shorter than the size in the Z-direction of the bottom of n post area 3.
On the other hand, the size in the Z-direction of p post area 4 increases progressively in the X direction.Therefore, the size in the Z-direction of part 4a is longer than the size in the Z-direction of part 4b.
The impurity concentration of second conductivity type of part 4a is equal with the impurity concentration of first conductivity type of the part 3a arranged side by side in z-direction with part 4a.And the size in the Z-direction of part 4a is longer than the size in the Z-direction of part 3a.Therefore, the impurity level of the second conductivity type contained by part 4a is larger than the impurity level of the first conductivity type contained by part 3a.
The impurity concentration of second conductivity type of part 4b is higher than the impurity concentration of first conductivity type of the part 2a arranged side by side in z-direction with part 4b.Size in the Z-direction of part 4b is shorter than the size in the Z-direction of part 2a.The impurity level of the second conductivity type contained by part 4b is less than the impurity level of the first conductivity type contained by part 2a.
The impurity level in each region such as by the impurity concentration in each region and the volume in each region product and try to achieve.
The carrier density of each semiconductor regions and the impurity concentration of each semiconductor regions proportional.
Therefore, if otherwise represent example represented by Fig. 1, then for the carrier density that is positioned at the first conductivity type of the part at the center of Z-direction at part 3a is equal with the carrier density of the second conductivity type of part at the center being positioned at Z-direction at part 4a.Size in the Z-direction of part 4a is longer than the size in the Z-direction of part 3a.
In addition, the carrier density being positioned at the second conductivity type of the part at the center of Z-direction at part 4b is higher than the carrier density being positioned at the first conductivity type of the part at the center of Z-direction at part 2a.Size in the Z-direction of part 4b is shorter than the size in the Z-direction of part 2a.
In addition, A-A' line is the line also extended in the X direction by the center of the Z-direction of n post area 3.B-B' line is the line also extended in the X direction by the center of the Z-direction of p post area 4.
The carrier density of described each several part also can comprise the inequality in manufacture.As long as the carrier density of a part is more than * * times and less than * * times in the carrier density of another part relatively, then can think that the carrier density in these regions is equal in fact.
N post area 3 forms so-called super junction with a part for p post area 4 and constructs.
In the following description, n post area 3 and part 4a will be comprised, and the region forming super junction structure is called drift region.
P base region 5 is optionally arranged on drift region.
Source region 6 is arranged in p base region 5.The impurity concentration of the first conductivity type of source region 6 is higher than the impurity concentration of the first conductivity type of n post area 3.P base region 5 and source region 6 extend in the Y direction.P base region 5 and source region 6 be arrange in z-direction multiple.
Contact area 7 is arranged in p base region 5.In addition, contact area 7 is arranged on and is arranged on source region 6 in p base region 5 equally each other.The impurity concentration of the second conductivity type of contact area 7 is higher than the impurity concentration of the second conductivity type of p base region 5.Contact area 7 is connected with following source electrode 11.Contact area 7 is not the necessary formation of present embodiment.But, in order to the electric hole in n post area 3 is expelled to source electrode 11 effectively, contact area 7 is preferably set.Contact area 7 extends in the Y direction.In addition, contact area 7 be to arrange in z-direction multiple.
Gate electrode 9 is arranged in n post area 3 and on p base region 5 across gate insulating film 8.Gate electrode 9 and a part for n post area 3 and a part of subtend of p base region 5.Gate electrode 9 extends in the Y direction.In addition, gate electrode 9 be to arrange in z-direction multiple.
By applying the voltage of more than threshold value to gate electrode 9, and make MOSFET become on-state, form passage (inversion layer) on the surface of p base region 5.
When MOSFET is off state, vague and general layer is expanded to n post area 3 and p post area 4 from the pn junction of n post area 3 with p post area 4.By the vague and general layer expanded to n post area 3 and p post area 4, and withstand voltage lifting can be made.
In drain region 1, drain electrode 10 is set with the face of n-type semiconductor region 2 opposition side.Drain electrode 10 is connected to drain region 1.
Source electrode 11 is arranged on source region 6 and on contact area 7, and with these joint areas.
Herein, the example of Fig. 2 to the manufacture method of semiconductor device 100 is used to be described.
Fig. 2 is the step cutaway view of the manufacturing step of the semiconductor device 100 representing the first execution mode.
First, as shown in Figure 2 A, the Semiconductor substrate 21 of the first conductivity type is prepared.
Secondly, as shown in Figure 2 B, Semiconductor substrate 21 makes semiconductor layer 31 epitaxial growth of the first conductivity type.
Then, as shown in Figure 2 C, in Semiconductor substrate 21, form groove T with through the semiconductor layer 31 of epitaxial growth.Groove T is formed by such as RIE (ReactiveIonEtching, reactive ion etch) method.The width that groove T-shaped becomes the top of groove T is wider than the width of bottom.By adjusting the kind of reactant gas, the pressure of reactant gas or the input electric power etc. when utilizing RIE method formation groove, and control the width of the width on the top of groove T and the bottom of groove T.The Semiconductor substrate 21 formed after groove T is equivalent to n-type semiconductor region 2.In addition, the semiconductor layer 31 after forming groove T is equivalent to n post area 3.
Then, as shown in Fig. 2 (d), in formed groove T, make the semiconductor layer epitaxial growth of the second conductivity type, form p post area 4.
Then, drift region is formed source region 6, contact area 7, gate insulating film 8, gate electrode 9 and source electrode 11.Then, n-type semiconductor region 2 with the formation drain region, region 1 of drift region opposition side, drain region 1 is formed drain electrode 10, obtains the semiconductor device 100 represented by Fig. 1 thus.
Represent by RIE method formation groove in Fig. 2, and in groove, make the example of semiconductor layer epitaxial growth.Be not limited thereto, also form the p post area 4 that the size in the Z-direction on top is longer than the size in the Z-direction of bottom by ion implantation.But, in order to the easiness that manufactures and the inequality reducing the impurity concentration in p post area 4, be preferably formed groove, form the method for p post area 4.
Below, the effect of present embodiment and effect are described.
First, the impurity level being set to first conductivity type of the part 3a than the n post area 3 arranged side by side in z-direction with part 4a by the impurity level of the second conductivity type by part 4a is large, and can strengthen the electric field of drift region.
Then, by setting unit 4b in n-type semiconductor region 2, and the electric field in n-type semiconductor region 2 can be strengthened.Now, the electric field strength in n-type semiconductor region 2 can affect the electric field strength in drift region.Therefore, except the described impurity level by part 4a be set to larger than the impurity level of part 3a except, by setting unit 4b in n-type semiconductor region 2, and produce than strong electric field in n-type semiconductor region 2.Its result, can make withstand voltagely significantly to promote.
On the other hand, be set to by the impurity level of the second conductivity type by part 4b less than the impurity level of the first conductivity type in the part 2a of the buffer area arranged side by side in z-direction with part 4b, and the increase of conducting resistance can be suppressed.That is, even if when arranging part 4b in n-type semiconductor region 2, also can suppress the expansion of the vague and general layer extended towards Z-direction and the direction contrary with Z-direction from part 4b, suppressing the increase of conducting resistance.
And, the electric field strengthened in drift region and n-type semiconductor region 2 is because the impurity concentration of the first conductivity type of n-type semiconductor region 2 is than low, so the decay of the electric field in n-type semiconductor region 2 can be suppressed, electric field can be made to extend to the lower part of n-type semiconductor region 2.
As mentioned above, the increase of conducting resistance can be suppressed according to the present embodiment, and make withstand voltage lifting by the electric field strengthened in drift region and n-type semiconductor region 2.
In addition, in order to strengthen the electric field in n-type semiconductor region 2 further, the X-direction of preferred part 4b is of a size of more than 4 μm.
In order to suppress the increase of the conducting resistance in semiconductor device, and improve withstand voltage further, more satisfactory for meeting following 2 conditions.
First condition is less than 1.1 times of the impurity level impurity level of second conductivity type of part 4a being set to first conductivity type of the part 3a of the n post area 3 arranged side by side in z-direction with part 4a.
Its reason is: when 1.1 times of the impurity level of first conductivity type of the impurity level overage 3a of second conductivity type of part 4a, the difference of the impurity level of the impurity level of second conductivity type of part 4a and first conductivity type of part 3a becomes greatly, and becomes and be difficult to improve the withstand voltage of drift region.
Second condition is less than 0.9 times of the impurity level impurity level of second conductivity type of part 4b being set to first conductivity type of the part 2a of the n-type semiconductor region 2 arranged side by side in z-direction with part 4b.
Its reason is: when 0.9 times of the impurity level of first conductivity type of the impurity level overage 2a of second conductivity type of part 4b, and the conducting resistance of n-type semiconductor region 2 can increase.
In addition, the size in the more satisfactory Z-direction being n post area 3 is successively decreased in the X direction, and the size in the Z-direction of p post area 4 increases progressively in the X direction.By adopting this formation, can be the more multiple current that circulates during on-state at semiconductor device 100.
Its reason is as described below.
Gate electrode 9 is being applied to the voltage of more than threshold value, when making semiconductor device 100 become on-state, making outflow of bus current between drain electrode 10 and source electrode 11.With this, the voltage between drain electrode 10 and source electrode 11 increases.And, cause vague and general layer to be expanded from n-type semiconductor region 2 and the pn junction between n post area 3 and p post area 4 because of the voltage between drain electrode 10 and source electrode 11.By the expansion of vague and general layer, and the current path in n-type semiconductor region 2 and n post area 3 is narrowed.Now, vague and general layer is expansion more, and the current path in n post area 3 becomes narrower, and saturation current becomes less.Than source electrode 11 side, vague and general layer is easier to be expanded in drain electrode 10 side.Especially, in present embodiment, the part due to p post area 4 is arranged on the impurity concentration of the first conductivity type than low n-type semiconductor region 2, so the vague and general layer in n-type semiconductor region 2 is easily expanded.
But, as present embodiment, by shortening the size in the Z-direction of part 4b, and can size in the Z-direction of incremental portion 2a.Its result, compared with the situation equal with the size in the Z-direction of part 4b with the size in the Z-direction of part 4a, the width of the current path in the n-type semiconductor region 2 when can to widen semiconductor device 100 be on-state, can increase saturation current.
In addition, the carrier density of each semiconductor regions and size such as can use SCM (ScanningCapacitanceMicroscopy, scan-type electrostatic capacitance microscope) and confirm.
Such as, Carrier Profile on the A-A' line investigating represented by Fig. 1 by using SCM, and the size in the Z-direction of the size can investigated in the Z-direction of the carrier density of the core of the Z-direction of the part 4a on A-A' line, the carrier density of core of the Z-direction of part 3a, part 4a and part 3a.
Similarly, such as, Carrier Profile on the B-B' line investigating represented by Fig. 1 by using SCM, and the size in the Z-direction of the size can investigated in the Z-direction of the carrier density of the core of the Z-direction of the part 4b on B-B' line, the carrier density of core of the Z-direction of part 2a, part 4b and part 2a.
(the second execution mode)
Fig. 3 is used to be described the second execution mode of the present invention.
Fig. 3 is the three-dimensional cutaway view of a part for the semiconductor device 200 representing the second execution mode.
In the explanation of following each execution mode, omit the description with the part that the first execution mode has identical structure or a function, mainly the part different from the first execution mode is described.
First execution mode is by making the size in the Z-direction of the size in the Z-direction of n post area 3 and p post area 4 change in the X direction, and the impurity level in each region is changed in the X direction.
In contrast, present embodiment is by making the impurity concentration of the impurity concentration of n post area 3 and p post area 4 change in the X direction, and the impurity level in each region is changed in the X direction.
Size in the Z-direction of n post area 3 is fixing in the X direction.That is, the size in the Z-direction of the bottom of n post area 3 is equal with the size in the Z-direction on the top of n post area 3.
Similarly, the size in the Z-direction of p post area 4 is also fixing in the X direction.Therefore, the size in the Z-direction of part 4a is equal with the size in the Z-direction of part 4b.
The impurity concentration of second conductivity type of part 4a is higher than the impurity concentration of second conductivity type of part 4b.
The impurity concentration of second conductivity type of part 4a is higher than the impurity concentration of first conductivity type of part 3a.And the size in the Z-direction of part 4a is equal with the size in the Z-direction of part 3a.Therefore, the impurity level of second conductivity type of part 4a is larger than the impurity level of first conductivity type of the part 3a of the n post area 3 arranged side by side in z-direction with part 4a.
The impurity concentration of second conductivity type of part 4b is lower than the impurity concentration of first conductivity type of part 2a.And the impurity level of second conductivity type of part 4b is less than the impurity level of first conductivity type of the part 2a of the buffer area arranged side by side in z-direction with part 4b.
If otherwise represent the example shown in Fig. 3, then the carrier density for being positioned at the second conductivity type of the part at the center of Z-direction at part 4a is higher than the carrier density being positioned at the first conductivity type of the part at the center of Z-direction at part 3a.Size in the Z-direction of part 4a is equal with the size in the Z-direction of part 3a.
In addition, the carrier density being positioned at the second conductivity type of the part at the center of Z-direction at part 4b is lower than the carrier density being positioned at the first conductivity type of the part at the center of Z-direction at part 2a.Size in the Z-direction of part 4b is equal with the size in the Z-direction of part 2a.
A-A' is the line at the center of Z-direction by n post area 3.B-B' is the line at the center of Z-direction by p post area 4.
Size in the Z-direction of described each several part also can comprise the inequality in manufacture.
By described formation, the increase of conducting resistance can be suppressed for semiconductor device in the same manner as the first execution mode, and make withstand voltage lifting.
The carrier density of each semiconductor regions and size such as to use SCM (scan-type electrostatic capacitance microscope) to confirm in the same manner as the first execution mode.
Such as, to the semiconductor device 200 represented by Fig. 3, by using SCM to investigate the Carrier Profile on A-A' line and the Carrier Profile on B-B' line, and the carrier density of each semiconductor regions that the line can investigating each divides and size.
(change case)
Then, the change case of Fig. 4 to the second execution mode is used to be described.
Fig. 4 is the three-dimensional cutaway view of a part for the semiconductor device 250 of the change case representing the second execution mode.
In this change case, n post area 3 comprises part 3a and part 3b.Part 3a is arranged on than part 3b more by X-direction side.That is, part 3b is arranged between part 3a and n-type semiconductor region 2.The impurity concentration of first conductivity type of part 3a is higher than the impurity concentration of first conductivity type of part 3b.
P post area 4 comprises part 4a, part 4b and part 4c.Part 4a and part 3a is arranged side by side in z-direction.Part 4c and part 3b is arranged side by side in z-direction.Part 2a in part 4b and n-type semiconductor region 2 is arranged side by side in z-direction.The impurity concentration of second conductivity type of part 4a is higher than the impurity concentration of second conductivity type of part 4c.
The impurity concentration of second conductivity type of part 4a is higher than the impurity concentration of first conductivity type of part 3a.And the size in the Z-direction of part 4a is equal with the size in the Z-direction of part 3a.Therefore, the impurity level of the second conductivity type in part 4a is larger than the impurity level of the first conductivity type in the part 3a of the n post area 3 arranged side by side in z-direction with part 4a.
The impurity concentration of second conductivity type of part 4c is higher than the impurity concentration of first conductivity type of part 3b.And the size in the Z-direction of part 4c is equal with the size in the Z-direction of part 3b.Therefore, the impurity level of the second conductivity type in part 4c is larger than the impurity level of the first conductivity type in the part 3a of the n post area 3 arranged side by side in z-direction with part 4c.But, the impurity level of the second conductivity type in part 4c, with the difference of the impurity level of the first conductivity type in the part 3a impurity level, little with the difference of the impurity level of the first conductivity type in part 3a than the second conductivity type in part 4a.
On the other hand, the impurity level of the second conductivity type in part 4b is less than the impurity level of the first conductivity type in the part 2a of the buffer area arranged side by side in z-direction with part 4b.
In this change case, also in the same manner as the first execution mode, the increase of conducting resistance can be suppressed to semiconductor device, and withstand voltage lifting can be made.
In addition, semiconductor device 200 also in the X direction and then can have the part that impurity concentration is mutually different in n post area 3.Similarly, semiconductor device 200 also in the X direction and then can have the part that impurity concentration is mutually different in p post area 4.
Or the impurity concentration of n post area 3 also can comprise the mode of part 3a and part 3b, changes continuously in the X direction.Similarly, the impurity concentration of p post area 4 also can comprise the mode of part 4a, part 4b and part 4c, changes continuously in the X direction.
Above, each execution mode is illustrated.
But, the size in the impurity concentration of the second conductivity type in part 4a and Z-direction, suitably can to change in the impurity level of the second conductivity type in the part 4a scope larger than the impurity quantitative change of the first conductivity type in part 3a with the size in the impurity concentration of the first conductivity type in part 3a and Z-direction.
Similarly, the size in the impurity concentration of the second conductivity type in part 4b and Z-direction, suitably can to change in the scope that diminishes than the impurity level of the first conductivity type in part 2a of the impurity level of the second conductivity type in part 4b with the size in the impurity concentration of the first conductivity type in part 2a and Z-direction.
Some execution modes of the present invention are illustrated, but these execution modes are pointed out as example, and be not intended to limit scope of invention.The execution mode of these novelties can other various modes be implemented, and in the scope of purport not departing from invention, can carry out various omission, displacement, change.These execution modes or its change are included in scope of invention or purport, and in the scope of the invention be included in described in claims and its equalization.
Claims (14)
1. a semiconductor device, is characterized in that comprising:
First semiconductor regions of the first conductivity type;
Multiple second semiconductor regions, optionally be arranged on described first semiconductor regions, there is the impurity concentration of first conductivity type higher than the impurity concentration of the first conductivity type of described first semiconductor regions, and extend in a first direction, and be mutually separated by the second direction orthogonal with described first direction and arrange;
3rd semiconductor regions of multiple second conductivity type, extend at described first direction, 3rd semiconductor regions of described second conductivity type comprises: Part I, be arranged between adjacent described second semiconductor regions, there is the impurity level of second conductivity type larger than the impurity level of the first conductivity type contained by adjacent described second semiconductor regions; And Part II, be arranged in described first semiconductor regions, there is the impurity level of second conductivity type less than the impurity level of the first conductivity type contained by described first semiconductor regions adjacent in this second direction;
4th semiconductor regions of the second conductivity type, is arranged on described 3rd semiconductor regions;
5th semiconductor regions, is arranged in described 4th semiconductor regions; And
Gate electrode, is arranged on across gate insulating film on described 4th semiconductor regions.
2. semiconductor device according to claim 1, is characterized in that: the size in the described second direction of described Part I is longer than the size in the described second direction of described Part II.
3. semiconductor device according to claim 2, is characterized in that: the impurity concentration of the second conductivity type of described Part I is equal with the impurity concentration of the second conductivity type of described Part II.
4. semiconductor device according to claim 2, is characterized in that: the impurity concentration of the second conductivity type of described Part I is higher than the impurity concentration of the second conductivity type of described Part II.
5. semiconductor device according to claim 1, is characterized in that: the size in the described second direction of described Part I is equal with the size in the described second direction of described Part II.
6. semiconductor device according to claim 5, is characterized in that: the impurity concentration of the second conductivity type of described Part I is higher than the impurity concentration of the second conductivity type of described Part II.
7. semiconductor device according to claim 1, is characterized in that: the impurity concentration of the second conductivity type of described Part I is higher than the impurity concentration of the first conductivity type of described second semiconductor regions.
8. semiconductor device according to claim 7, is characterized in that: the size in the described second direction of described Part I is equal with the size in the described second direction of described second semiconductor regions.
9. semiconductor device according to claim 7, is characterized in that: the size in the described second direction of described Part I is longer than the size in the described second direction of described second semiconductor regions.
10. semiconductor device according to claim 1, is characterized in that: the third direction orthogonal with described first direction and described second direction of described Part II is of a size of more than 4 μm.
11. semiconductor devices according to claim 1, is characterized in that: less than 1.1 times of the impurity level of first conductivity type of impurity level contained by adjacent described second semiconductor regions of the second conductivity type of described Part I;
Less than 0.9 times of the impurity level of first conductivity type of impurity level contained by adjacent described first semiconductor regions of the second conductivity type of described Part II.
12. semiconductor devices according to claim 1, characterized by further comprising: the 6th semiconductor regions being arranged on the second conductivity type on described 4th semiconductor regions, and
The impurity concentration of the second conductivity type of described 6th semiconductor regions is higher than the impurity concentration of the second conductivity type of described 4th semiconductor regions.
13. 1 kinds of semiconductor devices, is characterized in that comprising:
First semiconductor regions of the first conductivity type;
Multiple second semiconductor regions, is optionally arranged on described first semiconductor regions, and extends in a first direction, and be mutually separated by the second direction orthogonal with described first direction and arrange;
3rd semiconductor regions of multiple second conductivity type, extend at described first direction, 3rd semiconductor regions of described second conductivity type comprises: Part I, be arranged between adjacent described second semiconductor regions, in this second direction, the carrier density of the second conductivity type contained by core is equal with the carrier density of the first conductivity type contained by the core of described second semiconductor regions, and has the size longer than the size of described second semiconductor regions; And Part II, be arranged in described first semiconductor regions, in this second direction, the carrier density of the second conductivity type contained by core than described first semiconductor regions core contained by the carrier density of the first conductivity type high, and there is the size shorter than the size of described first semiconductor regions;
4th semiconductor regions of the second conductivity type, is arranged on described 3rd semiconductor regions;
5th semiconductor regions, is arranged in described 4th semiconductor regions; And
Gate electrode, is arranged on across gate insulating film on described 4th semiconductor regions.
14. 1 kinds of semiconductor devices, is characterized in that comprising:
First semiconductor regions of the first conductivity type;
Multiple second semiconductor regions, is optionally arranged on described first semiconductor regions, and extends in a first direction, and be mutually separated by the second direction orthogonal with described first direction and arrange;
3rd semiconductor regions of multiple second conductivity type, extend at described first direction, 3rd semiconductor regions of described second conductivity type comprises: Part I, be arranged between adjacent described second semiconductor regions, in this second direction, the carrier density of the second conductivity type contained by core than described second semiconductor regions core contained by the carrier density of the first conductivity type higher, and there is the size equal with the size of described second semiconductor regions; And Part II, be arranged in described first semiconductor regions, in this second direction, the carrier density of the second conductivity type contained by core than described first semiconductor regions core contained by the carrier density of the first conductivity type lower, and there is the size equal with the size of described first semiconductor regions;
4th semiconductor regions of the second conductivity type, is arranged on described 3rd semiconductor regions;
5th semiconductor regions, is arranged in described 4th semiconductor regions; And
Gate electrode, is arranged on across gate insulating film on described 4th semiconductor regions.
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| Application Number | Priority Date | Filing Date | Title |
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| JP2014156048 | 2014-07-31 | ||
| JP2014-156048 | 2014-07-31 |
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| CN105321946A true CN105321946A (en) | 2016-02-10 |
| CN105321946B CN105321946B (en) | 2019-05-03 |
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| KR (1) | KR20160016520A (en) |
| CN (1) | CN105321946B (en) |
| TW (1) | TWI606574B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113451389A (en) * | 2020-03-24 | 2021-09-28 | 株式会社东芝 | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109643656A (en) * | 2016-09-02 | 2019-04-16 | 新电元工业株式会社 | MOSFET and power conversion circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070272977A1 (en) * | 2006-03-29 | 2007-11-29 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN102723355A (en) * | 2012-06-29 | 2012-10-10 | 电子科技大学 | Groove-gate semiconductor power device |
| CN203644787U (en) * | 2013-12-26 | 2014-06-11 | 厦门元顺微电子技术有限公司 | Optimized-gate N-channel VDMOS power device |
-
2015
- 2015-01-21 KR KR1020150009896A patent/KR20160016520A/en not_active Application Discontinuation
- 2015-03-03 TW TW104106719A patent/TWI606574B/en active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070272977A1 (en) * | 2006-03-29 | 2007-11-29 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| CN102723355A (en) * | 2012-06-29 | 2012-10-10 | 电子科技大学 | Groove-gate semiconductor power device |
| CN203644787U (en) * | 2013-12-26 | 2014-06-11 | 厦门元顺微电子技术有限公司 | Optimized-gate N-channel VDMOS power device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451389A (en) * | 2020-03-24 | 2021-09-28 | 株式会社东芝 | Semiconductor device and method for manufacturing the same |
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| KR20160016520A (en) | 2016-02-15 |
| TW201605021A (en) | 2016-02-01 |
| CN105321946B (en) | 2019-05-03 |
| TWI606574B (en) | 2017-11-21 |
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