KR20160016520A - Semiconductor device - Google Patents

Abstract

A semiconductor device of an embodiment of the present invention comprises a first semiconductor area, a plurality of second semiconductor areas, a plurality of third semiconductor areas, a plurality of fourth semiconductor areas, a fifth semiconductor area and a gate electrode. The second semiconductor area has impurity density of a first conduction type higher than impurity density of the first conduction type of the first semiconductor area. The third semiconductor area includes a first part and a second part. The first part is formed between second semiconductor areas adjacent to each other. The amount of impurities of a second conduction type in the first part is greater than the amount of impurities of the first conduction type included in the adjacent second semiconductor area. The second part is formed in the first semiconductor area. The amount of impurities of the second conduction type in the second part is smaller than the amount of impurities of the first conduction type included in the adjacent first semiconductor area.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

This application is filed under Japanese Patent Application No. 2014-156048 (filed on July 31, 2014) as a basic application. This application is intended to cover all aspects of the basic application by reference to this basic application.

The embodiment to be described later roughly relates to a semiconductor device.

BACKGROUND ART Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are widely used for power conversion devices and power control devices for household electric appliances, communication devices, motor vehicles and the like. These semiconductor devices often require high-speed switching characteristics and reverse blocking characteristics (withstand voltage) of several tens to several hundreds of volts.

The on-resistance of these semiconductor devices largely depends on the electrical resistance of the drift region. The electrical resistance of the drift region depends on the impurity concentration in the drift region. The limit of the impurity concentration of the drift region is determined by the breakdown voltage of the p-n junction formed by the base region and the drift region. That is, when the impurity concentration in the drift region is increased, the breakdown voltage is lowered, and when the breakdown voltage is increased, the impurity concentration in the drift region is lowered. Therefore, there is an opposing relationship between the internal pressure and the on-resistance.

As a means for reducing the on-resistance while maintaining the breakdown voltage, there is a method of using the super junction structure in the drift region. In the super junction structure, a plurality of p-type filler regions and a plurality of n-type filler regions are alternately formed in the substrate in-plane direction. In this super junction structure, by making the amount of impurity contained in the p-type filler region equal to the amount of impurity contained in the n-type filler region, it is possible to increase the impurity concentration in the drift region while maintaining the breakdown voltage.

However, in the semiconductor device, a technique for further increasing the breakdown voltage while suppressing an increase in on-resistance is required.

An embodiment of the present invention provides a semiconductor device capable of further increasing the withstand voltage while suppressing an increase in on-resistance.

A semiconductor device of an embodiment includes a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of fourth semiconductor regions, a fifth semiconductor region, and a gate electrode.

The first semiconductor region is a semiconductor region of the first conductivity type.

The second semiconductor region is a first conductivity type semiconductor region selectively formed on the first semiconductor region. The second semiconductor region has an impurity concentration of the first conductivity type higher than the impurity concentration of the first conductivity type in the first semiconductor region. The second semiconductor region extends in the first direction. And the second semiconductor region is formed to be spaced apart from each other in the second direction orthogonal to the first direction.

The third semiconductor region includes a first portion and a second portion. The third semiconductor region extends in the first direction. The third semiconductor region is a semiconductor region of the second conductivity type.

The first portion is formed between the adjacent second semiconductor regions. The amount of the impurity of the second conductivity type in the first portion is larger than the amount of impurity of the first conductivity type contained in the adjacent second semiconductor region.

And the second portion is formed in the first semiconductor region. The amount of impurity of the second conductivity type in the second portion is smaller than the amount of impurity of the first conductivity type included in the adjacent first semiconductor region.

The fourth semiconductor region is formed on the third semiconductor region. The fourth semiconductor region is a semiconductor region of the second conductivity type.

The fifth semiconductor region is formed in the fourth semiconductor region.

The gate electrode is formed on the fourth semiconductor region via the gate insulating film.

1 is a perspective sectional view showing a part of a semiconductor device according to a first embodiment;
2A to 2D are process cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment;
3 is a perspective sectional view showing a part of a semiconductor device according to a second embodiment;
4 is a perspective sectional view showing a part of a semiconductor device according to a modification of the second embodiment;

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

Also, the drawings are schematic and conceptual, and the relationship between the thickness and the width of each portion, the ratio between the sizes of the portions, and the like are not necessarily the same as those in reality. Even in the case where the same portions are shown, there are cases in which the dimensions and the ratios are different from each other according to the drawings.

In the specification and drawings, elements similar to those described above with reference to the drawings already described are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

(First Embodiment)

1 is a perspective sectional view showing a part of a semiconductor device according to the first embodiment.

In the present embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

The semiconductor device 100 is, for example, a MOSFET.

The semiconductor device 100 includes a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a first conductivity type, a plurality of third semiconductor regions of a second conductivity type, 4 semiconductor region, a fifth semiconductor region of the first conductivity type, and a gate electrode.

The first semiconductor region is, for example, an n-type semiconductor region 2. The second semiconductor region is, for example, an n-filler region 3. The third semiconductor region is, for example, a p-filler region 4. The fourth semiconductor region is, for example, a p base region 5. The fifth semiconductor region is, for example, a source region 6.

The n-type semiconductor region 2 is formed on the drain region 1. the impurity concentration of the first conductivity type in the n-type semiconductor region 2 is lower than the impurity concentration of the first conductivity type in the drain region 1.

The n-type filler region 3 is selectively formed on the n-type semiconductor region 2. The impurity concentration of the first conductivity type in the n-type filler region 3 is higher than the impurity concentration of the first conductivity type in the n-type semiconductor region 2. the impurity concentration of the first conductivity type in the n-type filler region 3 is lower than the impurity concentration of the first conductivity type in the drain region 1. The n filler region 3 extends in the Y direction (first direction). The n filler regions 3 are formed in plural in the Z direction (second direction) perpendicular to the Y direction.

The p-filler region 4 is selectively formed on the n-type semiconductor region 2 so as to be located between the adjacent n-type filler regions 3. That is, the plurality of n-filler regions 3 and the plurality of p-filler regions 4 are alternately formed in the Z-direction. the impurity concentration of the second conductivity type in the p-filler region 4 is higher than the impurity concentration of the first conductivity type in the n-type semiconductor region 2. The p-pillar region 4 extends in the Y-direction. A plurality of p-filler regions 4 are formed spaced apart from each other in the Z direction.

The n-type semiconductor region 2 includes a portion 2a.

The n-filler region 3 includes a portion 3a.

The p-pillar region 4 includes a portion 4a (first portion) and a portion 4b (second portion).

The portion 4a of the p-filler region 4 is formed between the n-filler region 3 adjacent to the portion 4a. The portion 4a is formed at the same depth as the portion 3a of the n-filler region 3. That is, the portion 4a is arranged in parallel with the portion 3a in the Z direction.

and the portion 4b of the p-filler region 4 is formed in the n-type semiconductor region 2. However, the p-filler region 4 does not reach the drain region 1. That is, between the p-type filler region 4 and the drain region 1, the n-type semiconductor region 2 is present. The portion 4b is formed at the same depth as that of the portion 2a of the n-type semiconductor region 2. That is, the portion 4b is arranged in parallel with the portion 2a in the Z direction.

the dimension of the n-filler region 3 in the Z direction decreases in the X direction orthogonal to the Y direction and the Z direction. Therefore, the dimension in the Z direction at the upper portion of the n-pillar region 3 is shorter than the dimension in the lower direction of the n-pillar region 3 in the Z direction.

On the other hand, the dimension of the p-pillar region 4 in the Z-direction increases in the X-direction. Therefore, the dimension of the portion 4a in the Z direction is longer than the dimension of the portion 4b in the Z direction.

The impurity concentration of the second conductivity type in the portion 4a is equal to the impurity concentration of the first conductivity type in the portion 3a aligned in the Z direction with the portion 4a. The dimension of the portion 4a in the Z direction is longer than the dimension of the portion 3a in the Z direction. Therefore, the amount of the impurity of the second conductivity type included in the portion 4a is larger than the amount of impurities of the first conductivity type included in the portion 3a.

The impurity concentration of the second conductivity type in the portion 4b is higher than the impurity concentration of the first conductivity type in the portion 2a aligned in the Z direction with the portion 4b. The dimension of the portion 4b in the Z direction is shorter than the dimension of the portion 2a in the Z direction. The amount of the impurity of the second conductivity type contained in the portion 4b is smaller than the amount of impurities of the first conductivity type included in the portion 2a.

The amount of impurities in each region can be obtained, for example, by multiplying the impurity concentration of each region by the volume of each region.

The carrier density in each semiconductor region is proportional to the impurity concentration in each semiconductor region.

1, according to another expression, the carrier density of the first conductivity type in the portion located at the center in the Z direction in the portion 3a is smaller than the carrier density in the Z direction in the portion 4a Is equal to the carrier density of the second conductivity type in the portion located at the center of the second conductivity type. The dimension of the portion 4a in the Z direction is longer than the dimension of the portion 3a in the Z direction.

The carrier density of the second conductivity type in the portion located at the center in the Z direction in the portion 4b is the same as the carrier density of the first conductivity type in the portion located at the center in the Z direction in the portion 2a Is higher than the carrier density. The dimension of the portion 4b in the Z direction is shorter than the dimension of the portion 2a in the Z direction.

The line A-A 'is a line passing through the center of the n-filler region 3 in the Z direction and extending in the X direction. The line B-B 'is a line passing through the center of the p-pillar region 4 in the Z-direction and extending in the X-direction.

The carrier density of each of the above-described portions may include manufacturing variations.

A portion of the n-filler region 3 and the p-filler region 4 form a so-called super junction structure.

In the following description, the region including the n-filler region 3 and the portion 4a and forming the superjunction structure is referred to as a drift region.

The p base region 5 is selectively formed on the drift region.

The source region 6 is formed in the p base region 5. The impurity concentration of the first conductivity type in the source region 6 is higher than the impurity concentration of the first conductivity type in the n-filler region 3. The p base region 5 and the source region 6 extend in the Y direction. A plurality of p-type base regions 5 and source regions 6 are formed in the Z direction.

The contact region 7 is formed in the p base region 5. The contact regions 7 are formed between the source regions 6 formed in the same p base region 5. The impurity concentration of the second conductivity type in the contact region 7 is higher than the impurity concentration of the second conductivity type in the p base region 5. [ The contact region 7 is connected to a source electrode 11 to be described later. The contact region 7 is not essential for the present embodiment. However, in order to efficiently discharge the holes in the n-filler region 3 to the source electrode 11, it is preferable that the contact region 7 is formed. The contact region 7 extends in the Y direction. A plurality of contact regions 7 are formed in the Z direction.

The gate electrode 9 is formed on the n-filler region 3 and the p base region 5 with the gate insulating film 8 interposed therebetween. The gate electrode 9 is opposed to a part of the n-filler region 3 and a part of the p base region 5. The gate electrode 9 extends in the Y direction. A plurality of gate electrodes 9 are formed in the Z direction.

By applying a voltage equal to or higher than the threshold value to the gate electrode 9, the MOSFET is turned on and a channel (inversion layer) is formed on the surface of the p base region 5.

The depletion layer expands from the pn junction plane of the n-filler region 3 and the p-filler region 4 to the n-filler region 3 and the p-filler region 4 when the MOSFET is in the OFF state. the breakdown voltage can be improved by the depletion layer extending to the n-filler region 3 and the p-filler region 4. [

A drain electrode 10 is formed on the surface of the drain region 1 opposite to the n-type semiconductor region 2. The drain electrode 10 is connected to the drain region 1.

The source electrode 11 is formed on the source region 6 and on the contact region 7 and is connected to these regions.

Here, an example of a manufacturing method of the semiconductor device 100 will be described with reference to FIG.

2 is a process sectional view showing a manufacturing process of the semiconductor device 100 according to the first embodiment.

First, as shown in Fig. 2A, a semiconductor substrate 21 of a first conductivity type is prepared.

Next, as shown in FIG. 2B, the first conductive semiconductor layer 31 is epitaxially grown on the semiconductor substrate 21.

Next, as shown in FIG. 2C, a trench T is formed in the semiconductor substrate 21 and the semiconductor layer 31 which is epitaxially grown. The trench T is formed by, for example, RIE (Reactive Ion Etching). The trench T is formed such that the width at the top of the trench T is wider than the width at the bottom. The width of the upper portion of the trench T and the width of the lower portion of the trench T can be controlled by adjusting the kind of the reactive gas, the pressure of the reactive gas, the applied electric power, or the like when the trench is formed by the RIE method have. The semiconductor substrate 21 after forming the trench T corresponds to the n-type semiconductor region 2. The semiconductor layer 31 after forming the trench T corresponds to the n-filler region 3.

Next, as shown in Fig. 2D, the p-type pillar region 4 is formed by epitaxially growing the second conductive semiconductor layer in the trench T formed.

Next, a source region 6, a contact region 7, a gate insulating film 8, a gate electrode 9, and a source electrode 11 are formed on the drift region. 1 is formed by forming the drain region 1 in the region opposite to the drift region of the n-type semiconductor region 2 and forming the drain electrode 10 on the drain region 1, ) Is obtained.

2 shows an example in which a trench is formed by RIE and a semiconductor layer is epitaxially grown on the trench. Alternatively, the p-filler region 4 whose upper dimension in the Z-direction is larger than the dimension in the lower direction in the Z-direction may be formed by ion implantation. However, a method of forming a pillar region 4 by forming a trench is preferable for ease of manufacturing and reduction of fluctuation of impurity concentration in the p-pillar region 4.

The operation and effect of this embodiment will be described.

First, the amount of the impurity of the second conductivity type in the portion 4a is set to be larger than the amount of the impurity of the first conductivity type in the portion 3a of the n-filler region 3 arranged in the Z- By making the amount larger than the amount of water, the electric field in the drift region can be made strong.

Next, by forming the portion 4b in the n-type semiconductor region 2, the electric field in the n-type semiconductor region 2 can be strengthened. At this time, the electric field intensity in the n-type semiconductor region 2 is influenced by the electric field intensity in the drift region. Therefore, by forming the portion 4b in the n-type semiconductor region 2 in addition to making the amount of the impurity in the portion 4a larger than the amount of impurities in the portion 3a as described above, A strong electric field is generated in the region 2. As a result, the breakdown voltage can be greatly improved.

On the other hand, by making the amount of the impurity of the second conductivity type in the portion 4b smaller than the amount of impurity of the first conductivity type in the portion 4b and the portion 2a of the buffer region arranged in the Z direction , An increase in on-resistance can be suppressed. That is, even when the portion 4b is formed in the n-type semiconductor region 2, the depletion layer extending from the portion 4b toward the direction opposite to the Z direction and the Z direction is suppressed, Can be suppressed.

Since the impurity concentration of the first conductivity type of the n-type semiconductor region 2 is low, the electric field intensified in the drift region and the n-type semiconductor region 2 can be suppressed by decreasing the attenuation of the electric field in the n- It becomes possible to extend the electric field to the lower portion of the n-type semiconductor region 2 more.

As described above, according to the present embodiment, the breakdown voltage can be improved by increasing the electric field in the drift region and the n-type semiconductor region 2 while suppressing the increase in on-resistance.

In order to make the electric field in the n-type semiconductor region 2 stronger, the dimension of the portion 4b in the X direction is preferably 4 m or more.

In order to increase the breakdown voltage while suppressing the increase of the on-resistance in the semiconductor device, it is preferable that the following two conditions are satisfied.

The first condition is that the amount of impurities of the second conductivity type in the portion 4a is larger than the amount of impurities in the portion 4a in the portion 3a of the n-filler region 3 arranged in the Z- Of the amount of impurities in the water.

This is because when the amount of the impurity of the second conductivity type in the portion 4a exceeds 1.1 times the amount of impurity of the first conductivity type in the portion 3a, And the amount of the impurity of the first conductivity type in the portion 3a becomes large, and it becomes difficult to improve the breakdown voltage in the drift region.

The second condition is that the amount of the impurity of the second conductivity type in the portion 4b is larger than the amount of impurity in the portion 4b in the portion 2a of the n-type semiconductor region 2 arranged in the Z- Of the impurity quantity of the mold.

This is because when the amount of the impurity of the second conductivity type in the portion 4b exceeds 0.9 times the amount of the impurity of the first conductivity type in the portion 2a, This is because the resistance may increase.

It is also preferable that the dimension of the n-filler region 3 in the Z-direction decreases in the X-direction and the dimension of the p-filler region 4 in the Z-direction increases in the X-direction. By employing this configuration, it becomes possible to flow more current when the semiconductor device 100 is in the ON state.

The reason for this is as follows.

A current flows between the drain electrode 10 and the source electrode 11 when a voltage equal to or higher than a threshold value is applied to the gate electrode 9 and the semiconductor device 100 is turned on. Accordingly, the voltage between the drain electrode 10 and the source electrode 11 is increased. The voltage between the drain electrode 10 and the source electrode 11 causes a depletion layer from the pn junction between the n-type semiconductor region 2 and the n-filler region 3 and the p-filler region 4 . As the depletion layer expands, the current path in the n-type semiconductor region 2 and the n-pillar region 3 becomes narrow. At this time, the larger the depletion layer, the narrower the current path in the n-filler region 3, and the saturation current becomes smaller. The depletion layer is more likely to expand on the side of the drain electrode 10 than on the side of the source electrode 11. Particularly, in the present embodiment, part of the p-type pillar region 4 is formed in the n-type semiconductor region 2 having a low impurity concentration of the first conductivity type. Therefore, It is easy to expand the pit layer.

However, as in the present embodiment, by shortening the dimension of the portion 4b in the Z direction, the dimension in the Z direction in the portion 2a can be made longer. As a result, as compared with the case where the dimension in the Z direction of the portion 4a is equal to the dimension in the Z direction of the portion 4b, the n-type semiconductor region 2) can be made wider, and the saturation current can be increased.

Further, the carrier density and dimensions in each semiconductor region can be confirmed by using, for example, SCM (scanning type capacitance microscope).

The carrier distribution on the line A-A 'shown in Fig. 1 is examined using the SCM to determine the carrier on the line A-A' The density of the portion 3a, the carrier density of the center portion in the Z direction, the dimension of the portion 4a in the Z direction, and the dimension of the portion 3a in the Z direction.

Likewise, by using the SCM, the carrier distribution on the line B-B 'shown in FIG. 1 is examined, and the distribution of the center portion in the Z direction of the portion 4b on the line B-B' The carrier density of the center portion of the portion 2a in the Z direction, the dimension of the portion 4b in the Z direction, and the dimension of the portion 2a in the Z direction.

(Second Embodiment)

A second embodiment of the present invention will be described with reference to Fig.

3 is a perspective sectional view showing a part of the semiconductor device 200 according to the second embodiment.

In the following description of each embodiment, description of parts having the same structure or function as those of the first embodiment will be omitted, and a part mainly different from the first embodiment will be described.

In the first embodiment, by changing the dimension in the Z direction of the n-pillar region 3 and the dimension in the Z direction of the p-pillar region 4 in the X direction, the amount of impurity in each region is changed in the X direction Respectively.

In contrast, in the present embodiment, the impurity concentration in the n-filler region 3 and the impurity concentration in the p-filler region 4 are changed in the X-direction, thereby changing the amount of impurities in each region in the X-direction.

The n filler region 3 has a constant dimension in the Z direction in the X direction. That is, the dimension in the Z direction in the lower portion of the n-filler region 3 is equal to the dimension in the Z direction in the upper portion of the n-filler region 3. [

Similarly, the p-filler region 4 is also constant in dimension in the Z-direction in the X-direction. Therefore, the dimension of the portion 4a in the Z direction is equal to the dimension of the portion 4b in the Z direction.

The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the second conductivity type of the portion 4b.

The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the first conductivity type of the portion 3a. The dimension of the portion 4a in the Z direction is equal to the dimension of the portion 3a in the Z direction. Therefore, the amount of the impurity of the second conductivity type in the portion 4a is equal to the amount of the impurity of the first conductivity type in the portion 3a of the n-filler region 3 which is arranged in parallel with the portion 4a in the Z- Is greater than the amount of impurities.

The impurity concentration of the second conductivity type of the portion 4b is lower than the impurity concentration of the first conductivity type of the portion 2a. The amount of impurity of the second conductivity type in the portion 4b is smaller than the amount of impurity of the first conductivity type in the portion 2a of the buffer region which is arranged in parallel with the portion 4b in the Z direction.

3, the carrier density of the second conductivity type in the portion located at the center in the Z direction in the portion 4a is larger than the carrier density in the Z direction in the portion 3a Is higher than the carrier density of the first conductivity type in the portion located in the second conductivity type. The dimension of the portion 4a in the Z direction is equal to the dimension of the portion 3a in the Z direction.

The carrier density of the second conductivity type in the portion located at the center in the Z direction in the portion 4b is the same as the carrier density of the first conductivity type in the portion located at the center in the Z direction in the portion 2a Is lower than the carrier density. The dimension of the portion 4b in the Z direction is equal to the dimension of the portion 2a in the Z direction.

A-A 'is a line passing through the center of the n-filler region 3 in the Z direction. B-B 'is a line passing through the center of the p-pillar region 4 in the Z direction.

The dimensions of each of the above-described portions in the Z direction may include manufacturing variations.

With the above-described structure, as in the first embodiment, in the semiconductor device, it is possible to improve the breakdown voltage while suppressing an increase in on-resistance.

The carrier density and dimensions in each semiconductor region can be confirmed by using, for example, SCM (scanning-type capacitance microscope) as in the first embodiment.

For example, with respect to the semiconductor device 200 shown in Fig. 3, the carrier distribution on the line A-A 'and the carrier distribution on the line B-B' are examined using the SCM, The carrier density and dimensions of each semiconductor region on the line segment can be examined.

(Modified example)

Next, a modified example of the second embodiment will be described with reference to Fig.

4 is a perspective sectional view showing a part of a semiconductor device 250 according to a modification of the second embodiment.

In this modification, the n-filler region 3 includes a portion 3a and a portion 3b. The portion 3a is formed on the X direction side rather than the portion 3b. That is, the portion 3b is formed between the portion 3a and the n-type semiconductor region 2. The impurity concentration of the first conductivity type of the portion 3a is higher than the impurity concentration of the first conductivity type of the portion 3b.

The p-pillar region 4 includes a portion 4a, a portion 4b, and a portion 4c. The portion 4a is arranged in parallel with the portion 3a in the Z direction. The portion 4c is arranged in parallel with the portion 3b in the Z direction. The portion 4b is arranged in parallel with the portion 2a of the n-type semiconductor region 2 in the Z direction. The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the second conductivity type of the portion 4c.

The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the first conductivity type of the portion 3a. The dimension of the portion 4a in the Z direction is equal to the dimension of the portion 3a in the Z direction. Therefore, the amount of the impurity of the second conductivity type in the portion 4a is equal to the amount of the impurity of the first conductivity type in the portion 3a of the n-filler region 3 which is arranged in parallel with the portion 4a in the Z- Is greater than the amount of impurities.

The impurity concentration of the second conductivity type in the portion 4c is higher than the impurity concentration of the first conductivity type in the portion 3b. The dimension of the portion 4c in the Z direction is equal to the dimension of the portion 3b in the Z direction. Therefore, the amount of the impurity of the second conductivity type in the portion 4c is larger than the amount of the impurity of the first conductivity type in the portion 3a of the n-filler region 3 which is arranged in parallel with the portion 4c in the Z- Is greater than the amount of impurities. However, the difference between the amount of the impurity of the second conductivity type in the portion 4c and the amount of impurity of the first conductivity type in the portion 3a is larger than the amount of impurity of the second conductivity type in the portion 4a , And the amount of the impurity of the first conductivity type in the portion (3a).

On the other hand, the amount of the impurity of the second conductivity type in the portion 4b is smaller than the amount of impurity of the first conductivity type in the portion 2a of the buffer region which is arranged in parallel with the portion 4b in the Z direction.

In this modification, as in the first embodiment, the breakdown voltage can be improved in the semiconductor device while suppressing an increase in on-resistance.

In addition, the semiconductor device 200 may further include portions where the impurity concentrations are different from each other in the n-filler region 3 in the X direction. Likewise, the semiconductor device 200 may further include, in the p-filler region 4 in the X direction, portions different in impurity concentration from each other.

Alternatively, the impurity concentration of the n-filler region 3 may be continuously changed in the X direction so as to include the portion 3a and the portion 3b. Similarly, the impurity concentration of the p-pillar region 4 may be continuously changed in the X direction so as to include the portion 4a, the portion 4b, and the portion 4c.

The embodiments have been described above in detail.

Note that the impurity concentration of the second conductivity type and the dimension in the Z direction in the portion 4a and the impurity concentration of the first conductivity type in the portion 3a and the dimension in the Z direction are the same The amount of the impurity of the second conductivity type in the portion (4a) is larger than the amount of the impurity of the first conductivity type in the portion (3a).

Similarly, the impurity concentration of the second conductivity type and the dimension in the Z direction in the portion 4b, the impurity concentration of the first conductivity type in the portion 2a, and the dimension in the Z direction are the same 4b can be appropriately changed in such a range that the amount of the impurity of the second conductivity type in the portion 2a becomes smaller than the amount of impurity of the first conductivity type in the portion 2a.

While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and alterations can be made without departing from the gist of the invention. These embodiments and their modifications fall within the scope and spirit of the invention, and are included in the scope of the invention as defined in the claims and their equivalents.

Claims (14)

A first semiconductor region of a first conductivity type,
And an impurity concentration of the first conductivity type higher than an impurity concentration of the first conductivity type in the first semiconductor region, the impurity concentration of the first conductivity type being higher than that of the first conductivity type in the first direction, A plurality of second semiconductor regions formed apart from each other in a second direction,
A first portion formed between the adjacent second semiconductor regions and having an impurity amount of a second conductivity type larger than that of the first conductivity type included in the adjacent second semiconductor region,
And a second portion having an impurity amount of the second conductivity type smaller than that of the first conductivity type included in the first semiconductor region which is adjacent to the first semiconductor region in the second direction,
A plurality of third semiconductor regions of a second conductivity type extending in the first direction,
A fourth semiconductor region of a second conductivity type formed on the third semiconductor region,
A fifth semiconductor region formed in the fourth semiconductor region,
A gate electrode formed on the fourth semiconductor region,
And the semiconductor device. The method according to claim 1,
And the dimension of the first portion in the second direction is longer than the dimension of the second portion in the second direction. 3. The method of claim 2,
And the impurity concentration of the second conductivity type of the first portion is equal to the impurity concentration of the second conductivity type of the second portion. 3. The method of claim 2,
And the impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the second conductivity type of the second portion. The method according to claim 1,
And the dimension of the first portion in the second direction is equal to the dimension of the second portion in the second direction. 6. The method of claim 5,
And the impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the second conductivity type of the second portion. The method according to claim 1,
And the impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the first conductivity type of the second semiconductor region. 8. The method of claim 7,
And the dimension of the first portion in the second direction is equal to the dimension of the second semiconductor region in the second direction. 8. The method of claim 7,
And the dimension of the first portion in the second direction is longer than the dimension of the second semiconductor region in the second direction. The method according to claim 1,
And the dimension of the second portion in the first direction and the third direction orthogonal to the second direction is 4 占 퐉 or more. The method according to claim 1,
The amount of the impurity of the second conductivity type in the first portion is 1.1 times or less the amount of the impurity of the first conductivity type contained in the adjacent second semiconductor region,
And the amount of impurities of the second conductivity type in the second portion is 0.9 times or less the amount of impurities of the first conductivity type contained in the adjacent first semiconductor region. The method according to claim 1,
And a sixth semiconductor region of a second conductivity type formed over the fourth semiconductor region,
And the impurity concentration of the second conductivity type of the sixth semiconductor region is higher than the impurity concentration of the second conductivity type of the fourth semiconductor region. A first semiconductor region of a first conductivity type,
A plurality of second semiconductor regions selectively formed on the first semiconductor region and extending in a first direction and spaced apart from each other in a second direction orthogonal to the first direction;
A carrier density of a second conductivity type included in the central portion in the second direction is formed between the adjacent second semiconductor regions and the carrier density of the first conductivity type included in the central portion of the second semiconductor region A first portion that is equal to the carrier density and has a dimension longer than the dimension of the second semiconductor region,
The carrier density of the second conductivity type included in the central portion in the second direction is higher than the carrier density of the first conductivity type included in the central portion of the first semiconductor region, A second portion having a dimension smaller than the dimension of the first semiconductor region,
A plurality of third semiconductor regions of a second conductivity type extending in the first direction,
A fourth semiconductor region of a second conductivity type formed on the third semiconductor region,
A fifth semiconductor region formed in the fourth semiconductor region,
A gate electrode formed on the fourth semiconductor region,
And the semiconductor device. A first semiconductor region of a first conductivity type,
A plurality of second semiconductor regions selectively formed on the first semiconductor region and extending in a first direction and spaced apart from each other in a second direction orthogonal to the first direction;
A carrier density of a second conductivity type included in the central portion in the second direction is formed between the adjacent second semiconductor regions and the carrier density of the first conductivity type included in the central portion of the second semiconductor region A first portion having a height higher than the carrier density and having a dimension equivalent to that of the second semiconductor region,
The carrier density of the second conductivity type included in the central portion in the second direction is lower than the carrier density of the first conductivity type included in the central portion of the first semiconductor region, A second portion having a dimension equivalent to that of the first semiconductor region,
A plurality of third semiconductor regions of a second conductivity type extending in the first direction,
A fourth semiconductor region of a second conductivity type formed on the third semiconductor region,
A fifth semiconductor region formed in the fourth semiconductor region,
A gate electrode formed on the fourth semiconductor region,
And the semiconductor device.

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