TWI606574B - Semiconductor device - Google Patents

Description

Semiconductor device [related application]

This application is entitled to the priority of the application based on Japanese Patent Application No. 2014-156048 (application date: July 31, 2014). This application contains the entire contents of the basic application by reference to the basic application.

The following embodiments relate generally to a semiconductor device.

Semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor) are widely used in household appliances, communication equipment, and vehicle motors. Power conversion equipment or power control equipment, etc. In many cases, such semiconductor devices are required to have high-speed switching characteristics or reverse blocking characteristics (withstand voltage) of several tens to hundreds of volts.

The on-resistance of these semiconductor devices is largely dependent on the resistance of the drift region. The resistance of the drift region depends on the impurity concentration of the drift region. The limit of the impurity concentration of the drift region is determined by the withstand voltage of the p-n junction formed by the base region and the drift region. That is, when the impurity concentration in the drift region is increased, the withstand voltage is lowered, and when the withstand voltage is increased, the impurity concentration in the drift region is lowered. Therefore, there is a trade-off between the withstand voltage and the on-resistance.

As one of the methods for reducing the on-resistance while maintaining the withstand voltage, there is a method of using a super junction structure in the drift region. The super junction structure is provided with a plurality of p-type pillar regions and a plurality of n-type pillar regions alternately arranged in the in-plane direction of the substrate. The super junction structure is borrowed By making the amount of impurities contained in the p-type pillar region equal to the amount of impurities contained in the n-type pillar region, it is possible to increase the impurity concentration in the drift region while maintaining the withstand voltage.

However, there has been a demand for a semiconductor device that suppresses an increase in on-resistance while further increasing the withstand voltage.

According to an embodiment of the present invention, a semiconductor device capable of further improving a withstand voltage while suppressing an increase in on-resistance is provided.

The semiconductor device of the embodiment includes a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of fourth semiconductor regions, a fifth semiconductor region, and a gate electrode.

The first semiconductor region is a semiconductor region of a first conductivity type.

The second semiconductor region is selectively provided in the first conductivity type semiconductor region on the first semiconductor region. The second semiconductor region has a first conductivity type impurity concentration higher than that of the first conductivity type of the first semiconductor region. The second semiconductor region extends in the first direction. The second semiconductor region is provided apart from each other in the second direction orthogonal to the first direction.

The third semiconductor region includes a first portion and a second portion. The third semiconductor region extends in the first direction. The third semiconductor region is a semiconductor region of the second conductivity type.

The first portion is disposed between adjacent second semiconductor regions. The impurity amount of the second conductivity type of the first portion is larger than the impurity amount of the first conductivity type included in the adjacent second semiconductor region.

The second portion is disposed in the first semiconductor region. The impurity amount of the second conductivity type of the second portion is smaller than the impurity amount of the first conductivity type included in the adjacent first semiconductor region.

The fourth semiconductor region is provided on the third semiconductor region. The fourth semiconductor region is a semiconductor region of the second conductivity type.

The fifth semiconductor region is provided in the fourth semiconductor region.

The gate electrode is provided on the fourth semiconductor region via a gate insulating film.

1‧‧‧Bungee area

2‧‧‧Semiconductor area

2a‧‧‧Parts

3‧‧‧n pillar area

Section 3a‧‧‧

Section 3b‧‧‧

4‧‧‧p pillar area

4a‧‧‧Parts

4b‧‧‧section

4c‧‧‧section

5‧‧‧p base region

6‧‧‧ source area

7‧‧‧Contact area

8‧‧‧Gate insulation film

9‧‧‧ gate electrode

10‧‧‧汲electrode

11‧‧‧Source electrode

21‧‧‧Semiconductor substrate

31‧‧‧Semiconductor layer

100‧‧‧Semiconductor device

200‧‧‧Semiconductor device

250‧‧‧Semiconductor device

Fig. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to a first embodiment.

2A to 2D are cross-sectional views showing the steps of manufacturing the semiconductor device of the first embodiment.

Fig. 3 is a perspective cross-sectional view showing a part of the semiconductor device of the second embodiment.

Fig. 4 is a perspective cross-sectional view showing a part of a semiconductor device according to a modification of the second embodiment.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

Furthermore, the schema is model or conceptual, and the relationship between the thickness and the width of each part, the ratio of the sizes of the parts, and the like are not necessarily the same as the actual things. Further, even in the case of indicating the same portion, there are cases in which the dimensions or ratios are different depending on the schema.

In the present specification and the drawings, the same components as those described above are denoted by the same reference numerals, and the detailed description is omitted as appropriate.

(First embodiment)

Fig. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to a first embodiment.

In the present embodiment, a case where the first conductivity type is an n-type and the second conductivity type is a p-type will be described. However, the first conductivity type may be a p-type and the second conductivity type may be an n-type.

The semiconductor device 100 is, for example, a MOSFET.

The semiconductor device 100 includes a first semiconductor region of a first conductivity type, a second semiconductor region of a plurality of first conductivity types, a third semiconductor region of a plurality of second conductivity types, a fourth semiconductor region of a second conductivity type, and a first semiconductor region. The fifth semiconductor region of the conductivity type and the gate electrode.

The first semiconductor region is, for example, an n-type semiconductor region 2 . The second semiconductor region is, for example, an n pillar region 3 . The third semiconductor region is, for example, the p pillar region 4 . The fourth semiconductor region is, for example, a p base region 5. The fifth semiconductor region is, for example, the source region 6.

The n-type semiconductor region 2 is provided on the drain region 1. The impurity concentration of the first conductivity type of the n-type semiconductor region 2 is lower than the impurity concentration of the first conductivity type of the drain region 1.

The n-pillar region 3 is selectively provided on the n-type semiconductor region 2. The impurity concentration of the first conductivity type of the n pillar region 3 is higher than the impurity concentration of the first conductivity type of the n-type semiconductor region 2. The impurity concentration of the first conductivity type of the n pillar region 3 is lower than the impurity concentration of the first conductivity type of the drain region 1. The n-pillar region 3 extends in the Y direction (first direction). The n-pillar region 3 is provided in plural numbers apart from each other in the Z direction (second direction) orthogonal to the Y direction.

The p-pillar region 4 is selectively provided on the n-type semiconductor region 2 so as to be located between the adjacent n-pillar regions 3. That is, a plurality of n-pillar regions 3 and a plurality of p-pillar regions 4 are alternately arranged in the Z direction. The impurity concentration of the second conductivity type of the p pillar region 4 is higher than the impurity concentration of the first conductivity type of the n-type semiconductor region 2. The p-pillar region 4 extends in the Y direction. The p-pillar regions 4 are provided in plural numbers apart from each other in the Z direction.

The n-type semiconductor region 2 includes a portion 2a.

The n-pillar region 3 includes a portion 3a.

The p-pillar region 4 includes a portion 4a (first portion) and a portion 4b (second portion).

The portion 4a of the p-pillar region 4 is disposed between the n-pillar regions 3 adjacent to the portion 4a. The portion 4a is disposed at the same depth as the portion 3a of the n-pillar region 3. That is, the portion 4a and the portion 3a are juxtaposed in the Z direction.

A portion 4b of the p-pillar region 4 is disposed in the n-type semiconductor region 2. However, the p-pillar region 4 does not reach the drain region 1. That is, the n-type semiconductor region 2 exists between the p pillar region 4 and the drain region 1. The portion 4b is disposed at the same depth as the portion 2a of the n-type semiconductor region 2. That is, the portion 4b and the portion 2a are juxtaposed in the Z direction.

The dimension of the n-pillar region 3 in the Z direction is decreased in the X direction orthogonal to the Y direction and the Z direction. Therefore, the dimension in the Z direction of the upper portion of the n pillar region 3 is shorter than the dimension in the Z direction of the lower portion of the n pillar region 3.

On the other hand, the dimension of the p-pillar region 4 in the Z direction is increased in the X direction. because Thus, the dimension of the portion 4a in the Z direction is longer than the dimension of the portion 4b in the Z direction.

The impurity concentration of the second conductivity type of the portion 4a is equal to the impurity concentration of the first conductivity type of the portion 3a of the portion 4a juxtaposed in the Z direction. Moreover, the dimension in the Z direction of the portion 4a is longer than the dimension in the Z direction of the portion 3a. Therefore, the amount of impurities of the second conductivity type contained in the portion 4a is larger than that of the first conductivity type contained in the portion 3a.

The impurity concentration of the second conductivity type of the portion 4b is higher than the impurity concentration of the first conductivity type of the portion 2a of the portion 4b juxtaposed in the Z direction. The dimension in the Z direction of the portion 4b is shorter than the dimension in the Z direction of the portion 2a. The impurity amount of the second conductivity type contained in the portion 4b is smaller than the impurity amount of the first conductivity type contained in the portion 2a.

The amount of impurities in each region can be determined, for example, by the product of the impurity concentration of each region and the volume of each region.

The carrier density of each semiconductor region is proportional to the impurity concentration of each semiconductor region.

Therefore, if the example shown in Fig. 1 is otherwise shown, the carrier density of the first conductivity type in the portion where the portion 3a is located at the center of the Z direction and the second conductivity of the portion of the portion 4a located at the center of the Z direction are The type of carrier has the same density. The dimension in the Z direction of the portion 4a is longer than the dimension in the Z direction of the portion 3a.

Further, the carrier density of the second conductivity type in the portion where the portion 4b is located at the center of the Z direction is higher than the carrier density of the first conductivity type in the portion where the portion 2a is located at the center of the Z direction. The dimension in the Z direction of the portion 4b is shorter than the dimension in the Z direction of the portion 2a.

Further, the A-A' line passes through the center of the Z-direction of the n-pillar region 3 and extends in the X direction. The B-B' line passes through the center of the Z-direction of the p-pillar region 4 and extends in the X direction.

The carrier density of each of the above sections may also include manufacturing variations.

The n-pillar region 3 and one of the p-pillar regions 4 form a so-called super junction structure.

In the following description, the n pillar region 3 and the portion 4a are included, and the region in which the super junction structure is formed is referred to as a drift region.

The p base region 5 is selectively disposed on the drift region.

The source region 6 is disposed in the p base region 5. The impurity concentration of the first conductivity type of the source region 6 is higher than the impurity concentration of the first conductivity type of the n pillar region 3. The p base region 5 and the source region 6 extend in the Y direction. The p base region 5 and the source region 6 are provided in plural in the Z direction.

The contact region 7 is provided in the p base region 5. Further, the contact region 7 is provided between the source regions 6 which are also provided in the p base region 5. The impurity concentration of the second conductivity type of the contact region 7 is higher than the impurity concentration of the second conductivity type of the p base region 5. The contact region 7 is connected to the source electrode 11 described below. The contact region 7 is not essential in the present embodiment. However, in order to efficiently discharge the holes in the n-pillar region 3 to the source electrode 11, the contact region 7 is preferably provided. The contact area 7 extends in the Y direction. Further, the contact region 7 is provided in plural in the Z direction.

The gate electrode 9 is provided on the n pillar region 3 and the p base region 5 via the gate insulating film 8. The gate electrode 9 is opposed to a portion of the n-pillar region 3 and a portion of the p-base region 5. The gate electrode 9 extends in the Y direction. Further, the gate electrode 9 is provided in plural in the Z direction.

By applying a voltage equal to or higher than a threshold value to the gate electrode 9, the MOSFET is turned on, and a channel (inversion layer) is formed on the surface of the p base region 5.

When the MOSFET is in the off state, the depletion layer extends from the pn junction of the n pillar region 3 and the p pillar region 4 toward the n pillar region 3 and the p pillar region 4. The withstand voltage is increased by expanding the depletion layer to the n-pillar region 3 and the p-pillar region 4.

A drain electrode 10 is provided on a surface of the drain region 1 opposite to the n-type semiconductor region 2. The drain electrode 10 is connected to the drain region 1.

The source electrode 11 is disposed on the source region 6 and on the contact region 7, and is connected to the regions.

Here, an example of a method of manufacturing the semiconductor device 100 will be described with reference to FIG. 2 .

FIG. 2 is a cross-sectional view showing the steps of manufacturing the semiconductor device 100 of the first embodiment.

First, as shown in FIG. 2A, a semiconductor substrate 21 of a first conductivity type is prepared.

Next, as shown in FIG. 2B, the semiconductor layer 31 of the first conductivity type is epitaxially grown on the semiconductor substrate 21.

Then, as shown in FIG. 2C, a trench T is formed on the semiconductor substrate 21 and the epitaxially grown semiconductor layer 31. The trench T is formed by, for example, RIE (Reactive Ion Etching). The trench T is formed such that the width of the upper portion of the trench T is wider than the width of the lower portion. The width of the upper portion of the trench T and the width of the lower portion of the trench T can be controlled by adjusting the type of the reactive gas when the trench is formed by the RIE method, the force of the reactive gas, or the input of electric power. The semiconductor substrate 21 after the trench T is formed corresponds to the n-type semiconductor region 2. Further, the semiconductor layer 31 after the trench T is formed corresponds to the n pillar region 3.

Then, as shown in FIG. 2(d), the second conductivity type semiconductor layer is epitaxially grown in the formed trench T to form the p pillar region 4.

Then, the source region 6, the contact region 7, the gate insulating film 8, the gate electrode 9, and the source electrode 11 are formed on the drift region. Then, a drain region 1 is formed in a region of the n-type semiconductor region 2 opposite to the drift region, and a drain electrode 10 is formed on the drain region 1, whereby the semiconductor device 100 shown in FIG. 1 is obtained.

Fig. 2 shows an example in which a trench is formed by the RIE method and the semiconductor layer is epitaxially grown in the trench. The present invention is not limited thereto, and the p-pillar region 4 having a dimension in the Z direction of the upper portion and a length in the Z direction lower than the lower portion may be formed by ion implantation. However, in order to facilitate the manufacturing and to reduce the unevenness of the impurity concentration in the p-pillar region 4, it is preferable to form a trench to form the p-pillar region 4.

Hereinafter, the action and effect of the present embodiment will be described.

First, the impurity amount of the second conductivity type of the portion 4a is set to be larger than the impurity amount of the first conductivity type of the portion 3a of the n-pillar region 3 in which the portion 4a is aligned in the Z direction. The electric field in the strong drift region.

Then, the electric field in the n-type semiconductor region 2 can be enhanced by the provision of the portion 4b in the n-type semiconductor region 2. At this time, the electric field intensity in the n-type semiconductor region 2 affects the electric field intensity in the drift region. Therefore, in addition to the above-described mass of the portion 4a being made larger than that of the portion 3a, a strong electric field is generated in the n-type semiconductor region 2 by the portion 4b provided in the n-type semiconductor region 2. As a result, the withstand voltage can be greatly improved.

On the other hand, the on-resistance can be suppressed by making the impurity amount of the second conductivity type of the portion 4b smaller than the impurity amount of the first conductivity type in the portion 2a of the buffer region in which the portion 4b is aligned in the Z direction. Increase. In other words, even when the portion 4b is provided in the n-type semiconductor region 2, the expansion of the depletion layer extending from the portion 4b in the Z direction and in the direction opposite to the Z direction can be suppressed, and the increase in the on-resistance can be suppressed.

Further, the electric field enhanced in the drift region and the n-type semiconductor region 2 has a lower impurity concentration of the first conductivity type of the n-type semiconductor region 2, so that the attenuation of the electric field in the n-type semiconductor region 2 can be suppressed, and the electric field can be extended to The lower portion of the n-type semiconductor region 2.

As described above, according to the present embodiment, the increase in the on-resistance can be suppressed, and the withstand voltage can be improved by enhancing the electric field in the drift region and the n-type semiconductor region 2.

Further, in order to further enhance the electric field in the n-type semiconductor region 2, it is preferable that the dimension of the portion 4b in the X direction is 4 μm or more.

In order to suppress an increase in the on-resistance in the semiconductor device and further increase the withstand voltage, it is preferable to satisfy the following two conditions.

The first condition is that the amount of impurities of the second conductivity type of the portion 4a is 1.1 times or less the mass of the first conductivity type of the portion 3a of the n-pillar region 3 in which the portion 4a is aligned in the Z direction.

The reason for this is that when the impurity amount of the second conductivity type of the portion 4a exceeds 1.1 times the impurity amount of the first conductivity type of the portion 3a, the impurity amount of the second conductivity type of the portion 4a and the first conductivity of the portion 3a The difference in the mass of the type becomes large, and it becomes difficult to improve the withstand voltage of the drift region.

In the second condition, the impurity amount of the second conductivity type of the portion 4b is set to be 0.9 or less times the impurity amount of the first conductivity type of the portion 2a of the n-type semiconductor region 2 in which the portion 4b is aligned in the Z direction.

This is because the on-resistance of the n-type semiconductor region 2 increases when the impurity amount of the second conductivity type of the portion 4b exceeds 0.9 times the impurity amount of the first conductivity type of the portion 2a.

Further, it is preferable that the dimension in the Z direction of the n-pillar region 3 is decreased in the X direction, and the dimension in the Z direction of the p-pillar region 4 is increased in the X direction. According to this configuration, more current can flow when the semiconductor device 100 is in the on state.

The reason is as follows.

When a voltage equal to or higher than a threshold value is applied to the gate electrode 9 and the semiconductor device 100 is turned on, a current flows between the drain electrode 10 and the source electrode 11. Accordingly, the voltage between the drain electrode 10 and the source electrode 11 increases. Further, due to the voltage between the drain electrode 10 and the source electrode 11, the depletion layer spreads from the pn junction between the n-type semiconductor region 2 and the n-pillar region 3 and the p-pillar region 4. The current path in the n-type semiconductor region 2 and the n-pillar region 3 is narrowed by the expansion of the depletion layer. At this time, as the depletion layer expands, the current path in the n-pillar region 3 becomes narrower, and the saturation current becomes smaller. The depletion layer is more likely to expand on the side of the drain electrode 10 than the side of the source electrode 11. In particular, in the present embodiment, since one of the p-pillar regions 4 is provided in the n-type semiconductor region 2 having a lower impurity concentration of the first conductivity type, the depletion layer in the n-type semiconductor region 2 is easily expanded.

However, as in the present embodiment, the size of the portion 2a in the Z direction can be increased by shortening the dimension of the portion 4b in the Z direction. As a result, the width of the current path in the n-type semiconductor region 2 when the semiconductor device 100 is in the ON state can be widened as compared with the case where the dimension in the Z direction of the portion 4a is equal to the dimension in the Z direction of the portion 4b. , can increase the saturation current.

Furthermore, the carrier density and size of each semiconductor region can be, for example, SCM. (Scanning Capacitance Microscopy, scanning electrostatic capacitance microscope) confirmed.

For example, by using the SCM to investigate the carrier distribution on the A-A' line shown in FIG. 1, it is possible to investigate the carrier density of the central portion of the portion 4a on the A-A' line and the Z direction of the portion 3a. The carrier density of the central portion, the dimension of the portion 4a in the Z direction, and the dimension of the portion 3a in the Z direction.

Similarly, for example, by using the SCM to investigate the carrier distribution on the B-B' line shown in FIG. 1, it is possible to investigate the carrier density of the central portion of the portion 4b on the B-B' line, and the portion 2a. The carrier density in the central portion of the Z direction, the dimension in the Z direction of the portion 4b, and the dimension in the Z direction of the portion 2a.

(Second embodiment)

A second embodiment of the present invention will be described with reference to Fig. 3 .

Fig. 3 is a perspective cross-sectional view showing a part of the semiconductor device 200 of the second embodiment.

In the following description of the embodiments, the same components and functions as those of the first embodiment will be omitted, and the differences from the first embodiment will be mainly described.

In the first embodiment, the size of the n-pillar region 3 in the Z direction and the dimension of the p-pillar region 4 in the Z direction are changed in the X direction, and the impurity amount of each region is changed in the X direction.

On the other hand, in the present embodiment, the impurity concentration of the n-pillar region 3 and the impurity concentration of the p-pillar region 4 are changed in the X direction, and the impurity amount of each region is changed in the X direction.

The dimension of the n-pillar region 3 in the Z direction is fixed in the X direction. That is, the dimension in the Z direction of the lower portion of the n pillar region 3 is equal to the dimension in the Z direction of the upper portion of the n pillar region 3.

Similarly, the dimension of the p-pillar region 4 in the Z direction is also fixed in the X direction. because Thus, the dimension in the Z direction of the portion 4a is equal to the dimension in the Z direction of the portion 4b.

The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the second conductivity type of the portion 4b.

The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the first conductivity type of the portion 3a. Further, the dimension of the portion 4a in the Z direction is equal to the dimension of the portion 3a in the Z direction. Therefore, the impurity amount of the second conductivity type of the portion 4a is larger than the impurity amount of the first conductivity type of the portion 3a of the n pillar region 3 in which the portion 4a is aligned in the Z direction.

The impurity concentration of the second conductivity type of the portion 4b is lower than the impurity concentration of the first conductivity type of the portion 2a. Further, the impurity amount of the second conductivity type of the portion 4b is smaller than the impurity amount of the first conductivity type of the portion 2a of the buffer region in which the portion 4b is aligned in the Z direction.

If the example shown in FIG. 3 is otherwise shown, the carrier type of the second conductivity type in which the portion 4a is located at the center of the Z direction is the first conductivity type of the portion where the portion 3a is located at the center of the Z direction. The carrier density is high. The dimension in the Z direction of the portion 4a is equal to the dimension in the Z direction of the portion 3a.

Further, the carrier density of the second conductivity type in the portion where the portion 4b is located at the center of the Z direction is lower than the carrier density of the first conductivity type in the portion where the portion 2a is located at the center of the Z direction. The dimension in the Z direction of the portion 4b is equal to the dimension in the Z direction of the portion 2a.

A-A' is a line passing through the center of the Z-direction of the n-pillar region 3. B-B' is a line passing through the center of the Z-direction of the p-pillar region 4.

The dimensions of the above-described portions in the Z direction may also include manufacturing variations.

According to the above configuration, in the semiconductor device, as in the first embodiment, the increase in the on-resistance can be suppressed and the withstand voltage can be improved.

The carrier density and the size of each semiconductor region can be confirmed by, for example, SCM (scanning electrostatic capacitance microscope) as in the first embodiment.

For example, with respect to the semiconductor device 200 shown in FIG. 3, by using the SCM to investigate the carrier distribution on the A-A' line and the carrier distribution on the B-B' line, it is possible to investigate the line division of each person. Carrier density and size of each semiconductor region.

(variation)

Next, a modification of the second embodiment will be described with reference to Fig. 4 .

Fig. 4 is a perspective cross-sectional view showing a part of a semiconductor device 250 according to a modification of the second embodiment.

In the present variation, the n-pillar region 3 includes a portion 3a and a portion 3b. The portion 3a is disposed on the X-direction side of the portion 3b. That is, the portion 3b is provided between the portion 3a and the n-type semiconductor region 2. The impurity concentration of the first conductivity type of the portion 3a is higher than the impurity concentration of the first conductivity type of the portion 3b.

The p-pillar region 4 includes a portion 4a, a portion 4b, and a portion 4c. The portion 4a and the portion 3a are juxtaposed in the Z direction. The portion 4c and the portion 3b are juxtaposed in the Z direction. The portion 4b is juxtaposed with the portion 2a of the n-type semiconductor region 2 in the Z direction. The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the second conductivity type of the portion 4c.

The impurity concentration of the second conductivity type of the portion 4a is higher than the impurity concentration of the first conductivity type of the portion 3a. Further, the dimension of the portion 4a in the Z direction is equal to the dimension of the portion 3a in the Z direction. Therefore, the impurity amount of the second conductivity type in the portion 4a is larger than the impurity amount of the first conductivity type in the portion 3a of the n pillar region 3 in which the portion 4a is juxtaposed in the Z direction.

The impurity concentration of the second conductivity type of the portion 4c is higher than the impurity concentration of the first conductivity type of the portion 3b. Further, the dimension in the Z direction of the portion 4c is equal to the dimension in the Z direction of the portion 3b. Therefore, the impurity amount of the second conductivity type in the portion 4c is larger than the impurity amount of the first conductivity type in the portion 3a of the n pillar region 3 in which the portion 4c is aligned in the Z direction. However, the difference between the impurity amount of the second conductivity type in the portion 4c and the impurity amount of the first conductivity type in the portion 3a is higher than the impurity amount of the second conductivity type in the portion 4a, and the first conductivity type in the portion 3a. The difference in the quality of the impurities is small.

On the other hand, the impurity amount of the second conductivity type in the portion 4b is smaller than the impurity amount of the first conductivity type in the portion 2a of the buffer region in which the portion 4b is aligned in the Z direction.

Also in the present modification, as in the first embodiment, the increase in the on-resistance can be suppressed for the semiconductor device, and the withstand voltage can be improved.

Further, the semiconductor device 200 may further have a portion in which the impurity concentrations in the n pillar region 3 are different from each other in the X direction. Similarly, the semiconductor device 200 may further have a portion in which the impurity concentrations in the p pillar region 4 are different from each other in the X direction.

Alternatively, the impurity concentration of the n-pillar region 3 may include the portions 3a and 3b in a continuous manner in the X direction. Similarly, the impurity concentration of the p-pillar region 4 may include the portions 4a, 4b, and 4c in a continuous manner in the X direction.

Each embodiment has been specifically described above.

However, the impurity concentration of the second conductivity type in the portion 4a and the size in the Z direction, the impurity concentration of the first conductivity type in the portion 3a, and the size in the Z direction may be the second conductivity type in the portion 4a. The mass is appropriately changed within a range in which the mass of the first conductivity type in the portion 3a is increased.

Similarly, the impurity concentration of the second conductivity type in the portion 4b and the size in the Z direction, the impurity concentration of the first conductivity type in the portion 2a, and the size in the Z direction may be the second conductivity type in the portion 4b. The amount of impurities is appropriately changed within a range in which the amount of impurities of the first conductivity type in the portion 2a is small.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention may be embodied in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. These embodiments and variations thereof are included in the scope and spirit of the invention, and are included in the scope of the invention described in the claims.

1‧‧‧Bungee area

2‧‧‧Semiconductor area

2a‧‧‧Parts

3‧‧‧n pillar area

Section 3a‧‧‧

4‧‧‧p pillar area

4a‧‧‧Parts

4b‧‧‧section

5‧‧‧p base region

6‧‧‧ source area

7‧‧‧Contact area

8‧‧‧Gate insulation film

9‧‧‧ gate electrode

10‧‧‧汲electrode

11‧‧‧Source electrode

100‧‧‧Semiconductor device

Claims (14)

A semiconductor device comprising: a first semiconductor region of a first conductivity type; and a plurality of second semiconductor regions selectively provided on the first semiconductor region and having a first conductivity type that is higher than the first semiconductor region The impurity concentration of the first conductivity type having a high impurity concentration extends in the first direction and is provided apart from each other in the second direction orthogonal to the first direction; and the plurality of third semiconductors of the second conductivity type a region extending in the first direction and including: a first portion disposed between the adjacent second semiconductor regions and having a first conductivity type of the first conductivity type included in the adjacent second semiconductor region a second impurity type of the second conductivity type; and a second portion provided in the first semiconductor region and having a first conductivity type included in the first semiconductor region adjacent to the second direction a second conductivity type fourth semiconductor region provided on the third semiconductor region; a fifth semiconductor region provided in the fourth semiconductor region; and a gate electrode ,its Spacer gate insulating film provided on said fourth semiconductor region. The semiconductor device according to claim 1, wherein the dimension of the first portion in the second direction is longer than the dimension of the second portion in the second direction. The semiconductor device according to claim 2, wherein the impurity concentration of the second conductivity type of the first portion is equal to the impurity concentration of the second conductivity type of the second portion. The semiconductor device according to claim 2, wherein the impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the second conductivity type of the second portion. The semiconductor device of claim 1, wherein the first part of the first part is in the second direction The size is equal to the dimension in the second direction of the second part described above. The semiconductor device according to claim 5, wherein the impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the second conductivity type of the second portion. The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type of the first portion is higher than the impurity concentration of the first conductivity type of the second semiconductor region. The semiconductor device according to claim 7, wherein the dimension of the first portion in the second direction is equal to the dimension of the second semiconductor region in the second direction. The semiconductor device according to claim 7, wherein the dimension of the first portion in the second direction is longer than the dimension of the second semiconductor region in the second direction. The semiconductor device according to claim 1, wherein the dimension of the second portion in the third direction orthogonal to the first direction and the second direction is 4 μm or more. The semiconductor device according to claim 1, wherein the impurity amount of the second conductivity type of the first portion is 1.1 times or less the impurity amount of the first conductivity type included in the adjacent second semiconductor region; and the second portion The impurity amount of the second conductivity type is 0.9 times or less the impurity amount of the first conductivity type included in the adjacent first semiconductor region. The semiconductor device according to claim 1, further comprising: a sixth semiconductor region of the second conductivity type provided on the fourth semiconductor region, wherein an impurity concentration of the second conductivity type of the sixth semiconductor region is higher than that of the fourth semiconductor region The second conductivity type has a high impurity concentration. A semiconductor device comprising: a first semiconductor region of a first conductivity type; and a plurality of second semiconductor regions selectively provided on the first semiconductor region and extending in a first direction, and The first direction is orthogonal to each other in the second direction; the third semiconductor region of the plurality of second conductivity types is equal to the first direction extension The first portion is disposed between the adjacent second semiconductor regions, and has a second conductivity type carrier density and a center of the second semiconductor region in the second portion in the second direction The first conductivity type carrier contained in the portion has the same density and has a size longer than the size of the second semiconductor region; and the second portion is provided in the first semiconductor region in the second direction. The carrier density of the second conductivity type included in the central portion is higher than the carrier density of the first conductivity type included in the central portion of the first semiconductor region, and has a size shorter than the size of the first semiconductor region; a second conductivity type fourth semiconductor region provided on the third semiconductor region; a fifth semiconductor region provided in the fourth semiconductor region; and a gate electrode provided on the gate insulating film On the fourth semiconductor region. A semiconductor device comprising: a first semiconductor region of a first conductivity type; and a plurality of second semiconductor regions selectively provided on the first semiconductor region and extending in a first direction, and The first direction is orthogonal to each other in the second direction; the third semiconductor region of the plurality of second conductivity types is extended in the first direction, and includes a first portion that is disposed adjacent to the second portion Between the semiconductor regions, in the second direction, the carrier density of the second conductivity type included in the central portion is higher than the carrier density of the first conductivity type included in the central portion of the second semiconductor region, and has a The second semiconductor region has a size equal to the size; and the second portion is disposed in the first semiconductor region, and the carrier density of the second conductivity type included in the central portion is higher than the first one in the second direction The carrier of the first conductivity type contained in the central portion of the semiconductor region has a low density and has the first a size of the semiconductor region having the same size; a fourth semiconductor region of the second conductivity type provided on the third semiconductor region; a fifth semiconductor region provided in the fourth semiconductor region; and a gate electrode The gate insulating film is provided on the fourth semiconductor region.