CN205376537U - Improve super knot MOS device of backward recovery characteristic and snowslide ability - Google Patents
Improve super knot MOS device of backward recovery characteristic and snowslide ability Download PDFInfo
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- CN205376537U CN205376537U CN201620030764.XU CN201620030764U CN205376537U CN 205376537 U CN205376537 U CN 205376537U CN 201620030764 U CN201620030764 U CN 201620030764U CN 205376537 U CN205376537 U CN 205376537U
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Abstract
The utility model relates to an improve super knot MOS device of backward recovery characteristic and snowslide ability, it includes device region and terminal area, by conductivity type post district and the 2nd conductivity type post district super knot structure that NULL constituted to be present in in device region and the terminal area. Be provided with a plurality of the 2nd non -conterminous conductivity type tagmas in the device region, be provided with the 2nd conductivity type protection zone at the terminal area, it is direct not adjacent between arbitrary the 2nd a conductivity type tagma at the department of device region intra -area and the conductivity type drift region, kept apart by the 2nd conductivity type device post, it is direct not adjacent between arbitrary the 2nd a conductivity type protection zone at the department of terminal area and the conductivity type drift region, kept apart by the 2nd conductivity type terminal pole. The utility model discloses under the prerequisite that does not increase the technology degree of difficulty and manufacturing cost, device backward recovery characteristic and snowslide ability have been improved.
Description
Technical field
This utility model relates to a kind of superjunction MOS device, especially a kind of superjunction MOS device improving reverse recovery characteristic and avalanche capacity, belongs to the technical field of semiconductor MOS device.
Background technology
In mesohigh power semiconductor field, super-junction structure (SuperJunction) is widely adopted.In the drift region of superjunction merit MOS, multiple P-N posts that N post and P post are alternately provided adjacent to are to forming super-junction structure.When the MOS device with super-junction structure is ended, N post and P post in super-junction structure are depleted respectively, depletion layer extends from the P-N junction interface of each N post with P intercolumniation, owing to the impurity level in the impurity level in N post and P post is equal, therefore depletion layer extends and completely depleted N post and P post, thus supports is pressure.Contrast conventional power VDMOS device, superjunction MOS device can obtain the pressure tradeoff with conducting resistance of more excellent device.
But, the reverse recovery characteristic that one shortcoming of common superjunction devices is exactly its parasitic body diode is poor, the P-N column structure of super-junction structure is used to obtain charge balance, this brings two consequences to the parasitic body diode of superjunction devices: one is the area contrast tradition power MOS without super-junction structure of P-N junction, as big many in plane bilateral diffusion MOS (PlanarVDMOS), cause when superjunction MOS device is applied to the situation of some topological circuits of reverse fly-wheel diode, such as half-bridge (such as HID half-bridge or LLC) and full-bridge (such as ZVS bridge), parasitic body diode is after switch, bigger carrier injects and QRR Qrr and Reverse recovery peak point current Irrm is raised；Two is rapidly depleting due to P-N column structure, and the shutoff dv/dt of MOS device can be made to increase, and Reverse recovery hardness is high.These shortcomings so that common superjunction devices is damaged owing to higher Reverse recovery peak point current Irrm and dv/dt is very easy when hard switching is applied.
For solving superjunction MOS device body diode reverse recovery characteristics problem, have three kinds of modes to be suggested or adopt at present: 1), use electron irradiation manufacturing defect in drift layer, reduce carrier lifetime in reversely restoring process, reduce QRR.But this method can bring element leakage to increase, and the defect that irradiation produces can be recovered after high temperature and long-term work, affects device reliability；2), using heavy metal doping, form complex centre, reduce carrier lifetime in reversely restoring process in device drift layer, this mode manufacturing process is special, and process costs is high, and element leakage characteristic also can be deteriorated；3), in superjunction MOS device integrated schottky diode, to improve device body diode reverse recovery characteristic, this mode except manufacturing process special except, element leakage is uncontrollable especially, at present almost without be employed with in actual product.
The file that publication number is CN203456470U discloses a kind of MOS device increasing the first cushion and the second cushion, although improving super node MOSFET body diode reverse recovery characteristics by increasing the first cushion and the second cushion, but realize owing to this first cushion and the second cushion need to increase extra processing step, the process costs of device is greatly improved.
Meanwhile, superjunction MOS is little due to chip area, and the half that the chip area of same current specification is only common VDMOS is even less, and the avalanche capability of chip is relatively weak, in the application with inductive load, it is easy to cause component failure.
As can be seen here, one can pass through optimised devices structure, improves superjunction MOS body diode reverse recovery characteristics and avalanche capacity, and its manufacturing process is very important with the compatible novel superjunction MOS device of existing superjunction MOS manufacturing process.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, a kind of superjunction MOS device improving reverse recovery characteristic and avalanche capacity is provided, its compact conformation, technique is simple, mutually compatible with existing superjunction MOS manufacturing process, is effectively improved reverse recovery characteristic, improve the avalanche capacity of device, it is suitable for batch production, improves subject range, safe and reliable.
According to the technical scheme that this utility model provides, the described superjunction MOS device improving reverse recovery characteristic and avalanche capacity, in the top plan view of described MOS device, including the device area being positioned on semiconductor substrate and terminal area, described device area is positioned at the center of semiconductor substrate, and terminal area is positioned at the outer ring of described device area and around surrounding described device area；On the cross section of described MOS device, described semiconductor substrate includes the first conduction type drift region above and the first conductivity type substrate being positioned below, described first conductivity type substrate adjoins the first conduction type drift region, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate forms the second interarea of semiconductor substrate；
Some first conductivity type columns and the second conductivity type columns are set in the first conduction type drift region, first conductivity type columns, the second conductivity type columns extend vertically from the first interarea of semiconductor substrate to the direction pointing to the second interarea, and the first conductivity type columns and the second conductivity type columns are arranged alternately distribution in the first conduction type drift region；Described first conductivity type columns includes the first conduction type device post being positioned at device area and the first conduction type terminal pillar being positioned at terminal area, and the second conductivity type columns includes the second conduction type device post being positioned at device area and the second conduction type terminal pillar being positioned at terminal area；
Top in second conduction type device post is provided with the second conductivity type body region, and the second conductivity type body region is positioned at the second conduction type device post, and the second conductivity type body region is isolated by the second conduction type device post and the first conduction type drift region；The doping content of the second conduction type device post is lower than the doping content of the second conductivity type body region；
Being provided with the second conduction type protection zone in second conduction type terminal pillar, described second conduction type protection zone is positioned at the second conduction type terminal pillar, and the second conduction type protection zone is isolated by the second conduction type terminal pillar and the first conduction type drift region；The doping content of the second conduction type terminal pillar is lower than the doping content of the second conduction type protection zone.
On the cross section of described MOS device, the device area of MOS device adopts plane MOSFET structure, described plane MOSFET structure includes the first conduction type active area being positioned at the second conductivity type body region, first interarea of device area is provided with device gate electrode and for surrounding the device isolation dielectric layer covering described device gate electrode, described device isolation dielectric layer is deposited with source metal, described source metal and the second conductivity type body region and the first equal Ohmic contact of conduction type active area being positioned at described second conductivity type body region, source metal is by device isolation dielectric layer and the isolation of device gate electrode insulation.
On the cross section of described MOS device, first interarea of terminal area is coated with terminating insulation dielectric layer, described terminating insulation dielectric layer is provided with the gate metal layer for forming grid, described gate metal layer and the grid lead body Ohmic contact in terminating insulation dielectric layer, described grid lead body electrically connects with device gate electrode.
Second interarea of described semiconductor substrate is provided with drain metal, described drain metal and the first conductivity type substrate Ohmic contact.
In both described " the first conduction type " and " the second conduction type ", for N-type power MOSFET device, the first conduction type refers to N-type, and the second conduction type is P type；For P type power MOSFET device, the type of the first conduction type and the second conduction type indication and N-type semiconductor device contrast.
Advantage of the present utility model:
1, when being operated in body diode freewheeling mode, the second conduction type carrier flows into the first conduction type drift region from the second conductivity type body region and the second conduction type protection zone respectively through the second conduction type device post, the second conduction type terminal pillar.First conduction type carrier flows into the second conductivity type body region, the second conduction type protection zone from the first conduction type drift region respectively through the second conduction type device post, the second conduction type terminal pillar.Owing to the doping content of the second conduction type device post is lower than the doping content of the second conductivity type body region; the doping content of the second conduction type terminal pillar is lower than the doping content of the second conduction type protection zone; therefore; can effectively reduce the second conduction type carrier current ratio in afterflow process, reduce the storage in the first conduction type drift region of the second conduction type carrier.When device enters reversely restoring process, QRR and reverse recovery current can substantially reduce, and device body diode reverse recovery speed and softness also can improve accordingly.Wherein, the second conduction type carrier is hole or electronics, and the first conduction type carrier is electronics or hole.
2, owing to the second conductivity type body region, the second conduction type protection zone are surrounded by the second conduction type device post, the second conduction type terminal pillar respectively, the junction curvature between the second conduction type device post, the second conduction type terminal pillar and the first conduction type drift region is relatively small.In device avalanche process, current convergence can be reduced, reduce the size of current below the first conduction type active area, reduce the possibility that parasitic triode is opened, be more conducive to improve the avalanche capacity of device.
3 is mutually compatible with semiconductor power device manufacturing process general at present, and manufacturing cost and technology difficulty are not significantly increased, and is suitable for batch production.
Accompanying drawing explanation
Fig. 1 is the partial top view of this utility model superjunction MOS device.
Fig. 2 be in Fig. 1 A-A ' to sectional view.
Fig. 3 be in Fig. 1 B-B ' to sectional view.
Fig. 4 ~ Fig. 9 is that this utility model is embodied as step sectional view for N-channel planar gate superjunction MOS device, wherein:
Fig. 4 is the sectional view of this utility model semiconductor substrate.
Fig. 5 is the sectional view after this utility model obtains hard mask layer.
Fig. 6 is the sectional view after this utility model obtains hard mask window.
Fig. 7 is the sectional view after this utility model obtains device trenches, terminal trenches.
Fig. 8 is that this utility model is to the sectional view after the first interarea planarization of semiconductor substrate.
Fig. 9 is the sectional view after this utility model obtains P+ body district and P+ protection zone.
Figure 10 is the sectional view after this utility model obtains device architecture and terminal structure.
Description of reference numerals: 01-N type drift region, 02-N+ substrate, 03-drain metal, 04-hard mask layer, 11a-P type terminal pillar, 11b-N type terminal pillar, the hard mask window of 11c-terminal, 11d-terminal trenches, 12-P+ protection zone, 13-terminating insulation dielectric layer, 14-grid lead body, 15-gate metal layer, 21a-P type device post, 21b-N type device post, the hard mask window of 21c-device, 21d-device trenches, 22-P+ body district, 23-device isolation dielectric layer, 24-device gate electrode, 25-source metal, 26-N+ active area, 101-the first interarea, 102-the second interarea, 111-terminal area and 112-device area.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the utility model is described in further detail.
As shown in Figure 1, Figure 2 and Figure 3: in order to be effectively improved reverse recovery characteristic, improve the avalanche capacity of device, for N-type super-junction MOSFET device, this utility model is in the top plan view of described MOS device, including the device area 112 being positioned on semiconductor substrate and terminal area 111, described device area 112 is positioned at the center of semiconductor substrate, and terminal area 111 is positioned at the outer ring of described device area 112 and around surrounding described device area 112；On the cross section of described MOS device, described semiconductor substrate includes N-type drift region 01 above and the N+ substrate 02 being positioned below, described N+ type substrate 02 adjoins N-type drift region 01, the upper surface of N-type drift region 01 forms the second interarea 102 of the lower surface formation semiconductor substrate of the first interarea 101, N+ substrate 02 of semiconductor substrate；
Arranging some N posts and P post in N-type drift region 01, N post, P post extend vertically from the first interarea 101 of semiconductor substrate to the direction pointing to the second interarea 102, and N post and P post are arranged alternately distribution in N-type drift region 01；N-type device post 11b that described N post includes being positioned at device area 112 and N-type terminal pillar 11b, the P post being positioned at terminal area 111 include being positioned at the P-type device post 21a of device area 112 and are positioned at the P type terminal pillar 11a of terminal area 111；
Top in P-type device post 21a is provided with body district of P+ body district 22, P+ 22, and to be positioned at P-type device post 21a, QieP+Ti district 22 isolated with N-type drift region 01 by P-type device post 21a；The doping content of P-type device post 21a is lower than the doping content in P+ body district 22；
Being provided with P+ protection zone 12 in P type terminal pillar 11a, described P+ protection zone 12 is positioned at P type terminal pillar 11a, and P+ protection zone 12 is isolated with N-type drift region 01 by P type terminal pillar 11a；The doping content of P type terminal pillar 11a is lower than the doping content of P+ protection zone 12.
Specifically; the material of semiconductor substrate can be the conventional semi-conducting materials such as silicon; the conduction type of semiconductor substrate is N-type; the doping content of N+ substrate 02 is more than the doping content of N-type drift region 01; the device architecture of superjunction MOS device can be formed by device area 112; terminal area 111 for forming the protection structure to device area 113 protection, device area 112, terminal area 111 function be known by those skilled in the art, repeat no more herein.
What described super-junction structure included in N-type drift region 01 some alternates the N post of distribution, P post, N post, P post extend vertically downward from the first interarea 101 of semiconductor substrate, N post, the P post degree of depth in N-type drift region 01 are not more than the thickness of N-type drift region 01, usually, N post, the P post degree of depth in N-type drift region 01 are less than the thickness of N-type drift region 01, super-junction structure is distributed in device area 112 and terminal area 111, super-junction structure distribution form in N-type drift region 01, known by those skilled in the art, repeats no more herein.In this utility model embodiment, there is in terminal area 111 N-type terminal pillar 11b and the P type terminal pillar 11a alternateing distribution, there is in device area 112 alternatively distributed N-type device post 21b and P type terminal pillar 21a, in terminal area 111, the degree of depth of N-type terminal pillar 11b, P type terminal pillar 11a is consistent, N-type device post 21b in device area 112, P-type device post 21a the degree of depth consistent, and N-type terminal pillar 11b, P type terminal pillar 11a, N-type device post 21b and P-type device post 21a in N-type drift region 01 also in N post, the distribution form that alternates of P post.In the specific implementation, N-type terminal pillar 11b and N-type device post 21b can have identical width and the degree of depth, and the degree of depth of N-type terminal pillar 11b, width can also be different from N-type device post 21b, specifically can carry out selection as required and determine, repeat no more herein.
P+ body district 22 is positioned at the degree of depth in P-type device post 21a, P+ body district 22, width no more than P-type device post 21a, it is thus possible to it is isolated with N-type drift region 01 to make P+ body district 22 can pass through P-type device post 21a.P+ protection zone 12 is positioned at the degree of depth of P type terminal pillar 11a, P+ protection zone 12, width is not more than P type terminal pillar 11a, it is thus possible to it is isolated with N-type drift region 01 to make P+ protection zone 12 can pass through P type terminal pillar 11a.P+ protection zone 12 can be only located in the P type terminal pillar 11a in adjacent devices region 112, it is also possible to is respectively provided with P+ protection zone 12 in all of P type terminal pillar 11a.
Further, on the cross section of described MOS device, the device area 112 of MOS device adopts plane MOSFET structure, described plane MOSFET structure includes the N+ active area 26 being positioned at P+ body district 22, first interarea 101 of device area 112 is provided with device gate electrode 24 and for surrounding the device isolation dielectric layer 23 covering described device gate electrode 24, described device isolation dielectric layer 23 is deposited with source metal 25, described source metal 25 and P+ body district 22 and the equal Ohmic contact of N+ active area 26 being positioned at described P+ body district 22, source metal 25 is dielectrically separated from by device isolation dielectric layer 23 and device gate electrode 24.
In this utility model embodiment, for plane MOS device, namely the structure of device area 112 adopts plane MOS cellular, on the cross section of MOS device, plane MOS cellular includes the N+ active area 26 being positioned at P+ body district 22, and described N+ active area 26 is symmetrically distributed in P+ body district 22.Device gate electrode 24 can adopt conductive polycrystalline silicon, device gate electrode 24 to be positioned at above the first interarea 101, and device gate electrode 24 is isolated absolutely by device isolation dielectric layer 23 and the first interarea 101, and device gate electrode 24 is wrapped in device isolation dielectric layer 23.Device gate electrode 24 is positioned at above N-type device post 21b, the width of device gate electrode 24 is more than N-type device post 21b, the two ends of device gate electrode 24 extend respectively to the top of corresponding adjacent N+ active area 26 in P-type device post 21a, and device gate electrode 24 only overlaps mutually with the N+ active area 26 of part, it is thus possible to the source metal 25 above making can with N+ active area 26 and P+ body district 22 Ohmic contact after traverse device isolation dielectric layer 23.When being embodied as, above device area 112 and the device gate electrode 24 in adjacent terminals region 111 also extend in terminal area 111, now, one end of device gate electrode 24 and the N+ active area 26 in adjacent terminals region 111 in P-type device post 21a, the other end of device gate electrode 24 covers the subregion of P+ protection zone 12 in the P type terminal pillar 11a in adjacent devices region 112 in terminal area 111, device gate electrode 24 is dielectrically separated from also by the first interarea 101 of device isolation gate dielectric layer 23 with semiconductor substrate, namely device gate electrode 24 is by device isolation gate dielectric layer 23 and P+ protection zone 12, N-type drift region 01, P-type device post 21a, P type terminal pillar 11a and N+ active area 23 are isolated.
On the cross section of described MOS device, first interarea 101 of terminal area 111 is coated with terminating insulation dielectric layer 13, described terminating insulation dielectric layer 13 is provided with the gate metal layer 15 for forming grid, described gate metal layer 15 and grid lead body 14 Ohmic contact in terminating insulation dielectric layer 13, described grid lead body 14 electrically connects with device gate electrode 24.
In this utility model embodiment, the thickness of terminating insulation dielectric layer 13 is more than device isolation dielectric layer 23, terminating insulation dielectric layer 13 covers on the first interarea 101 of semiconductor substrate, and namely terminating insulation dielectric layer 13 covers the upper end of N-type terminal pillar 11b in terminal area 111, N-type device post 11a.In order to the grid of MOS device, it is necessary to being drawn by device gate electrode 24, gate metal layer 15 is supported on terminating insulation dielectric layer 13, and with grid lead body 14 Ohmic contact in terminating insulation dielectric layer 13.Usually, arranging terminal contact hole in terminating insulation dielectric layer 13, gate metal layer 15 is by terminal contact hole and grid lead body 14 Ohmic contact.Owing to grid lead body 14 electrically connects with device gate electrode 24, it is thus possible to form gate terminal by gate metal layer 15 after being drawn.
Second interarea 102 of described semiconductor substrate is provided with drain metal 03, described drain metal 03 and N+ substrate 02 Ohmic contact.In this utility model embodiment, the cellular parallel connection of multiple MOS device can be formed entirety by source metal 25, namely the source terminal of MOS device can be formed by source metal, the gate terminal of MOS device can be formed by the cooperation of device gate electrode 24, grid lead body 14 and gate metal layer 15, the drain electrode end of device can be formed by drain metal 03.Source metal 25, gate metal layer 15 can be same process layer.
As shown in Fig. 4 ~ Figure 10, the above-mentioned superjunction MOS device improving reverse recovery characteristic and avalanche capacity can be prepared by following processing step, and specifically, the manufacture method of described superjunction MOS device comprises the steps:
A, provide there is the semiconductor substrate of two opposing main faces, two opposing main faces include the first interarea 101 and second interarea 102 corresponding with described first interarea 101, include N-type drift region 01 and be positioned at the N+ substrate 02 below described N-type drift region 01 between the first interarea 101 and the second interarea 102；
As shown in Figure 4, semiconductor substrate is the semi-conducting material with N conduction type, and the material of semiconductor substrate can include silicon, naturally it is also possible to for other conventional semi-conducting material.N-type drift region 01 is positioned at the top of semiconductor substrate, N-type substrate 02 is positioned at the bottom of semiconductor substrate, N-type drift region 01 adjoins N-type substrate 02, the upper surface of N-type drift region 01 forms the first interarea 101, the lower surface of N-type substrate 02 forms the second interarea 102, usually, the impurity concentration of N-type substrate 02 is much larger than the impurity concentration of N-type drift region 01.
B, on the first interarea 101 of above-mentioned semiconductor substrate, it is deposited with hard mask layer 04, and optionally shelters and etch described hard mask layer 04, to obtain the hard mask window of some through hard mask layers 04；
As shown in Figure 5, described hard mask layer is LPTEOS, thermal oxide silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds the materials such as silicon nitride, the technological means conventional by the art can obtain hard mask layer 04, and the process that described hard mask layer 04 is optionally sheltered and etched is also known by the art.After hard mask layer 04 is etched, described hard mask window includes the terminal hard mask window 11c being positioned at the terminal area 111 and hard mask window 21c of device being positioned at device area 112, specifically as shown in Figure 6.Corresponding first interarea 101 can be made exposed by terminal hard mask window 11c, device hard mask window 21c.Terminal hard mask window 11c, device hard mask window 21c can have identical or different width.
C, utilize above-mentioned hard mask window that the first interarea 101 of semiconductor substrate is performed etching, to obtain some grooves in N-type drift region 01, described groove extends vertically downward in N-type drift region 01 from the first interarea 101 of semiconductor substrate, and groove includes the device trenches 21d being positioned at the device area 112 and terminal trenches 11d being positioned at terminal area 111；
As shown in Figure 7, utilize anisotropic etching, groove can be obtained in N-type drift region 01, wherein, terminal trenches 11d is obtained in the N-type drift region 01 corresponding with terminal hard mask window 11c, device trenches 21d is obtained in the N-type drift region 01 corresponding with device hard mask window 21c, terminal trenches 11d, device trenches 21d extends vertically downward from the first interarea 101, terminal trenches 11d, the degree of depth of device trenches 21d is less than the thickness of N-type drift region 01, terminal trenches 11d, the corresponding degree of depth of device trenches 21d, width can be similar and different, specifically by the above-mentioned hard mask window 11c of terminal, the width etc. of the hard mask window 21c of device is determined, it is specially known by those skilled in the art, repeat no more herein.
D, on the first interarea 101 of above-mentioned semiconductor substrate deposit P type epitaxial material, described P type epitaxial material is filled in device trenches 21d and terminal trenches 11d, first interarea 101 of described semiconductor substrate is planarized, to remove hard mask layer 04, obtain being positioned at the P-type device post 21a of device area 112 and being positioned at the P type terminal pillar 11a of terminal area 111；
As shown in Figure 8, when using epitaxial deposition process growing P-type epitaxial layer, P type epitaxial material can deposit at device trenches 21d, terminal trenches 11d sidewall, until device trenches 21d, terminal trenches 11d are filled.Use flatening process such as CMP etc. that semi-conducting material the first first type surface 101 is planarized, and remove hard mask 04.The only P type epitaxial layer in retaining means groove 21d, terminal trenches 11d, forms P-type device post 21a and P type terminal pillar 11a；The corresponding adjacent N-type drift layer 01 between P post region forms N-type device post 21b, N-type terminal pillar 11b.
E, on the first interarea 101 of above-mentioned semiconductor substrate, be selectively implanted p type impurity ion knot, with in P-type device post 21a formed P+ body district 22, in P type terminal pillar 11a formed P+ protection zone 12；
As it is shown in figure 9, implanting p-type foreign ion knot formed P+ body district 22, P+ protection zone 12 process known by those skilled in the art, repeat no more herein.P+ body district 22 is positioned at P-type device post 21a, P+ protection zone 12 and is positioned at P type terminal pillar 11a.
F, by conventional semiconductor process, form required device architecture at device area 112, and form required terminal structure in described terminal area 111.
As shown in Figure 10, device area 112 and the terminal area 111 of MOS device is formed by conventional semiconductor process.Tool includes the terminating insulation dielectric layer 13 of terminal area 111, the grid lead body 14 also serving as field plate and gate metal layer 15；The device isolation dielectric layer 23 of device area 112 and device gate electrode 24, the N+ active area 26 surrounded by described device isolation dielectric layer 23, source metal 25 routine MOS Facad structure such as grade.And on the second first type surface 102 of semiconductor substrate, form the drain metal 03 with N+ type substrate 02 Ohmic contact.Described terminating insulation dielectric layer 13, device isolation dielectric layer 23 can be silica glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG)；Described metal level can be aluminum, copper or tungsten etc..
When being embodied as, device area 111 adopts planar gate MOS structure cell, manufactures device cellular process and includes the techniques such as the injection of routine, diffusion, photoetching, etching.In the specific implementation, the manufacture method of described planar gate MOS structure is referred to manufacture method disclosed in ZL01807673.4.
In above-mentioned manufacture method, P+ body district 22 and P+ type protection zone 12 can concurrently form, it is also possible to formed respectively in forming conventional MOS structure process, be specially known by those skilled in the art, repeat no more herein.
To conventional super-junction MOSFET device, when being operated in body diode freewheeling mode, electric current flows into drain electrode end from source terminal, and namely electric current flows simultaneously into N-type drift region 01 from P+ body district 22 and P-type device post 21a, and hole can form carrier storage in N-type drift region 01.When device body diode reverse recovery, device drain terminal voltage raises, super-junction structure in N-type drift region 01 exhausts rapidly, the hole being stored in N-type drift region 01 is swept out, forming reverse recovery current, the size of the hole total amount being stored in N-type drift region 01 determines the size of QRR and reverse recovery current.Device can be impacted by excessive reverse recovery current and QRR, affects device reliability.
In this utility model embodiment, when device is operated in body diode freewheeling mode, hole flows into N-type drift region 01 from P+ body district 22 and P+ protection zone 12 through P-type device post 21a, P type terminal pillar 11a.Electronics flows into P+ body district 22, P+ protection zone 12 from N-type drift region 01 through P-type device post 21a, P type terminal pillar 11a.Owing to the doping content of P-type device post 21a is lower than the doping content in P+ body district 22; the doping content of P type terminal pillar 11a is lower than the doping content of P+ protection zone 12; therefore, it can effectively reduce hole current ratio in afterflow process, reduce hole storage in N-type drift region 01.When device enters reversely restoring process, QRR and reverse recovery current can substantially reduce, and device body diode reverse recovery speed and softness also can improve accordingly.
In this utility model embodiment, owing to P+ body district 22, P+ protection zone 12 are surrounded by P-type device post 21a, P type terminal pillar 11a respectively, the junction curvature between P-type device post 21a, P type terminal pillar 11a and N-type drift region 01 is relatively small.In device avalanche process, current convergence can be reduced, reduce the size of current below N+ active area 26, reduce the possibility that parasitic NPN audion is opened, be more conducive to improve the avalanche capacity of device.
Additionally, the manufacture method in this invention is mutually compatible with semiconductor power device manufacturing process general at present, manufacturing cost and technology difficulty are not significantly increased, and are suitable for batch production.
Above-described embodiment simply for design of the present utility model and feature are described, does not limit protection domain of the present utility model with this.Should be understood that every equivalence done according to this utility model spirit changes all within this utility model protection domain.
Claims (4)
1. the superjunction MOS device improving reverse recovery characteristic and avalanche capacity, in the top plan view of described MOS device, including the device area being positioned on semiconductor substrate and terminal area, described device area is positioned at the center of semiconductor substrate, and terminal area is positioned at the outer ring of described device area and around surrounding described device area；On the cross section of described MOS device, described semiconductor substrate includes the first conduction type drift region above and the first conductivity type substrate being positioned below, described first conductivity type substrate adjoins the first conduction type drift region, the upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate forms the second interarea of semiconductor substrate；
Some first conductivity type columns and the second conductivity type columns are set in the first conduction type drift region, first conductivity type columns, the second conductivity type columns extend vertically from the first interarea of semiconductor substrate to the direction pointing to the second interarea, and the first conductivity type columns and the second conductivity type columns are arranged alternately distribution in the first conduction type drift region；Described first conductivity type columns includes the first conduction type device post being positioned at device area and the first conduction type terminal pillar being positioned at terminal area, and the second conductivity type columns includes the second conduction type device post being positioned at device area and the second conduction type terminal pillar being positioned at terminal area；It is characterized in that:
Top in second conduction type device post is provided with the second conductivity type body region, and the second conductivity type body region is positioned at the second conduction type device post, and the second conductivity type body region is isolated by the second conduction type device post and the first conduction type drift region；The doping content of the second conduction type device post is lower than the doping content of the second conductivity type body region；
Being provided with the second conduction type protection zone in second conduction type terminal pillar, described second conduction type protection zone is positioned at the second conduction type terminal pillar, and the second conduction type protection zone is isolated by the second conduction type terminal pillar and the first conduction type drift region；The doping content of the second conduction type terminal pillar is lower than the doping content of the second conduction type protection zone.
2. the superjunction MOS device improving reverse recovery characteristic and avalanche capacity according to claim 1, it is characterized in that: on the cross section of described MOS device, the device area of MOS device adopts plane MOSFET structure, described plane MOSFET structure includes the first conduction type active area being positioned at the second conductivity type body region, first interarea of device area is provided with device gate electrode and for surrounding the device isolation dielectric layer covering described device gate electrode, described device isolation dielectric layer is deposited with source metal, described source metal and the second conductivity type body region and the first equal Ohmic contact of conduction type active area being positioned at described second conductivity type body region, source metal is by device isolation dielectric layer and the isolation of device gate electrode insulation.
3. the superjunction MOS device improving reverse recovery characteristic and avalanche capacity according to claim 2, it is characterized in that: on the cross section of described MOS device, first interarea of terminal area is coated with terminating insulation dielectric layer, described terminating insulation dielectric layer is provided with the gate metal layer for forming grid, described gate metal layer and the grid lead body Ohmic contact in terminating insulation dielectric layer, described grid lead body electrically connects with device gate electrode.
4. the superjunction MOS device improving reverse recovery characteristic and avalanche capacity according to claim 1, is characterized in that: be provided with drain metal, described drain metal and the first conductivity type substrate Ohmic contact on the second interarea of described semiconductor substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620030764.XU CN205376537U (en) | 2016-01-13 | 2016-01-13 | Improve super knot MOS device of backward recovery characteristic and snowslide ability |
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| CN201620030764.XU CN205376537U (en) | 2016-01-13 | 2016-01-13 | Improve super knot MOS device of backward recovery characteristic and snowslide ability |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448997A (en) * | 2016-01-13 | 2016-03-30 | 无锡新洁能股份有限公司 | Super-junction MOS device for improving reverse recovery feature and avalanche capability, and manufacturing method thereof |
| CN107611167A (en) * | 2017-08-21 | 2018-01-19 | 无锡新洁能股份有限公司 | A kind of super-junction semiconductor device and its manufacture method with multiple concentration centers |
-
2016
- 2016-01-13 CN CN201620030764.XU patent/CN205376537U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448997A (en) * | 2016-01-13 | 2016-03-30 | 无锡新洁能股份有限公司 | Super-junction MOS device for improving reverse recovery feature and avalanche capability, and manufacturing method thereof |
| CN105448997B (en) * | 2016-01-13 | 2019-02-15 | 无锡新洁能股份有限公司 | Improve the superjunction MOS device and its manufacturing method of reverse recovery characteristic and avalanche capacity |
| CN107611167A (en) * | 2017-08-21 | 2018-01-19 | 无锡新洁能股份有限公司 | A kind of super-junction semiconductor device and its manufacture method with multiple concentration centers |
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