TW201101497A - Nanotube semiconductor devices and fabrication method thereof - Google Patents

Abstract

Nanotube semiconductor devices and fabrication method thereof, forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate.A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Description

201101497 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a nanochannel vertical channel metal oxide tantalum field effect transistor semiconductor device, in particular, a vertical channel for preparing a nanotube via a sidewall epitaxial layer The process of metal oxide tantalum field effect device. Furthermore, the present invention relates to an edge termination structure in a charge balancing power device. [Prior Art] [0002] Metal oxide tantalum field effect device is formed by various lateral and vertical structures. Although the lateral metal oxide tantalum field effect device has a fast switching speed, it is not as dense as a vertical metal oxide tantalum field effect transistor. Vertical metal oxide tantalum field effect devices can be used to fabricate high density arrays of electromorphs, but typical vertical metal oxide tantalum field transistors have large gate-drain capacitance (Cgd) and drain-source capacitance (Cds). Therefore, the vertical metal oxide tantalum field effect device has a lower turn-to-turn speed, and the thumb-capacitance (Cgd) of the thumb-structured transistor is lower, but due to the overlap of the gate oxide and the N-drift region. Self-calibration characteristics, the mask gate structure of the transistor device increases the variation range of the drain-source "on" impedance (Rds〇n). In addition, the polysilicon germanium electrode, the polysilicon inter-layer dielectric (IpD), and the channel etching (sidewall angle) unit step process make the processing process of the mask gate structure transistor complicated and expensive. Moreover, the increase in output capacitor and mask gate polysilicon impedance reduces the switching speed of the mask gate structure transistor. U.S. Patent No. 5,981,996, issued to U.S. Pat. On the side wall. The N-type drain drift region formed by ion implantation and diffusion has the form number A0101, page 4 / page 123 d 201101497 / Chen degree gradient, that is, the doping concentration is not uniformly distributed throughout the drain drift region, The level and vertical direction of the drain drift region vary. SUMMARY OF THE INVENTION [0003] ο ο 099119030 The invention relates to a semiconductor device, which can improve the charge balance effect of a transistor by forming a drift region having a uniform doping concentration and improve the breakdown voltage characteristics; A "mass-filled channel that extends into the heavily doped profile improves switching speed and reduces gate-drain capacitance

Parasitic capacitance such as Cgd improves the conversion performance of the transistor device. In order to achieve the above object, the present invention provides a semiconductor device comprising: a conductive type of a first semiconductor layer comprising a plurality of channels formed in a top surface of the first semiconductor layer, the channels being in the first semiconductor Forming a mesa structure in the layer; a second semiconductor layer of a first conductivity type on the bottom surface of the first semiconductor layer; a first-epitaxial layer of a first conductivity type formed on the sidewall of the channel, the first epitaxy The layer covers at least a side of the mesa structure in the first semiconductor layer; a second epitaxial layer of a second conductivity type formed on the first epitaxial layer, the first epitaxial layer being electrically connected to the second semiconductor layer; a first dielectric layer in the channel, adjacent to the second epitaxial layer, the first dielectric layer filling at least a portion of the trench; and - forming on the dielectric layer at least (four) at least one of the sidewalls a thumb dielectric layer; a gate conductive layer formed in the first channel above the dielectric layer and adjacent to the gate dielectric layer, wherein the 'first epitaxial layer and the second epitaxial layer along the side of the channel 099327845 4-0 Form number surface ^ 5 I/* 123 I 顺十灯201101497 Doped region, the first epitaxial layer and the second epitaxial layer each have a uniform doping concentration, the second epitaxial layer has a first thickness and the first a doping concentration, the mesa structure of the first epitaxial layer and the first semiconductor layer each having a second thickness and a second average doping concentration, selecting suitable first and second thicknesses, and first doping concentration and second average doping The impurity concentration is such that a charge balance is obtained in actual operation. The present invention provides a semiconductor device comprising: an active region carrying an active device and a cut-off region around the active region, wherein the cut-off region contains an array of cut-off cells from the parent of the active region The first cut-off cell at the interface is up to the last cut-off cell. Each of the cut-off cells includes a mesa structure of a first semiconductor layer, a first epitaxial layer is formed on the sidewall thereof, and a second epitaxial layer is formed on the first epitaxial layer, wherein the mesa structure is located on the first dielectric layer only a first region of the first conductivity type formed on the top surface of the mesa structure and electrically connected to the first epitaxial layer and the first semiconductor layer; and a first a second region of the second conductivity type is formed on the top surface of the mesa structure and electrically connected to the second epitaxial layer. In the mesa structure, the second region is separated from the first region, and the second region is formed in addition to the last A cut-off unit cell is thought to be in each of the cut-off cells. The first region of the first turn-off cell is electrically coupled to the source or emitter potential of the semiconductor device, and the second region of the last turn-off cell is electrically coupled to the drain or collector potential of the semiconductor device, or near the drain , or collector potential. The remaining second region of the carrier cell is electrically coupled to the first region of the next turn-off cell in the array. Alternatively, the first field plate is placed between the last cut-off cell and the drain/collector potential. If a field plate is used, the last cutoff cell also contains a second region of the second conductivity type. 099119030 Form No. A0101 Page 6 / 123 Page 0993278454-0 201101497 The present invention also provides a semiconductor device comprising: a first conductivity type of the first semiconductor comprising a top surface of the first abundance conductor layer Forming a mesa (four) structure in a plurality of channels; feeding on a bottom surface of a second semiconductor layer of a second conductivity type of the first semiconductor layer; and located at the first semiconductor layer

a second epitaxial layer of a two-conductivity type formed on the sidewall of the trench, covering at least a sidewall of the mesa structure of the first semiconductor layer; a first dielectric layer formed in the trench, adjacent to the second epitaxial layer, the first Interposing at least a portion of the trench, one formed on the first gate dielectric layer; on the at least one first trench sidewall above the dielectric layer

a gate conductive layer formed over the first dielectric layer and adjacent to the first dielectric layer of the gate dielectric layer, wherein the second epitaxial layer forms parallel doped regions along the sidewalls of the trench, and the second epitaxial layer has uniform uniform doping a heterogeneous concentration, the second outer layer has a first thickness and a first doping concentration, and the mesa structure of the fourth guiding layer has a first thickness and a second doping concentration, and is drawn; And a second thickness and a first doping concentration and a second doping concentration to obtain a charge balance; and 099119030 wherein the semiconductor device is an active region carrying an active device and a cutoff around an active region Formed by the region, the cut-off region includes a cut-off cell array 'from the first cut-off cell that interfaces with the active region, and one until the last-off cell, each of which has: a first semiconductor layer a mesa structure having a second epitaxial layer formed on a sidewall thereof, wherein the mesa structure is located near a trench filled with a first dielectric layer instead of a form number Α0101 page 7 / 123 page f 201101497 gate conductive layer a first region of a first conductivity type formed in a top surface of the mesa structure electrically connected to the first semiconductor layer; and a second region of a second conductivity type formed in a top surface of the mesa structure, electrically connected And to the second epitaxial layer, the second region is away from the first region in the mesa structure, and is turned into each of the cut-off unit cells except the last one of the cut-off cells, wherein the first one of the first cut-off cells The region is electrically connected to the source or emitter potential of the semiconductor device, and the second epitaxial layer of the last carrier cell is electrically connected to the drain or collector potential of the semiconductor device or near the drain or collector potential, and the rest The second region of the cut-off cell is electrically connected to an equal region of its next cut-off cell in the array, respectively. The present invention also provides a method of fabricating a semiconductor device, the method comprising: forming a plurality of channels on a top surface of a first semiconductor layer of a first conductivity type, the channels forming a mesa structure in the first semiconductor layer; Forming a first epitaxial layer of a second conductivity type by epitaxial growth on the surface of the first semiconductor layer, covering at least a sidewall of the trench; preparing a first dielectric layer in the trench, wherein the first dielectric layer is filled with at least a portion of the trench Forming a gate dielectric layer over the sidewall of the first dielectric layer and adjacent to the sidewall of the at least one first trench of the first epitaxial layer; forming a gate conductive layer in the first trench, wherein the gate conductive layer is located a second semiconductor layer of a second conductivity type is formed over the first dielectric layer and adjacent to the gate dielectric layer; and 099119030 is formed on the bottom surface of the first semiconductor layer, wherein the first epitaxial layer is electrically connected to the second semiconductor layer form number A0101 page 8 / 123 page 201101497, wherein the first epitaxial layer is arranged along the sidewall of the channel and has a uniform doping concentration, The epitaxial layer has a first thickness and a first doping concentration, the mesa structure of the first semiconductor layer has a second thickness and a second doping concentration in the horizontal direction, and the appropriate first and second thicknesses and the first and second are selected Doping concentration to achieve charge balance in actual operation.其他 In other embodiments, the channel metal oxide tantalum field effect device, the insulated gate bipolar transistor device, and the W can be fabricated using the above-described fabrication process for forming a germanium-epitaxial layer/germanium-epitaxial layer nanotube structure. Tetripolar and Ρ-Ν junction diodes. The main feature of the semiconductor device provided by the present invention is that the nanotube region is prepared by an epitaxial process to obtain a uniform doping concentration. The conventional process for preparing the trench sidewall drift region is to use ion implantation followed by annealing and diffusion, which results in a concentration gradient in the drift region. By forming a drift region having a uniform doping concentration, the charge balance effect of the transistor can be improved and the breakdown voltage characteristics can be improved. Further, the semiconductor device of the present invention is formed by a low temperature process after forming a nanotube, thereby preventing outward diffusion of the nanotube region. Conventional fabrication processes use high temperature processes, for example up to 11 oo ° C, which results in the outward diffusion of the thin epitaxial layer forming the nanotube region. Further, the semiconductor device of the present invention increases the switching speed by filling the channel with a medium extending into the heavily doped substrate. In this way, the parasitic capacitance such as the gate-drain capacitance Cgd is lowered, and the conversion performance of the transistor device is improved. In this manner, the semiconductor device structure of the present invention can realize the high-density advantage that can be realized only by the vertical transistor structure, and also realize the lateral metal oxide germanium transistor 099119030 Form No. A0101 Page 9 / A total of 123 pages 0993278454-0 201101497 advantages of high conversion speed. Read the detailed description below and the drawings. [Embodiment] [0004] The present invention will be better grasped.

In accordance with the teachings of the present invention, a vertical channel metal oxide (IV) effect transistor device formed in a semiconductor layer with a dielectric filled trench, comprising a thin epitaxial layer having a thickness of submicron to several microns ("nanotube" This epitaxial layer is formed on the sidewall of the channel as a drain drift region. Therefore, the doping concentration of the drain rinsing is uniform. The doping structure of the mean sentence in the drain drift region contributes to the charge balance of the transistor, thereby increasing the breakdown voltage of the transistor. The thickness of the epitaxial layer of the nanotube is a function of the desired level of latching charge. For the copper side device, the thickness of the rice tube is submicron. For a device with a side Qv, the degree of the nanotube is approximately a few microseconds. In another embodiment, the vertical channel metal oxide 7 field effect transistor device comprises a first thin epitaxial layer formed on the sidewall of the trench 4 and a second formed on the first epitaxial layer having a reduced conductivity type. Thin epitaxial layer. The second epitaxial layer forms a drain drift, and both (10) layers ("double nephew") have uniform impurity concentrations. The change of the impurity concentration of the first-epitaxial layer improves the charge balance in the transistor even in the case of higher breakdown "τ, the domain ensures charge balance 4 in other embodiments" using the first and second thin epitaxy The basic vertical channel metal oxide 矽 field effect transistor structure of the layer can be used to fabricate an insulated gate bipolar transistor, a Schottky diode, and a Ρ-Ν junction type diode. 099119030 The vertical channel metal telluride 矽 field effect tube device of the present invention utilizes the concept of an apricot rice tube to realize a low conduction state electric form number Α0101 10th/123 page resistance (10)dS〇n), in the trench 0993278454-0 A charge-balanced drift zone ("nanotube,") is formed on the sidewall of the 201101497. In addition, the epitaxial layer is used to prepare the nanotube drift zone to ensure uniform doping concentration. Since the nanotube is very Thin, so it is necessary to slowly epitaxially grow the nanotubes in a controlled manner to achieve the desired uniform doping concentration. The uniform high doping concentration in the drift region reduces the on-resistance of the transistor, and at the same time, the height Controlled charge balancing ensures that the entire drift zone is depleted in the horizontal direction, ultimately resulting in a high breakdown voltage. In an alternative embodiment, 'the second nanotube zone 相反 with the opposite conductivity type' is located in the nanotube drift zone The second nanotube region is also formed by an epitaxial layer to make the doping concentration uniform. In the conventional device, the vertical channel metal oxide effect, the tube is formed at the base. In the semiconductor layer, the base semiconductor layer itself has a change in doping degree. Since the electric field in the entire region is not uniformly distributed in the depletion state, and the electric balance cannot be achieved, the change affects the breakdown characteristics of the transistor. In the vertical channel metal oxide material effect tube device of the present invention, the nano tube drifting region is located on the side of the nanotube region, and the doping concentration thereof is 〇& The nanotube drift zone and the nanotube body zone can also be depleted under a uniform electric field distribution" in order to obtain a high breakdown voltage property. The n-f body region and the nanotube drift region are formed on the base semiconductor layer. The base semiconductor layer has a very low doping concentration, so that its contribution to the charge balance is negligible, that is, the base layer itself. The effect of the doping variation on charge balance is negligible. The main feature of the vertical channel metal oxide (IV) field effect tube device of the present invention is that the nano tube region is prepared to obtain a uniform uniform impurity concentration. The conventional process for preparing the trench sidewall drift region is to use ion implantation 'subsequent annealing and diffusion, which results in a drift zone with a 099119030 form nickname A0101 page. By forming a drift region having a uniform doping concentration, the charge balance effect of the transistor can be improved and the breakdown voltage characteristics can be improved. Further, the vertical channel metal oxide tantalum field effect device of the present invention is formed by a low temperature process after forming a nanotube, thereby avoiding outward diffusion of the nanotube region. Conventional fabrication processes employ high temperature processes, for example up to 1100 ° C, which will result in the outward diffusion of thin epitaxial layers forming the nanotube regions. According to one embodiment of the present invention, a vertical channel metal oxide tantalum field effect device is fabricated using a low temperature preparation process, for example, at a temperature of 1 000 ° C or lower, to form a thin epitaxial layer of a nanotube region It does not spread out, but the doping area is still strictly defined. The vertical channel metal oxide tantalum field effect device of the present invention is applicable to a breakdown voltage of 20V to 1 200V. For a breakdown voltage of 20V to 100V, a single nanotube drift zone structure can be employed. If the breakdown voltage is 100V or higher, a double nanotube structure can be used to obtain a uniform electric field distribution in the depletion region. In addition, the vertical channel metal oxide tantalum field effect device of the present invention fills the channel by a medium extending into the heavily doped substrate, thereby increasing the switching speed. In this way, the parasitic capacitance such as the gate-drain capacitance Cgd is lowered, and the conversion performance of the transistor device is improved. In this manner, the vertical channel metal oxide tantalum field effect device structure of the present invention can realize the high-density advantage that can be realized only by the vertical transistor structure, and realize the lateral metal oxide tantalum. The advantage of high conversion speed of the crystal. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a vertical channel metal oxide tantalum field effect transistor device in accordance with a first embodiment of the present invention. Referring to Fig. 1, an N-type vertical channel metal oxide tantalum field effect transistor device ("N-type metal oxide 099119030 Form No. A0101 Page 12/123 Pages 0993278454-0 201101497 Chemical Crystal") 100, Formed in an array of parallel transistor cells and mb. A desired number of transistor cell axis arrays are used to obtain an N-type metal oxide crystal cell having a breakdown voltage (drain-source on-resistance) characteristic. The array of transistors can be - dimensionally arrayed, depending on the number of cell units included. For example, a stripe cell structure can be used - a column, and a hexagonal cell structure can use a two-dimensional array, as will be described in further detail below. Ο

099119030 N-type metal oxide dream crystal (10) is formed on a N + + substrate 102 having a relatively high dopant concentration. N + + is used as the drain electrode of the transistor. An oxide-filled ship 112 is formed in the p_Keyan (wafer structure_extension) layer 104. The thick oxide layer in the oxide-filled trench 112 removes the gate 118 from the drain, which reduces the tantalum capacitance Cgd and increases the transistor's switching speed. A thin N-type epitaxial layer 11() ("nanotube,") formed on the oxide-filled channel 112, which acts as an N-type drain drift region in the transistor ιι. 118^ In the channel next to the thumb oxide layer 116, the gate oxide layer 116 is located in the oxide-filled channel 112_H-type body region (10) is formed in the p_mesa structure_epitaxial layer 104' and extends almost to the polycrystalline stone At the bottom edge of the gate 118. The N+ source region 122 and the P+ body contact region 124 are formed on top of the p_ mesa structure-epitaxial layer 104. The N+ source region 122 extends only to the top of the polysilicon gate 118. The 7 glass layer (BpsG) 126 covers the entire structure, and an opening is formed at the N+ source region 122 and the p+ body contact region 124 to form a source contact electrode, so that the electrical contact is made to the electric b body 1 〇〇 Source and body. Therefore 'N-type metal oxide made of thin N- epitaxial layer 10 0 278 晶 晶 0993278454-0 Form No. A0101 Page 13 / 123 Page 201101497 The drain drift area of body 100, Having a thickness of submicron to a few microns and a uniform doping concentration. In one embodiment The thickness of the N_ epitaxial layer n 小于 is less than lum. For example, in one embodiment, the thickness of the N − epitaxial layer 11 约为 is about 10 〇 nm. For a low voltage application device (about 3 〇 v), the nanotube epitaxial layer The width or thickness is in the range of about 0.05 - 0.2_. For medium voltage applications (60-200V), the width or thickness of the epitaxial layer of the nanotube is about 0.1-〇.24111. For high-voltage applications ( 2〇〇¥ above), the width or thickness of the epitaxial (iv) is approximately in the range of 〇·2_2μπι. The thickness of the nanotubes of each voltage level depends to some extent on the epitaxial growth process used. _ Yi technology improvement, the optimal thickness can also be changed. In the actual work 'When (4) metal oxide dream crystal 1〇〇 is in the off state, the depletion layer will be from the Ν- drifting area u〇 and ρ_ mesa structure The Ρ-Ν junction between the epitaxial layers 104 expands outward. The thin epitaxial layer 11 〇 and the thick ρ_ mesa structure - the epitaxial layer 104 are completely depleted to form a balanced space charge region in the body of the transistor. The balanced space charge in the zone can get a high hit The voltage. More precisely, the charge balance in the vertical channel metal oxide MOSFET is obtained by selecting the thickness ratio of the Ν-drift region and the mesa structure _ epitaxial layer and the doping concentration ratio, ie Νχη =ρχρ, where Ν denotes the doping concentration of the Ν-drifting zone, χη denotes the thickness of the drifting zone, Ρ表Ρ- mesa structure-the concentration of the epitaxial layer, Χρ denotes the thickness of the ρ_ mesa structure-epitaxial layer. A high concentration drift region can be used in charge balancing to achieve low on-resistance and achieve a high breakdown voltage. The uniform doping concentration in the epitaxial layer 110 improves the uniform distribution of the electric field in the depletion region, and the performance of the breakdown voltage is improved. Figures 3(a) through 3(h) show an embodiment of the present invention 0993278454-0 099119030 Form number face 1 page n / page 123 201101497, vertical channel metal as shown in Figure 1 A cross-sectional view of a process for preparing an oxide tantalum field effect device. Referring to Figure 3(a), the fabrication process begins with a highly doped N++ substrate 102. The p-mesa structure-epitaxial layer 104 is grown on the substrate 102. Referring to Fig. 3(b), the structure is then masked and anisotropically etched to form a trench 106 in the p-mesa structure-epitaxial layer. These channels extend straight through the p-mesa structure - epitaxial layer 1 〇 4 and partially into the N ++ substrate 102. In other embodiments, the channels are engraved to or near the substrate 102 such that they do not extend into the substrate.准确 The exact thickness of these channels does not play a decisive role, as long as the bottom of the channel is sufficiently close to the N ++ substrate 1〇2 so that the substrate can be counter-doped to the bottom of the subsequently formed thin epitaxial layer, It will also be described in detail. The P-mesa structure-epitaxial layer 1〇4 thus formed includes a channel and a mesa structure. A suitable mesa structure-epitaxial layer 104 doping level is selected to achieve a balanced space charge when depleted under reverse bias, and the doping level is a function of the width of the mesa structure to a certain extent. For example, when the width of the mesa structure

When 〇· 333 Um, the P-mesa structure! · The doping level of the epitaxial layer 1 〇 4 is about 6 x l016 cm -3 . See Fig. 3(c) for the growth of an N-type epitaxial layer 110 on the exposed surface of the semiconductor substrate by epitaxy. Therefore, the N- epitaxial layer is grown on the sidewalls and top surface of the p-tablet structure-epitaxial layer 1〇4, and on the exposed surface of the N++ substrate 1〇2. In an alternative embodiment, the channel is prepared. The hard mask used in 1〇6 may remain on the P~ mesa structure-epitaxial layer 104 during the epitaxial growth of the nanotubes. This causes the N- epitaxial layer 11〇 to grow only in the channel 1 〇6. An oxide layer 113 is then deposited to fill the trenches 1 〇 6 as shown in Figure 3(d). The deposited oxide layer 113 extends and the 099119030 covers the P-mesa structure - the mesa structure of the epitaxial layer 104. Form No. A0101 Page 15 / Total I23 Since the doping concentration of the substrate 102 0993278454-0 201101497 (the bottom) is extremely high, Even during the epitaxial growth process, and even during the rest of the preparation process, the type dopants are directly diffused outward from the substrate, so that the partial N_ epilayer layer on the N++ substrate 102 is as shown in the figure. The dotted line circle 114 is removed by the outward diffusion of this highly doped n++ base m. After depositing the oxide, the surface of the semiconductor substrate is flattened by a chemical mechanical polishing process. The polishing process removes excess oxide and a thin epitaxial layer over the mesa structure of the P-mesa structure-epitaxial layer 104. See Section 3 (e) ® ' to deposit oxide layer 113 down the channel so that the oxide layer fills only a portion of the channel, forming an oxide-filled channel 112. More precisely, 5' etches the redundant oxide layer 1 to the desired depth so that the subsequent _ electrodes are aligned with the body region. A gate gasification layer 116 is grown on the sidewalls of the channel. The gate oxide layer 116' is to be grown by a low temperature process to avoid outward diffusion of the thin germanium-epitaxial layer 110. See Fig. 3(f) 'deposited in the trench—a polycrystalline 7 layer and inscribed to form an embedded polysilicon gate. In one embodiment, the deposited polycrystalline layer is first smoothed, and the deer is followed by The surname is engraved to dent the polycrystalline layer in the channel. After the salty polycrystalline __hetero 118 is passed through the ion implantation process, the P body region 12 is formed on the upper portion of the mesa structure-epitaxial layer 104, as shown in Fig. 3(g). In one embodiment, the ions/疋 are implanted at an angle of 疋. The N + source region 122 is then formed by a second ion implantation. The resulting source region 22 is located in the body region 120 and adjacent to the channel sidewalls. As shown in Figure 3(h), source region 122 extends down to the vicinity of the top edge of polysilicon gate electrode 118. In particular, when the depth of the N + source region m is controllable, the source and source regions are aligned with the top edge of the polycrystalline spine 0993278454-0 tree electrode and with a small portion of the gate electrode 099119030 Form No. A0101 Page 16 / a total of 123 f 201101497 As shown in Figure 3 (h), the P + body contact region 124 is formed by a third ion implantation and finally near the source region 122. A layer 126 of deposition medium (e.g., a enamel-containing glass) covers the entire semiconductor substrate. In the case, the __glass layer is smoothed by a chemical mechanical polishing process, and then a contact opening is formed in the ruthenium-containing (tetra) glass layer (BPSG) 126 so that the N+ source region 122 and the p+ body contact region 124 Bare out. As shown in Fig. i, a patterned metal layer is deposited and source electrode 130 is formed. Then, a passivation layer is deposited over the entire structure (there is no illusion in the figure to passivate the (4) metal oxide crystal. The N-type metal oxide germanium transistor of the present invention is 1 〇 0, which can be in the transistor. For the low-voltage (3〇v and below) application device, a cell pitch (tcp) of about 〇8岬, a mesa structure of plutonium (p-mesa structure-epitaxial layer) can be used. The width and the width of the epitaxial layer of 7511111. The uniform N- epitaxial layer with high doping concentration makes the N-type metal oxide tantalum transistor 1〇〇 stable and reliable breakdown voltage and voltage characteristics. More specifically, we have known that for an effective charge balance between a drift region and a body of a vertical metal oxide tantalum transistor, the thickness ratio of the N-drift region to the P-mesa structure region, Their respective doping degrees are linearly inversely proportional. Moreover, we also know that when the doping concentration of each region in the vertical channel metal oxide 矽 field effect transistor is about 1E12 cm 2 , its charge balance is reached. Best state" The thickness ratio between the N- epitaxial layer 110 and the P-mesa structure-epitaxial layer 104 has the following relationship: the thickness of the N- epitaxial layer 'N-the doping amount of the epitaxial layer / cm3 099119030 Form No. A0101 0993278454-0 Page 17 of 123201101497 =or p-mesa structure - thickness of epitaxial layer, p_ mesa structure - doping amount of epitaxial layer / cm3 lE12cm_2or ri〇12cm-2. > idea: P-mesa The thickness of the structure-epitaxial layer is about the mesa structure in the horizontal direction, and the thickness of the P-mesa structure-epitaxial layer is divided by 2 because there is an N-epit layer on both sides of the epitaxial structure-epitaxial layer. One half of the structure-epitaxial layer balances one epitaxial layer on one side and the other half balances the N- epitaxial layer on the other side. In one embodiment, doping per unit volume in the N- epitaxial layer no The concentration is at least twice that of the P-mesa structure-epitaxial layer to minimize doping compensation in the epitaxial layer by p-type impurities from the mesa structure-epitaxial layer. In another embodiment, Production of N-type metal oxide tantalum transistor with breakdown voltage of 3〇V The parameters are as follows: 30V metal oxide 矽 field effect transistor - width (μιη) height (μιη) doping concentration and remark channel 0.20 2.00 50-200 Α gate oxide polysilicon gate 0.16 0.60 Ν ++ in situ doping P - Countertop structure - Epitaxial layer 0.35 1.75 5.7Ε16 cm-3 N- Epitaxial layer 0.075 2.00 1.33E17cm·3 2 42 pohms*cnf Gate leakage dielectric 0.20 1.00 Si〇2 Polycrystalline germanium containing boric acid above the gate of polycrystalline germanium 0.20 0.40 by chemistry Mechanically polished flattened glass/tetraethyl orthosilicate with cell borate spacing of 0.70 N- epitaxial layer resistance: A*Rds = 42p〇hms-cm'2 In the above example, P-mesa structure-epitaxial The concentration of each region in layer 1〇4 is 1.99E12 cm_2 (approximately 2E12 cm-2), and the concentration of each region in the N- epitaxial layer 110 is 9.91E11 cm_2 (approximately 1E12 cm_2). 099119030 Form No. A0101 18 Page / Total 123 pages 0993278454-0 201101497. The reason why the concentration of each region in the p-mesa structure-epitaxial layer 104 is set to an optimum value of 1E12 cm 2 is because a single-p_ mesa structure-epitaxial layer 104 supports p-mesa structure-epitaxial The charge balance of the drain drift regions of the two n-epitaxial nanotubes on the sidewalls of the layer. That is to say, a P-table junction-half doping concentration of each region in the epitaxial layer 1〇4, to support the charge balance of one of the two N- epitaxial nanotube drain drift regions. A cross-sectional view of a vertical channel metal oxide tantalum field effector device in accordance with a second embodiment of the present invention. Referring to Fig. 2, an N-3L vertical channel metal oxide tantalum field effect device ("N-type metal oxide magnetite crystal") is formed in a parallel transistor cell 2 〇 1 a and In the array of 201b, a certain number of transistors are used to form an array 'to make the N-type metal oxide 矽" crystal 2 〇 (y has the required breakdown voltage characteristics. Is it a one-dimensional transistor array or two-dimensional electricity? The crystal array depends mainly on the number of transistor unit cells used. The structure of the N-type metal oxide tantalum transistor 2〇〇 has an additional thin P-type epitaxial layer 2 in addition to the thin epitaxial layer 21 Except for 〇8, the remaining structure is the same as the N-type metal oxide ridge crystal as shown in Fig. 1, and the β N_ epitaxial layer 210 and the P- epitaxial layer 208 form a "double nanotube tube, structure. In addition, the transistor cell is formed in the P-type epitaxial layer 2〇4, and the doping concentration of the p-type epitaxial layer 2〇4 is very light, as in the “p_ mesa structure epitaxial layer in FIG. 2, The boundary of the N- epitaxial layer 21 is defined by a thin epitaxial layer 208 to form a parallel doped region having a uniform doping concentration. When the N epitaxial layer 21 and the epitaxial layer 208 are depleted, the thin epitaxial layer 208 can ensure a uniform electric field distribution, thus improving the breakdown voltage characteristics. In the N螌 metal oxide tantalum transistor 200, the use is sub- Micro-thickness to a few 099, 19030, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The thickness of the N_ epitaxial layer 21 ^ is lum. For example, the thickness of the N- epitaxial layer 21 在 is about the sub-layer (10). Similarly, the P- epitaxial layer 208 also has a submicron thickness and a uniform doping concentration. For example, the thickness of the P- epitaxial layer 208 is about 25 〇 nm. The doping concentration of the p-extension layer 208 is greater than the doping concentration of the p_ mesa structure-epitaxial layer 2〇4, which is smaller than the doping concentration of the thin epitaxial layer 210. As described above, the thickness of the nanotube layer (the N- epitaxial layer 210 and the P- epitaxial layer 2〇8) is a function of the breakdown voltage level of the device + and the P-epitaxial layer is utilized. 208 defines the advantages of the N- epitaxial layer drain drift region boundary, which is not possible in ordinary transistors When the epitaxial layer 2〇4 of the P-mesa structure is prepared by a conventional epitaxial process, the epitaxial layer 204 itself has a doping concentration change of about 10%. This change in doping concentration, It is an intrinsic result when growing a thick epitaxial layer in the epitaxial process, which cannot be avoided. When the drain drift region of the N-type epitaxial layer is directly formed in the p_ mesa structure-epitaxial layer, the doping concentration of the P-mesa structure_epitaxial layer The variation may cause the electric field to be non-uniform when the two regions are depleted. However, according to the present invention, (4) the P- epitaxial layer is closer to the boundary of the N_ material extension layer. Since the thin p- epitaxial layer 2〇8 can grow slowly, its push concentration and thickness can be well controlled. Therefore, this ensures that when the N-type epitaxial layer 210 and the P-type epitaxial layer 204 are depleted, the electric field at their p_N junctions is uniformly distributed. The doping concentration of the P-mesa structure-epitaxial layer 204 can be low so that its contribution to charge balance is small, and the majority of the charge of the charge balancing blanket is provided by the thin epitaxial layer 208. Therefore, the influence of the doping concentration change inherent in the epitaxial layer 204 on the charge balance can be neglected. 099119030 Form No. A0101 Page 20/123 Page 0993278454-0 201101497 Figures 4(a) to 4(d) show the preparation of a double nanotube according to one embodiment of the present invention, as shown in Figure 2 A cross-sectional view of a vertical channel metal oxide FET device fabrication process. The N-type metal oxide tantalum transistor 200 as shown in FIG. 2 except for the lightly doped P-mesa structure epitaxial layer 204 and an additional thin P-type epitaxial layer 208, the remaining preparation process and the The preparation process of the N-type metal oxide tantalum transistor 100 shown in Fig. 1 is the same. Therefore, the same preparation process is as shown in Figures 3(a) to 3(h), and will not be repeated here. Referring to Fig. 4(a), a lightly doped P-mesa structure-epitaxial layer 204 is formed on the N + + substrate 202 and then etched to form a trench and mesa structure. A p_ type epitaxial layer 208 is grown on the exposed surface of the semiconductor structure by an epitaxial process. A P-type epitaxial layer is grown on the sidewalls and top surface of the P-mesa structure-epitaxial layer 204, and on the exposed surface of the N++ substrate 202. A thin epitaxial layer 210 is then grown on the exposed surface of the semiconductor structure by a second epitaxial process. Therefore, as shown in Fig. 4(a), the N-type epitaxial layer 210 is grown on the p-type epitaxial layer 208. In an alternative embodiment, the sturdy mask used to etch the trench can be left in the epitaxial growth process of the p-type epitaxial layer 208 and the N-type epitaxial layer 210. Above 204, this causes the epitaxial layers to grow only in the channel and then deposit an oxide layer 213 to fill the trench, as shown in Figure 4(b). The deposited oxide layer 213 extends and covers the mesa structure of the p-mesa structure-epitaxial layer 204. When the N-type epitaxial layer 210 and the p-type epitaxial layer 208 are formed 'they are adjacent to the portion of the N ++ substrate 102 (as indicated by the dotted circle 214 in the figure), due to the N ++ substrate 2 The high doping concentration of 〇2 is removed by 099119030 and is doped in the opposite direction. After depositing the oxide, the form nickname A0101 Page 21 of 123 passes through the chemical machine 0993278454-0 201101497 The mechanical polishing process flattens the surface of the semiconductor substrate. The chemical mechanical polishing process removes excess germanide and a thin epitaxial layer over the mesa structure of the p-mesa structure-epitaxial layer 204 and a thin p- epitaxial layer. Referring to Fig. 4(C), the residual oxide layer 213 is etched down until it is recessed in the trench to form an oxide filled trench 212. A gate oxide layer 216 is grown on the sidewalls of the trench, and a polycrystalline rhyme is deposited, and a polysilicon gate electrode 218 is formed down. Referring to Fig. 4(d), a P-body region 22G, an N+ source region 222, and a P + body contact region m are formed by ion implantation. A layer of dielectric 226 (e.g., bismuth glass containing boric acid) is then applied over the entire semiconductor structure. Smooth the glass containing the shout and form a pattern to form a contact opening. Then, a source electrode 23 (Fig. 2) is formed to make electrical contact with the N + source region 222 and the P + body contact region 224. Select a suitable P mesa structure _ epitaxial layer 2Q4 and thin p-type epitaxial layer 2 〇 8 push level ("average doping concentration"), paste when these two regions are depleted under reverse bias, the same Ν _ type epitaxial layer 21 () - the domain is balanced by the space. The level of the Ρ-mesa structure-epitaxial layer 2Φ4 and the thin Ε-type epitaxial layer 208 is a function of the width of the ρ' type and the width of the Ρ- mesa structure-epitaxial layer 204. Further, as described above, the thickness ratio of the Ν-type epitaxial layer to the P i epitaxial layer/ρ_ mesa structure epitaxial layer has a linear inverse relationship with their respective ## concentrations. More precisely, for charge balance, the thickness ratio and doping concentration ratio between the N-type epitaxial layer 21〇 and the ρ_type epitaxial layer/ρ-mesa structure-epitaxial layer 2〇9/2〇4 The following relationship exists: thickness of Ν-type epitaxial layer 掺杂 doping amount of Ν_type epitaxial layer / cm_3 - (thickness of p-type epitaxial layer 'doping amount of p_type epitaxial layer / cm-3>) + (〇 5 ' 099119030 Form No. A0101 Page 22 of 123 0993278454-0 201101497 p-type mesa structure - thickness of epitaxial layer 'p_type mesa structure - doping amount of epitaxial layer / cm_3) =0. 5 ^ P - Type epitaxial layer and p_type mesa structure - Total thickness of epitaxial layer 'p-type epitaxial layer and p-type mesa structure - average doping amount of epitaxial layer / cm - 3 lE12ciir2 〇r ri 〇 12 cm~2. Note: The thickness of the P-mesa structure-epitaxial layer is the mesa structure in the direction of the level.

In one embodiment, a preparation parameter of an N-type metal oxide tantalum transistor having a breakdown voltage of 100 V is as follows: 100 V metal oxide tantalum field effect tube width (μπι) height (μπι) doping concentration channel 0.50 4.25 500 -1000 ΑCalcium Oxide Polycrystalline Gate 0.16 0.60 Ν++In-situ doped P-mesa structure-epitaxial layer 0,50 4.00 5E14cm·3 (or 0.25Ellcm-2 for two nanotubes N-type epitaxy Concentration of each region in the drain region of the layer) P- epitaxial layer 0.25 4.00 3.95E16cnf3 (or concentration of each region of 0.9875E12 cnf2) N· epitaxial Tang—^^ 0.125 ______—0.20 4.00 8E16cm'3 42 pohms*citf2 1.00 Si〇2 •TwJ w|| ~ Polystyrene-containing bismuth glass above the polycrystalline germanium gate 0.20 -1, 0.40 矽 glass/tetraethyl orthosilicate containing cell pitch 1.75 N by chemical mechanical polishing - Epitaxial layer resistance: A*Repi=225 pohms-cm·2; The resistance of the P- epitaxial layer and the P-external layer nanotube are equal to the resistance of the N- epitaxial layer

In one embodiment, a preparation parameter of an N-type metal oxide tantalum transistor having a breakdown voltage of 200 V is as follows: 099119030 Form No. A0101 Page 23 / Total 123 Page 0993278454-0 201101497 200V Metal Oxide Tantalum Effect Tube Width (μιη Height (μιη) doping concentration and remark channel 0.50 8.25 500-1000 human gate oxide polycrystalline octagonal pole 0.16 0.60 Ν ++ in-situ doped P-mesa structure - epitaxial layer 0.50 8.00 5E14cm-3 ( 〇r0.25Ell cm·2 is the concentration of each region in the drain region of the two nanotube N-type epitaxial layers) P- epitaxial layer 0.25 8.00 3.95E16 cm-3 (or 0.9875E12 cm·2·each region Concentration) N- Epitaxial layer 0.125 8.00 8E16cm-3 42 p〇hms*cm_2 Gate leakage clear 0.20 1.00 Si02 Polysilicate glass containing boric acid above the gate of the polycrystalline germanium 0.20 0.40 Polished glass plate containing boric acid by chemical mechanical polishing /Tetraethyl orthosilicate cell spacing -*---- 1.75 N- epitaxial layer resistance: A*Repi = 225pohms-cni'2 P- epitaxial layer and P- epitaxial layer nanotubes have resistance N-epitaxial _ layer resistance is equal

The fifth graph is not in the depletion state, along the mode of the electric field distribution of the drift region of the n-type metal oxide semiconductor transistor 1()_nanotube as shown in the (10)

Small I & Qing sign / show / melon run and P - inside (when 曰 is exhausted 'line 550 means electric field drifts along the nanotube drain and direction cloth ' line 552 represents the electric field in the p-mesa structure epitaxial layer distribution ° Line 554 represents the direction distribution of the electric field along the gate and oxide; as shown in Figure 5, due to the name of the drain drift region of the nanotube; the degree of agronomy is uniform, and the electric field is also N- The Μ distribution of the epitaxial layer of the nanotubes in the whole degree of direction, which is higher than the breakdown of the enamel. In 099119030 page 24 / a total of 23 pages of H metal oxide (four) crystal money, there is no deep oxygen below the gate ^ form It is also balanced by mi. In this case, the electric field distribution will differentiate as indicated by the dotted line 556 in No. 5,993,278,454 to 201101497. This electric field gradient adversely affects the breakdown voltage characteristics of the transistor. Semiconductor Device According to other aspects of the present invention, the above-described N-type epitaxial layer/P-type epitaxial layer nanotube structure can also be used to fabricate other semiconductor devices. In one embodiment, an N-type epitaxial layer is utilized. Preparation of Insulated Gate Bipolar Crystals by P-Type Epitaxial Layer Nanotubes In another embodiment, the Schottky diode is fabricated using an N-type epitaxial layer/P-type epitaxial layer nanotube structure. In another embodiment, an N-type epitaxial layer is utilized. P-type epitaxial layer nanotube transistor structure is used to prepare PN junction diode. These insulated gate bipolar transistor, Schottky diode and PN junction diode can pass through the single nephew as shown in Fig. 1. The rice tube structure, or the double nanotube structure as shown in Fig. 2. And the preparation of the diode device does not require a gate electrode in the channel of the semiconductor unit cell. Further, in one embodiment of the invention An N-type metal oxide tantalum transistor can be prepared by using an array of transistor cells (such as the transistor cell shown in FIGS. 1 and 2), and a transistor cell array is inserted into the array. Or a plurality of insulated gate bipolar transistor devices, or Schottky diodes or PN junction diodes, or devices using the same type of N-type epitaxial layer/P-type epitaxial layer nanotube structure Any combination. The vertical N-type metal oxide or P-type metal oxide layer thus formed The crystals are connected in parallel with an insulated gate bipolar transistor device, a stellite diode, and/or a PN junction diode. The insulated gate bipolar transistor device, Schottky diode, and/or PN junction diode The body, in parallel with the vertical channel metal oxide 矽 field effect transistor, is very advantageous for the operation of the device, as will be described in more detail below. 099119030 Form No. A0101 Page 25 / 123 Page 0993278454-0 201101497 The sixth chart is not in accordance with the present invention. One embodiment of an insulated gate bipolar transistor device. Referring to Figure 6, an insulated gate bipolar transistor device 300 is formed on the N-type buffer layer 302 to function as a field stop. In one embodiment, the wound-type buffer layer 302 is implanted by epitaxial growth or by back implantation to a thickness of 2-15 microns. The N-type buffer layer 302 can also serve as a starting substrate. A P-type semiconductor layer is formed on the bottom surface of the N-type buffer layer 3〇2 to constitute a P+ internal emitter region 332. Metal layer 334 is used to form the collector to make electrical contact with P+ internal emitter region 332. As shown in Fig. 6(a), it is known that in the terminology of the external device connector, the internal emitter of the insulated gate bipolar transistor is the collector, and the remaining N-type is prepared by referring to the method shown in Fig. 2 Epitaxial layer / p-type epitaxial wide-nanotube n-type metal oxide tantalum transistor. Gate polysilicon electrode 318 is located in oxide filled trench 312 and gate dielectric 316 is adjacent. An N-type epitaxial layer 310 and a P-type epitaxial layer 308 are formed on the sidewalls of the channel. The P-type body region 320 serves as the internal collector of the insulated gate bipolar transistor device 300. Metal layer 330 forms an emitter electrode to form an electrical contact with P+ contact region 324 of P-body internal collector 320 and electrical contact with N+ source region 322 via bismuth glass 326 containing boric acid. As shown in Figure 6(a), it is known that in the terminology of external device connectors, the internal collector of an insulated gate bipolar transistor is the emitter. In an array of transistors, there are many advantages to connecting an insulated gate bipolar transistor device to a metal oxide tantalum field effect device. First of all, in high frequency conversion applications, a nanotube insulated gate bipolar transistor device is required. Secondly, in a common array, the size and system cost of the 'passive device' will be reduced after the integration of the insulated gate bipolar transistor prepared by the same fabrication method and the metal oxide tantalum field effect transistor, and the whole system is 099119030. Forms St A0101 Page 26 of 123 Page 0993278454-0 201101497 Power dissipation will also be reduced. In addition, the doping concentration of the N-type epitaxial layer of the base layer forming the base region of the insulated gate bipolar transistor device is relatively high compared to the insulated gate bipolar transistor device prepared by the conventional process (for example, 2 Magnitude). Therefore, the amount of electricity stored in the base region will be reduced, and the life of a small number of carriers will also be shortened. The insulated gate bipolar transistor device fabricated by the N-type epitaxial layer/P-type epitaxial layer nano tube preparation process of the present invention will have a lower collector-emitter voltage Vce, which makes conduction Lower losses and faster conversions. Of course, in other embodiments,

Insulated gate bipolar transistor devices can also be formed separately on a semiconductor substrate without the need for metal oxide germanium field effect transistors or other devices.

Fig. 7 is a cross-sectional view showing a Schottky diode according to an embodiment of the present invention. Referring to Fig. 7, a Schottky diode 4 is formed on the N+ substrate 402. Metal layer 442 is used to provide electrical contact to N+ substrate 402 to form a cathode electrode. The remaining N-type epitaxial layer/p-type epitaxial layer nanotube N-type metal oxide tantalum transistor is prepared in the same manner as shown in Fig. 2, but the difference is that no multi-crystal lattice is formed. A shallow P + anode contact region 424 is formed in the facet structure - epitaxial layer 404, the pole, the body region, the source region, and the body contact region. The p + anode contact region 424 is heavily doped to ensure ohmic contact in this region. The Schott Foundation layer 440 is deposited over the semiconductor structure and is in contact with at least the N-type epitaxial layer 41, the P-type epitaxial layer 4A8, the P-mesa structure-epitaxial layer, and the P+ anode contact region 424. At the junction 446 between the Schottky metal layer 44 and the epitaxial layer 410, a Schottky junction is formed. The SCHOTT Fund 440 constitutes the anode electrode of the monopole body 400. The first? (&) The chart does not have Schottky's two-pole circuit symbol. In an alternative embodiment, before depositing the stellite metal, the top surface of the P-mesa structure _ epitaxial layer 4 〇 4 099119030 form nickname A0101 page 27 / 123 page 0993278454-0 201101497 P + type implanted characters (Example 1 or BF2) to form: a mixed side doped region 438. The doped region 438 extends and passes through the entire surface of the mesa:, including the N-type epitaxial layer 410 and the P-type epitaxial layer 408. The doped region 438 has the effect of reducing the surface concentration of the epitaxial layer to adjust the Schottky. The height of the Mann, 'reducing leakage current' when the Schottky diode is off ensures good Schottky contact. In another embodiment, an N-type metal oxide oxide crystal is prepared by using a transistor cell array as shown in FIGS. 1 and 2, and the same N-type epitaxial layer/P_ type is also used. A Schottky diode device composed of an epitaxial nanotube transistor structure is inserted into the transistor cell array. The Schottky diode device inserted into the transistor array has the function of improving the reset of the transistor. In one embodiment, 10% of the crystal unit cells are all thiol diodes. Figure 8 is a cross-sectional view showing a p-N junction diode in accordance with one embodiment of the present invention. Referring to Fig. 8, a P_N junction diode 500 is formed on the N+ substrate 502. The metal layer 542 is used to provide electrical contact to the N + substrate 502 to form a cathode electrode, the remaining N-type epitaxial layer / P-type epitaxial layer of the nanotube N-type metal oxide tantalum transistor, as in the second The same method shown in the figure is prepared 'but differing in that the polysilicon gate electrode, the source region and the body contact region are not formed, but a P + anode contact region 52 is formed in the P-mesa structure epitaxial layer 504. An ohmic metal layer 540 is deposited over the semiconductor structure and is coupled to the P+ anode contact region 520 to form an anode electrode. At the junction 546 between the P + anode contact region 520 and the N-type epitaxial layer 510, a P-N junction is formed. Fig. 8(a) shows the circuit symbol of the P-N junction diode 500. Therefore, the PN junction diode 500 made by the same N-type epitaxial layer/P-type epitaxial layer nano tube transistor preparation process can be used with the same kind of 099119030 Form No. A0101 Page 28 / 123 Page 0993278454-0 201101497 Preparation process N-type metal oxide tantalum or p-type oxide tantalum transistor formed in an array. Integrating the P-N junction diode and the vertical channel metal gas 矽 field effect transistor device in the same transistor array eliminates the need for external diodes, reducing cost and improving performance. In Figs. 6 to 8, an insulated gate double crystal device, a Schottky diode, and a P-N junction diode are prepared using a double nanotube structure. In other embodiments, the same insulated gate dual crystal device, Schottky diode, and P-N junction diode can be fabricated using a single N- epitaxial layer nanotube. Preparation Process Using P-Type Substrate According to another aspect of the present invention, a vertical channel metal oxide tantalum field effect transistor having a thin N-type epitaxial layer and a P-type epitaxial layer ("nanotube") is prepared. The method is to use a lightly doped P-type single crystal substrate as the body of the device. The back layer of the vertical channel metal oxide FET device is formed by epitaxial growth or ion implantation. In addition, the same preparation method can be used to prepare an insulated gate bipolar transistor device, a stellite diode, and a P-N junction diode or a combination thereof. More importantly, the same preparation method can also be used to prepare a vertical channel metal oxide oxide field transistor cell unit' with one or more insulated gate bipolar transistor devices, Schottky diodes, and PN junctions. Combination of diodes to achieve parallel structure 'Electrical performance of improved power metal oxide tantalum field effect device device 9th to 9th (k) and 9th (fl) to 9th (11th) In accordance with an alternative embodiment of the present invention, a cross-sectional view of a fabrication process for a vertical channel metal oxide tantalum field effect device and an insulated gate bipolar transistor device is prepared. Referring to Figure 9(a), a method for fabricating a vertical channel metal oxide tantalum field effect device is to use a P-type single crystal germanium substrate (099119030 Form No. A0101 Page 29 / 123 Page 0993278454-0 201101497 P _ basic) 6 0 4 as a starting material. In one embodiment, the doping concentration of p~ the base 604 is 1E14 to 1E15 cnf3. As shown in Fig. 9(b), the #P-substrate 604 is patterned to form a channel 6〇6. As in the above-described preparation process, a vertical channel metal oxide field effect tube or other device can be formed in the mesa structure (P-mesa structure substrate) of the substrate 6〇4 without using epitaxial growth.

Referring to Fig. 9(c), a P-type epitaxial layer 608 is formed on the surface of the p-substrate 6?4 by an epitaxial process. P-type epitaxial layers 6〇4 are formed conformally on the exposed surface of P-substrate 604, in the trench, and on the top and bottom surfaces. Then, as shown in Fig. 9(d), a type epitaxial layer wo is formed on the surface of the p-type epitaxial layer 608 by the second epitaxial process. The epitaxial layer 610 is formed conformally on the conformal p-type epitaxial layer 608.

As shown in Fig. 9(e), the next process is similar to the steps shown in Figs. 4(b) to 4(d), and the crystal structure is completed on the top surface of the P-mesa structure substrate 60|. . More specifically, the channel 606 is filled with a dielectric material such as oxidized 612 and back etched. A polysilicon layer 618 is formed in the channel to form a gate terminal adjacent the gate dielectric 616. A doped region is then formed on the top surface of the p_ mesa structure substrate 604. The p-body region 62 is formed accordingly. In the P-body region 620, a heavily doped N+ source region 622 and a heavily doped P+ body contact region 624 are formed. Then, this embodiment continues to complete the top processing. That is, referring to Fig. 9(f), an insulating layer (e.g., Shixia glass 626 containing shed acid) is formed over the entire surface of the semiconductor structure. An opening is made in the bismuth glass 626 containing boric acid, and a metal layer 630 is deposited to contact the N + source region 622 and the P + body contact region 624. The metal layer 630 will form a source electrode or an emitter electrode, depending mainly on the bottom processing type 099119030 Form No. A0101 Page 30 / 123 Page 0993278454-0 201101497 Type. In an alternative embodiment, when the bottom processing is performed, the top processing is not completed and is not performed, as will be described in more detail below. As shown in Fig. 9(g), in the present embodiment, after the top treatment is completed, the semiconductor structure is back-grinded to remove the excess liner material at the bottom. Back grinding continues until the bottom of the oxide filled trenches', i.e., up to the bottom surface of oxide layer 612. Therefore, the excess N-type and P-type epitaxial layers at the bottom of the channel are removed. Ο

As shown in Fig. 9(h), after back grinding, an N+ doped layer 660 is formed at the bottom of the P-mesa structure by backside implantation (e.g., ion implantation or diffusion). In this manner, a vertical N-type metal oxide tantalum transistor 600 is formed, wherein the N + doped layer 660 serves as a drain, the N- epitaxial layer 610 serves as a nanotube drain drift region, and the N+ region 622 serves as a source. And a polysilicon layer 618 is used as the gate. In other embodiments, the N+ layer 660 acts as an ohmic contact to the cathode of the Schottky diode or P-N junction diode. As shown in Figure 9(i), after local implantation is initiated by rapid thermal annealing or laser annealing, the bottom plating metal 664 is used to form a drain electrode at the bottom of the abundance conductor structure. In one embodiment, the metallization of the backside is plated, and the metal of the f 1 roll® i,-i'VK.. can be selected from titanium, nickel or gold. In another embodiment, an insulated gate bipolar transistor is fabricated using the same vertical channel metal oxide semiconductor field effect transistor structure containing N-type and P-type nanotubes. As shown in Fig. 9(h), after the N+ layer 660 is formed by the back N + implantation, the P+ doping layer 662 is formed at a position required by the insulated gate bipolar transistor device by the second back implant. The N+ doped layer 660 forms an N-type buffer layer 662 or field barrier of the insulated gate bipolar transistor, and the P+ doped layer 662 forms the P+ internal emitter of the insulated gate bipolar transistor. The P+ implant may be a Thin layer, all vertical channel metal oxide 099119030 Form No. A0101 Page 31 / 123 Page 099327MM-0 201101497 The semiconductor field FET structure is integrated into the IGBT, or some specific The semiconductor structure is selectively integrated into an insulated gate bipolar transistor device. As shown in Fig. 9(k), the collector electrode of the P+ internal emitter 662 is formed by the bottom metal plating 664. In addition to having an additional P+ layer 662 through the back implant, the fabrication process of the bipolar transistor device 680 is the same as that of the n-type metal oxide; The P-body region 620 functions as a back collector in the insulated gate bipolar transistor device 680. The top metallization 63 〇 constitutes the emitter electrode 'contacts the P-body internal collector region 620. In summary, as shown in Figure 9 (e), after the formation of the transistor structure above the P_ mesa. structure 6〇4, before the bottom, the mask or the top treatment is not completed, while the bottom treatment is performed, The top processing can be done as shown in Figure 9 (f). The 9th (fl)th to the 9thth (11th)th drawings show the treatment process which can be selected by using a P-type single crystal substrate which is lightly pushed, to prepare a vertical channel metal oxide (four) field effect tube and other devices. Referring to Fig. 9 (fl), 'after the 9th (e) figure', a layer of stone 626 containing acid-cutting is formed to cover the entire top surface of the semi-guided structure. Then, before proceeding to the process, the wire feeds the excess Ρ-substrate until it approaches the bottom of the oxide-filled channel, as shown in Fig. 9 (g〇. Contains Wei (4) The glass layer 626 protects the top of the metal oxide tantalum field device during the f-treatment. In one embodiment to the 'back grinding—straight to the position below the channel 2_5 micro-seeking. That is, in the back grinding After the treatment, only the 25-micron P-substrate layer 6G4 remains under the channel. When the _P+ layer must be formed on the back side by epitaxial growth, the remaining substrate on the bottom surface becomes critical. See Section 9 ( Hi) Figure 'by epitaxial growth or ion implantation, in the back shape 099119030 0993278454-0 Form No. A0101 Page 32 / 123 pages into N + Tu 661. As shown in Figure 9 (hi), dopants from the material The layer 661 is outwardly diffused, and the N- epitaxial layer and the p_ epitaxial layer at the bottom of the channel are reversely doped to form an N + layer. If a vertical 1 ^ type metal oxide magnetite crystal is to be prepared It is necessary to directly metallize the N + layer 661. However, if one is to be prepared An insulated bipolar transistor device is formed by a field growth or ion implantation to form a P+ layer 663 on the back, as shown in Fig. 9 (j 1). Especially if the P + layer 663 is to be grown, due to the epitaxy During the growth process, the P+ layer 663 will be contaminated by the top metal, so it is best to cover the top with a layer of strontium containing boric acid instead of exposing the metallization. ..... . . . . 9 (kl) shown in the figure 'If an insulated gate bipolar transistor device is to be fabricated, the back metallization 664 is used in the formation of the P+ layer 663. Then, a top treatment is performed to obtain a bismuth glass layer 626 containing boric acid. An opening is formed in the middle, and a top metal plating 630 is formed, as shown in Fig. 9 (11). The thus formed insulated gate bipolar transistor device is 78 0 0, wherein the top metal plating 630 is used as the emitter electrode 'bottom mineral metal 664 Collector electrode. The fabrication process described in Figures 9(a) through 9(11) can be used to fabricate an insulated gate bipolar transistor device, Schottky diode and/or PN junction diode. Combined metal oxide tantalum transistor array. Figure 10 According to one embodiment of the present invention, a vertical N-type metal oxide combined with an N-type insulated gate bipolar transistor is prepared using a process as shown in Figures 9(a) through 9(k). A cross-sectional view of the device, the eleventh figure shows an equivalent circuit diagram of the integrated metal oxide tantalum field effect transistor and the insulated gate bipolar transistor device shown in Fig. 10, and Fig. 11(b) shows The fabrication time diagram of the metal telluride 矽 field effect transistor and the insulated gate bipolar transistor device shown in Fig. 11(a) is shown in Fig. 10, in the semiconductor device 8 〇〇 Form No. 1010101 Page 33 of 123 In 201101497, the preparation process of 'N-type metal oxide tantalum transistor 8011 other than p+ layer 663 except 'special transistor cell is only used to form the internal emitter of insulated gate bipolar transistor】) Both are the same as the insulated gate bipolar transistor device 801a. In addition, the structure of the vertical N-type metal oxide magnetite 801b and the insulating gate bipolar transistor device 80 la are also similar. As shown in Fig. 11 (a), the formed N-type insulated gate The bipolar transistor 801a is connected in parallel with the N-type metal oxide tantalum transistor 801b. The collector and drain terminals of the device are connected by metallization at the bottom, and the emitter and source terminals of the device are connected by metallization at the top. In actual operation, the insulated bipolar transistor device 80 la is turned on after the N-type metal oxide tantalum transistor 8〇11), and the insulated gate bipolar is quickly turned off before the N-type metal oxide tantalum transistor 801b. The crystal device 80 la reduces the conduction damage of the synthetic semiconductor device, and the N-type metal oxide tantalum transistor 80 lb improves its turn & performance. Combining the best performance of N-type metal oxide tantalum (conversion), and the best performance of insulated gate bipolar transistor device (3⁄4 "on, under voltage drop"), synthetic semi-conducting device SMfl makes preparation - species A novel force rate device structure is possible. Fig. 12 shows a round implementation according to the invention: 3⁄4], using the 9th, a) to 9th (e) and 9th (fl) to 9th (11) A cross-sectional view of a vertical metal oxide tantalum transistor combined with a Schottky diode prepared by the process of Figure 1-3. Figure 13 shows the combined metal oxide of Figure 12. Equivalent circuit diagram of the field effect transistor and the Schottky diode. See Fig. 12, the preparation process of the N-type metal vaporized transistor 901a and the Schottky diode 901b in the semiconductor device 900, the nanotube The preparation process of the N- epitaxial layer/P- epitaxial layer is the same as that of the basic 099119030. When the transistor structure is prepared on the p-mesa structure 604, for the Schottky dinuclear form number A0101, page 34 / 123 pages lb And 201101497 言 'only formed one, some examples of the invention ❹ The Ρ+ region 625 can be prepared in the same manner as the Ρ+ body contact region 624. Although it may not be visible from Fig. 14, in this case, the depth and concentration of the Ρ+ region 625 will be the same as the ρ + body. The contact region 624 is the same. Then, using the back treatment (for example, epitaxial growth), the formation layer 661 ° Ν + layer 661 is not only used as the W-type metal oxide oxide crystal 9 〇 1 & and the drain terminal, but also as Schottky II The cathode terminal of the electrode body 9 〇 lb. The back clock metal 664 constitutes the contact electrode of the drain and cathode of the two devices. When performing the top treatment, the Schottky metal layer 6 is formed in the cell region. The base diode will also be formed in the second, then, using the top money metal 630, the source and body of the N-type metal oxide power generating crystal 9〇1 & are shorted to the anode of the Schottky diode 9〇lb Therefore, the top forged metal 630 forms the contact electrode of the source 'body and the anode of the two devices. As shown in Fig. 13, the formed N-type metal oxide (tetra) transistor 9〇la and Schottky The diodes 9 lb are connected in parallel ^ Figure 14 shows the _ according to the invention In the example, a cross-sectional view of an insulated gate bipolar transistor device combined with a PN diode is prepared by using the process shown in Figures 9(4) to 9(1). The button diagram indicates that Figure 14 does not. The equivalent circuit diagram of the integrated insulated gate bipolar transistor and the n-junction diode. See Figure 14, the preparation process of the insulated gate bipolar transistor πηπ^ρ-ν junction-pole body mlb, and the basic nano When the preparation process of the tube n_ epitaxial layer/p- epitaxial layer is the same crystal structure, for the second: structure 6 ° 4 on the preparation of electricity, " a polar body i〇oib 'only formed + anode contact area 627 « Then use the top 邛 to form the top plating and connect the insulated gate bipolar electric 099119030's emission::: extreme. Then use the back treatment, through 0993278454-0 page 35 / 123 pages, 201101497 over the ion injection, shape her layer 66 divination + layer 661 not only as the N-buffer / field layer of the insulated gate bipolar transistor 1001a, Moreover, it is a cathode terminal of the p_N junction diode i〇〇ib. A p+ layer 663 is selected to be formed in the insulated gate bipolar B cell to form the internal emitter of the insulated gate bipolar transistor device. Contact electrodes for the collector and cathode of the two devices are formed by the back mineral metal 664. Therefore, as shown in Fig. 15, the formed insulated gate bipolar transistor 1001a and the p_N junction diode 1〇〇11) are connected in parallel. Figures 16(a) and 16(b) are cross-sectional views showing an alternative processing technique for fabricating a vertical channel metal oxide tantalum field effector device in accordance with an embodiment of the present invention. Referring to the 16th U) @, after epitaxially growing the P- epitaxial layer 608 and the N- epitaxial layer 61, each of the excipients is implanted to counter-doping the N- epitaxial layer at the bottom of the trench. - Epitaxial layer. The depth of penetration of the N+ implant is indicated by a dotted circle 692. In the present embodiment, the level of the semiconductor structure is protected by the thin mask oxide layer 1180 from damage by implantation. Anisotropic N + implantation also reversely doping the N- epitaxial layer and the P- epitaxial layer on top of the mesa structure 6〇4. After annealing, a structure as shown in Fig. 16(b) is formed in which a region 1182 appears at the top of the p mesa structure 604 and at the bottom of the channel. The N+ region 1182 at the top of the mesa structure 6〇4 is removed by a chemical mechanical polishing process (CMP) prior to formation of the transistor structure. The backside of the substrate is then smoothed down to the underside of the N+ layer 1182 at the bottom of the trench, as indicated by the dashed line 1184 in the figure. The N + drain or N + field region of the device is formed by epitaxial growth. In addition, a P+ region is formed by epitaxial growth to form an internal emitter of the insulated gate bipolar transistor device. When performing the processing shown in Figures 16(a) and 16(b), you can use the back ion implantation completely, using only 099119030 Form No. A0101 Page 36/123 Page 0993278454-0 201101497 A back layer can be formed. This method of counter-doping the bottom of the channel can also be used to grow the p-mesa structure-epitaxial layer on highly doped substrates. In this case, the channel does not need to extend further onto the substrate as long as the anisotropic N+ implant passes through the bottom of the channel and spreads outward from the substrate—until the _ epitaxial nanotube is connected to the + The above-mentioned semiconductor device including the metal oxide stone MOSFET device, the insulated gate bipolar transistor device, the Schottky diode and the p_N diode can be used on the substrate. The N- epitaxial layer/p_ epitaxial layer nanotube structure described in the present invention is prepared by forming an array of electro-crystal cells. The transistor cell is either a single nanotube structure or a double nanometer structure depending on the application. The array of transistor unit cells may be a one-dimensional array or a two-dimensional array. According to an alternative embodiment of the invention, a hexagonal electro-corporeal BS cell or a square transistor cell cell is used to form electricity in a two-dimensional array. Crystal Cell® Figure 17 is a top view of a hexagonal array of electro-optic crystal cells, not according to one embodiment of the present invention. Referring to Fig. 17, a two-dimensional array of transistor cell 1201 is used to form a transistor array. The transistor cell 1200 is a hexagonal unit cell containing a pad-shaped mesa structure 12()4. Located around the P epitaxial layer 1208 and the N- epitaxial layer 1210. The N- epitaxial layer 1210 has a gate oxide layer 1216 on the outside. The channels of the transistor array 12 are all filled with a polycrystalline gate 1218. The hexagonal unit cell structure is a symmetrical unit cell structure. Figure 18 is a plan view showing an embodiment of a square-shaped electromorphic unit cell array in accordance with the present invention. Referring to Fig. 18, a two-dimensional array of transistor cells 1301 is used to form a transistor array 1 300. Transistor crystal 0993278454-0 099119030 Form No. A0101 Page 37 / 123 Page 201101497 Cell 1 300 is a hexagonal unit cell containing a P-type mesa structure 13〇4, located in the P- epitaxial layer 1308 and N-epitaxial Layer 131 around. The outside of the N_ epitaxial layer 1310 is a gate oxide layer 1316. The channels of the transistor array 13 are all filled with a polysilicon gate 1318. Cut-off structure - a power half (four) device formed on a dragon peach, such as a power metal yttria field effect tube device, which can be formed by using the above single nanotube or double nanotube tube, which is characterized by having one (four) and _ Deadline. The active region is the region where the charge balancing device is formed. The cut-off area is an area where there is no active device for insulating the active device from the physical edge of the gift circuit or the wafer and distributing the electric field along the periphery of the farm. The cut-off area ensures that the power semiconductor device obtains the charge balance, shifts the appropriate breakdown voltage, and avoids excessive device brittleness around the wafer. Only the cut-off area is properly designed, and the high-breakdown voltage is not obtained when the active and cut-off regions are verified. This is very important because of the limitations. To be more specific, the cut-off area is the highest working voltage of the integrated circuit, which is divided into smaller voltage steps, each step is smaller than the breakdown voltage of Shi Xi' and is charged in the cut-off area. (four) jump. In actual operation, the cut-off region of the N-channel device will speed up the voltage increment until the operating voltage reaches its maximum before the edge of the wafer. Another role of the cutoff region is to prevent the depletion region from reaching the edge of the wafer. If the depletion region reaches the edge of the wafer, the abrupt electric field is cut, resulting in a reduction in the breakdown voltage of the semiconductor device or a higher leakage current in the device operating at the operating voltage. FIG. 19 shows a top view of an integrated circuit (wafer) of a power semiconductor device including an active region and a cutoff region in accordance with an embodiment of the present invention. Form No. Page 38 of 123 201101497

Figure. Referring to Fig. 19, the integrated circuit 1400 includes an active region 1450 and a cutoff region 1452. Active devices such as metal oxide tantalum field effect transistors, insulated gate bipolar transistors, Schottky diodes, and p-gate junctions are all located in active region 1450. The cut-off region 1452 surrounds the active region along the physical edge of the wafer. Thus, the cutoff region 1452 isolates the active region 1450 from the physical edge of the wafer. As a complete integrated circuit, the wafer 1400 is covered by a passivation layer with openings in the passivation layer for electrical contact to the source and gate electrodes. The drain electrode (not shown) is located at the bottom of the wafer. Figure 9 shows a typical embodiment of a source metal connection and a gate metal connection. As shown in FIG. 19, the source metal and gate metal contacts are located in the active region 145 of the integrated circuit 14A and the openings in the passivation layer are used to metal the source metal tab 1454 and the gate metal tab 1456. The pad is bare. According to the aspect of the present invention, the "cut-off structure made by the method of the magnetic ring or the nanotube" is prepared for the above-described single-nanometer double-nanotube structure. Electricity

The physical edge of the road is surrounded by and surrounded by the active area of the force semiconductor device. The cut-off structure distributes the electric field in the whole marriage and the stop zone, which is beneficial to improve the breakdown voltage. In the present embodiment, the carrier structure is made of the same single nanotube or double nanotube structure as described above. "The method is to use a type of P-type and N-type area" where the first P-type area is grounded, and the middle crotch area is floating. The N_-type area is connected to the highest operating voltage of the integrated circuit. In actual work, each side-type area breaks the punch-through voltage--, driving the floating Ρ-type area to pass through the voltage of the front-side type area, so that a series of adjacent types and types can be relied on. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The N-type zone is lightly coupled to the highest cutting organization (4) The electric house gradually declines in the cut-off zone. The 29 diagram of the present invention: preparation and operation are not described in detail here, please refer to Figure 2 - According to an embodiment of the present invention, an integrated circuit including an active device is used by a double-nano-tube, and the cut-off is integrated into the integrated body f. See _, the material conductor is mounted = The integrated circuit 1 500 includes an active 550 for carrying an active device. In the present description, the active device is The device is, for example, a vertical n-type metal oxide (tetra) crystal meal, and a double-turn crystal. In the figure, the active region 155 可以 can be seen. The last _^N-type metal oxide magnetite crystal cell A gate electrode 1518, a thumb electrode ^16] N + source region 1522, and a p + body contact region 1524 are included. The N + source region 1522 and the P + body contact region 1524 are connected together to the source electrode 153. In Fig. 20, the connection line and the terminal "s" are symbolically shown. 099119030 For the n-channel device on the integrated circuit 1500, the source electrode 153 is connected to the source (or the insulated gate bipolar transistor). At the emitter's potential, the source potential is usually grounded and is the lowest potential in the integrated circuit. The Ν-type metal oxide 石 电 衬底 + substrate (not shown) is used as its drain electrode (or set) The electrode) is connected to the highest operating voltage of the integrated circuit 15 。. For the ρ_channel device in the integrated circuit, the source/emitter electrode is connected to the highest operating voltage of the integrated circuit, And the drain/collector electrode is connected to the lowest potential of the integrated circuit Usually grounded. Although this description applies only to the cut-off structure of the Ν-channel device, the working principle can be applied to the form with the channel device Α0101 Page 40 of 123 by appropriately changing the voltage polarity. The integrated circuit of 201101497.

The integrated circuit 1500 has a cut-off structure formed in the cut-off region 1552 of the integrated circuit. As shown in Fig. 20, a portion of the cutoff structure is adjacent to the source region 1550. It is known that the cut-off structure extends from the end of the active region to the edge of the wafer with the integrated circuit 1500, and only a portion of the cut-off structure can be seen in the second figure. The cutoff structure also includes an end stop cell at the edge of the wafer, as described in more detail below. In this embodiment, the cut-off structure includes a cut-off unit cell 1554 formed by the same N- epitaxial layer/p_ epitaxial layer double nanotube structure of the active device. That is to say, each of the cut-off cells is composed of a P-mesa structure layer 丨5〇4 with side walls, and p_ epitaxial layer nanotubes 1 508 and N-纟ft extended layer nanotubes 151 Covered on the side wall. In summary, the P-mesa structure layer 1 504 can be a p-mesa structure-epitaxial layer or a P-mesa structure-substrate. The cut-off structure does not use a polysilicon gate electrode, so the cut-off cell 1554 is interrupted by the oxide-filled channel 1512, in which no polycrystalline gate electrode is formed.

The cut-off cells 1554 are connected to each other to form a spring column, and the p_-type region and the n-type region are alternated in order to improve the operation of the product. More specifically, the N_ epitaxial layer nanotube is used as the N-type region, and the p_ epilayer nanotube with the p-mesa structure layer is used as the P-type region. The nanotube and P-mesa structure layers are interconnected by p- and N-type doped regions to form a series of alternating P-type regions and N-type regions. In a series arrangement of alternating P and N-type regions, the first p_-type region (p_ epitaxial layer nanotube/P-mesa structure layer) is connected to the source/emitter potential, and the last N-type region (N- epitaxial layer nanotubes) are connected to the drain/collector potential. For an N-channel device, the first P-type region is grounded, and the last N-type region is connected to the integrated circuit 15A through the N+ substrate. All other highest working voltages (not shown in Figure 20) 099119030 Form No. A0101 Page 41 / 123 Page 0993278454-0 201101497 p-type area (P_ epitaxial layer nanotube / table structure layer) are The other N-type regions in the cut-off region are connected to the substrate, but are in the sense of charge balance and potential difference. For the p__channel device, the first -^~-type region is connected to the highest of the integrated circuit. On the working electrode, the last P-type region is grounded. 099119030 Therefore, in the present embodiment, the epitaxial layer nanotubes 1 508 and the P_ mesa structure layers 15〇4 in each of the cut-off cells 1554 are electrically connected. To a lightly doped P-type doped region 156 〇 ("P_ doping region,"), the N_ epitaxial layer nanotube 1510 is electrically connected to a lightly doped __ doped region i On the 562 (u miscellaneous region), the continuous impurity cell 1 562 and the nucleus region are connected to each other through metal and joints to form a series of alternating types and N-type regions. In the example, the _ 卜 doped region 156 〇 contains -fica doped (four) 1563. Heavy doping (four) (four) 丨 (6) (four) region 1 563 are all beneficial from (four) doping The ohmic contact of the zone (5) 0, 1562 to the metal interconnect header. Different re-emphasis cores and 1563 ' can be selected and in other embodiments of the invention, P+/N+ zones 1561 and 15&3 can also be saved. The P-type region and the N-type region of the invention are formed by the P-epitope layer 15G8a and the P-mesa, and the first layer is formed to form the first cut-off unit U54a. , the mesa structure layer passes through the doping (four) 56 () and _1561, and is connected to the source electrode 1530. Therefore, the 'first epitaxial zone (the epitaxial layer of the nanotubes 15 〇 8a / P - mesa structure layer 15 〇 4a) Grounding. The n_ epitaxial layer of nanotubes 151〇a is in the P- epitaxial layer of the Nei tube 15_ and the nanotubes (with the P-mesa structure below) neighbors 'they form the first pair or phase together The adjacent p and N epitaxial layers of the nanotubes 151〇a pass through the rubbing area and the area A0101 42nd/dm

Page 42 of 123 0993278454-0 201101497

1 563, using the metal interconnection joint 1572 to connect to the "next" P- epitaxial layer nanotubes 15 〇 8b / p_ mesa structure layer 1504b 'N- epitaxial layer nanotubes 151 〇a in the next cut-off unit cell 1554b And the N-epitaxial layer tube 1510b forms a next pair of adjacent P and N regions. The P- epitaxial layer nanotube/P-mesa structure layer and the N_ epitaxial layer nanotube in the same cut-off unit continue to interconnect, forming a pair of adjacent P-type and N-type regions, which are filled by oxide The epitaxial layer nanotubes and the p_ epitaxial layer nanotube/P-mesa structure layer in the adjacent isolated cell are interconnected and continue to be connected in series to the p-type and N-type regions to form a cut-off structure:

In the embodiment shown in Fig. 20, the P-doped region 156 〇 and the [doped region 1 562 are alternately arranged in two rows to facilitate interconnection of adjacent cut-off cells. As shown in Fig. 21 and Fig. 22, 'P-epitaxial nanotube/p-mesa structure region and N are further illustrated by the cross-sectional view of the accumulating circuit along the α-, Α, line and along the B-B' line. - a series structure between epitaxial layers of nanotube regions. Referring first to Figure 21, Figure 21 shows a cross-sectional view of integrated circuit 1500 along line A-A'. Vertical N-type metal oxide germanium transistor 1565 is the last active device in active region 1 550 'cutoff ΙΪ 1552 Starting from the first cut-off unit cell 15 5 a containing the P-epitaxial layer and the P- mesa structure layer 15 0 4a, the cut-off unit cell 1554a is connected to the P-doped region 1 560 and P+ On the region 1561, the P-doped region 1560 and the P+ region 1561 are electrically connected to the source electrode 153A. Therefore, the P- epitaxial layer nanotubes 1508a and the P-mesa structure layer in the first cut-off unit cell 1554a are connected to the source potential. The N- epitaxial layer nanotubes 1510 in each of the cut-off cells 1554 are connected to the N + substrate 1502, which serves as the drain terminal of the vertical N-type metal oxide magnetite 1555, through the P- The level-direction charge balance between the mesa structure 1 504/P- epitaxial layer nanotube 1508 and the N- epitaxial layer nanotube 1510 (099119030 Form No. A0101 Page 43/123 pages 0993278454-0 201101497 and potential difference) Blocked from the drain potential in the vertical direction. The N + substrate 1 502 is connected to the highest operating voltage of the integrated circuit 1500. Therefore, all of the N- epitaxial nanotubes 1510 in the cut-off unit cell are connected to the highest operating voltage of the integrated circuit 1500. As shown in Figures 9(a) through 9(11), in other embodiments, the N+ substrate 1 502 may also be an N+ layer formed on the bottom surface of the P-mesa structure layer. Connecting the N- epitaxial layer nanotube 1510a in the first cut-off unit cell 1554a to the p- epitaxial layer nanotube tube 15〇8b in the next stem cell 1 554b is away from the P-doped region 156 〇, completed along the position of the cut-off unit cell. More specifically, the N-epitaxial nanotubes used in the cut-off unit cell 1554b

1510a is connected to the N-doped region 1562 on the p-doped region 1562, deposited along the BB line. The cross-sectional view thereof is shown in FIG. 22, see FIG. 22, the doped region 1562 of the first cut-off unit cell 1554a, Electrically connected to the doped region 1560 of the next turn-off cell 1554b by a metal interconnect connector 1572. Therefore, the N_ epitaxial layer nanotube 1 in the first cut unit cell 1554a is connected to the P- epitaxial layer nanotube 1508b/P-mesa structure layer 15〇41 of the lower cut unit cell 1554b) on. Then, the N-doped region 1562 of the cut-off unit cell 1554b is connected to the under-doped cell 156 通过 via the metal tab 1573 (Fig. 21). As shown in Fig. 21 and 22 As shown in the figure, the above series will form a long-length carrier cell, with an N_ epitaxial layer of nanotubes and an epitaxial layer of nanotubes/P-mesa structure layers connected in series in the __b epitaxial layer. a tube/p mesa structure layer (at the source/emitter potential) and a last N_ epitaxial layer nanotube (at the drain/collector potential) for the N-channel device in the integrated circuit That is, the n- epitaxial layer of the nanotube is connected to the highest operating voltage. 099119030 Form No. A0101 Page 44 / 123 Page 0993278454-0 201101497 As shown in Figure 20 - Figure 22, by adding each cut-off cell The upper voltage, the resulting cut-off structure can withstand the high voltage of the active device. More specifically, in each of the cut-off cells, the P-epitaxial nanotube/P-mesa structure layer and the N-epitaxial The layered nanotubes are pinched off at the punch-through voltage νρτ. Since the Ρ-epitaxial nanotubes and the Ρ-mesa structure are floating Therefore, the voltage of each cut-off unit cell increases in increments of the punch-through voltage νρτ until the end of the cut-off unit cell near the edge of the wafer reaches the highest operating voltage. Another way is to use the cut-off unit cell as a series of two The Ρ-mesa structure 1504 and the Ρ-epitaxial layer 1 508 of each of the cut-off cells constitute a ΡΝ diode of the same unit cell with a Ν-epitaxial layer 1510. The ΡΝ diode is in a latching mode. It is reverse biased so that it can withstand a certain voltage. The Ν portion (1510) of the diode is shorted to the Ρ portion (1 504, 1 508 ) of the next cell by a short circuit (for example, 1 572 ). Figure 23 is a graph showing the voltage characteristics of the cut-off structure in accordance with an embodiment of the present invention. Referring first to the curve 1610 in Figure 23, when the first Ρ-type region is connected to the source electrode, the voltage of the cut-off structure is from the source. The pole voltage begins. Then, the first Ν-type region is pinched off, and the punch-through voltage (νρτ) is reached in the first Ν-type region, driving the next floating Ρ-type region to also maintain the punch-through voltage (VpT). Break an N-type zone and reach another The punch-through voltage (νρτ) drives the subsequent P-type region to reach and maintain twice the punch-through voltage (2VpT). The voltage step continues to increase until the last cut-off cell at the edge of the wafer reaches the highest operating voltage (eg Fig. 23 shows the voltage characteristics of another cut-off structure, which will be described in more detail below. The punch-through voltage of the N-type region is a function of the thickness and doping level of the N-type region. Said, the punch-through voltage is N-epitaxial layer 099119030 Form No. A0101 Page 45 / Total 123 Page 0993278454-0 201101497 The thickness of the nanotube and the level of doping. Moreover, since the N- epitaxial layer of the water pipe 1510 has a uniform layer, the thickness of the port of 彳m (as shown in Fig. 21), the punch-through voltage is only the Ύ Ύ 外延 epitaxial layer The doping of the rice tube is too 嚯: function. The value of the typical punch-through voltage is a top view of the integrated circuit in the __ square, showing an alternative embodiment of the invention, a cut-off month - ββ. The interface between the active region and the first cut-off guard +. See the integrated circuit 1700 of Fig. 24, including the use of the Neibu camp structure in the active area 175 with double Μ* * , / / The source device, and the active device is made into a square unit cell. The 24th 牖 掏 ' . . figure shows the strip of the integrated circuit 1 700, wherein the cutoff region 1 752 is a ring, and the sentence 冉 L L 匕 is active Around the area 1750. The first cut-off unit cell A is more exactly a cut-off ring 1 754 that is wound and connected to the active area 1750. As with ^v, the remaining concentric cut-off rings can The voltage is pulled from the source potential at the first cut-off loop and the integrated circuit at the cut-off loop is the voltage of the k. As shown in Fig. 25. According to an alternative embodiment of the present invention, the P- epitaxial layer and the mesa structure layer are each connected to the axis, and there is no heavily doped p+ region, and N, ^, -N The epitaxial layer nanotubes are each connected to the N_ doped region, wherein there is a n-doped N+ region. As long as the P-doped region and the N-doped _ (four) ohmic touch, The (four) interconnected cut-off cell 'Fig. 25' is more purely implemented. According to another alternative embodiment of the present invention, the staggered structure formed by the staggered p and N miscellaneous regions is as shown in Fig. 26. That is, the dummy regions 1562, 1560 are not formed on the same line as shown in Fig. 2. Instead, each pair of interconnected N/P doped regions are staggered or offset from each other. Interlacing N/P doped regions, by avoiding the minimum spacing between metal joints and metal interconnects ♦, a more compact design layout can be obtained. 099119030 Page 46 of 123 Form No. ΑΟίοι « μ eu = 201101497 In an alternative embodiment of the invention, a subsurface P-type implant region is formed in the cut-off unit cell to Doping concentration of low N nanotubes. Figure 27 is a cross-sectional view showing a cut-off structure as an active device made using a double nanotube process in accordance with a third alternative embodiment of the present invention. A part of the integrated circuit. Referring to Fig. 27, the integrated circuit 1 800 includes a cut-off structure which is prepared in the same manner as the above-described 20th to 22nd. However, the cutoff in the integrated circuit 1 800 The structure also includes a P-type implant region 1 880 formed below the surface of the P-mesa structure layer 1804. In particular, the P-type implant layer 1880 is located deep below the surface area. In the present embodiment, P-doped region 1860 and N-doped region 1 862 place P-type implant region 1880 in each of the cut-off cells. In one embodiment, the P-type implant region 1880 is formed by a high energy implant that uses boron as a dopant. The P-type implant region 1 880 in each of the cut-off cells is capable of charge-compensating the N- epitaxial layer nanotube 1810 to adjust the punch-through voltage. More specifically, the effective N-type dopant concentration in the N- epitaxial nanotubes will decrease in the range of the P-type implant region 1880, so the punch-through voltage VPT is a function of the N-type dopant concentration. It will also decrease. In other words, the P-type implanted region will deplete faster and have a lower breakdown voltage than the remaining cut-off cells. The P-type implant region 1 808 will force pinch-off of the N-type and P-type regions, occurring deeper in the cut-off unit cell, away from the surface of the P-mesa structure layer 1804 where the surface charge is often non-uniform. Placing the pinch-off under the surface will result in a more uniform breakdown of the N-type and P-type regions. Turning again to Fig. 23, a curve 1612 indicates the voltage characteristics of the cutoff structure shown in Fig. 27 of the P-type implanted region 1 880 having a surface below. P-type plant 099119030 Form No. A0101 Page 47 / Total 123 Page 0993278454-0 201101497 Incoming zone 188G has the effect of the doping concentration of the drop-epitaxial nanotubes, so that each of the cut-off cells is energized. $low. As the punch-through voltage νρτ decreases, the voltage in the cut-off region grows more slowly than when the punch-through voltage is not corrected (curve 1610). Therefore, to achieve the highest operating power (for example, 600V), more voltage steps are needed (more channels are blocked). Each step is located lower, helping to break the cool off the wafer surface. The cut-off structure described in the above embodiment is formed by a double-nanostructure. In other embodiments, the cutoff structure can be made from a single nanotube configuration. Figure 28 is a cross-sectional view of a cut-off structure in accordance with a fourth alternative embodiment of the present invention, wherein the cut-off structure is part of an integrated circuit comprising an active device fabricated using a single nanotechnology process. Referring to Fig. 28, the integrated circuit 1 900 includes a cut-off structure formed in the cut-off region 1952, and the cut-off region 1952 contains the cut-off unit cell 1954, except for the preparation using only the N- epitaxial layer nanotube 191, the cut-off crystal. The other preparation methods of Cell 1 954 are the same as those shown in Figure 20. The p-doped region 196 接触 contacts the yarn of the P-mesa structure layer 19 to form a pad-shaped region of the cut-off structure. The operation of the cut-off junction wheel in the integrated circuit 1 900 is the same as that of the integrated circuit 1500 shown in Fig. 2 . The above-described cut-off structure is for gradually forming the voltage of the cut-off region of the integrated circuit with respect to the formation of the cut-off cell. At the last cut-off cell, for an N-channel device, the voltage has risen to the highest operating voltage (for p-channel devices, the voltage is reduced to ground potential). In accordance with one aspect of the invention, an end stop cell comprising a field plate is formed in the cutoff structure at the interface between the last cut cell and the edge of the wafer. Figure 29 shows a zero-cut structure 099119030 form number A0101 in accordance with an embodiment of the present invention.

0993278454-0 Page 48 of 123 201101497 A cross-sectional view of an end-cut cell in which the cut-off structure is part of an integrated circuit containing active devices fabricated using a dual nanotube process.

Referring to Fig. 29, the integrated circuit 2000 includes a cut-off structure with a series of cut-off cells, and the last cut-off cell 2〇54ζ can be seen in the figure. The cutoff structure also includes an end stop cell 2056. The end stop cell 2056 contains a wide 台-mesa structure layer 2004 ζ, polycrystalline 矽 field plates 2090 and 2091 are formed on the Ρ-mesa structure layer 2004ζ, through the dielectric layer 2096, the polycrystalline slab field plates 2〇90 and 2091 and Ρ- The mesa structure layer is 2〇〇4ζ insulated. The width f of the wide-tower structure layer 2〇〇4ζ is much larger than the width of the other ρ_ mesa structure layers. The end stop cell 205.6 also contains a final Ρ-mesa structure layer ϊ2#〇4χ on the edge of the wafer, and the scribe line is located at the edge of the wafer. The Ν-epitaxial nanotubes and the Ρ-epitaxial nanotubes are arranged next to the sidewalls of the ρ_ mesa structures 2004ζ and 2004χ. In the present embodiment, the width of the p-mesa structure layer 2004 is about 40 mm.场 Field plates 2090 and 2091 are used to carry the voltage drop across the field plate, making the N-doped region of the last turn-off cell 2054z; the voltage _ '2 is lower than the maximum operating voltage of the integrated circuit'. The cell 2056 = N- epitaxial layer nanotube 2010x is connected to the drain potential, that is, at the highest operating voltage. Field plates 2090 and 2091 are connected in series to carry excess breakdown voltage and push the electric field from the edge of the wafer back to the last cut-off cell 2〇54z. More specifically, the polysilicon field plate 2090 is electrically connected to the last cut-off cell 2〇54z through the metal interconnection joint 2092. The polysilicon field plate 2091 is electrically connected to the N-doped region 2〇62x and the N+ region 2063x through the metal interconnection head 2093'. The N- epitaxial nanotube 2010x is connected to the N+ substrate, that is, the highest operating voltage is connected and stopped as a channel. Therefore, the polysilicon field plate 2091 is biased toward the highest operating voltage. Field plates 2〇90 and 2〇91 will drive the electric field and deplete 099119030 Form No. A0101 Page 49/123 Page 0993278454-0 201101497 The area is reversed to the last cut-off unit cell. Thus, the end stop cell 2〇56 blocks the intercept structure away from the edge of the wafer. Moreover, the field plate also helps to block the excess voltage 'protecting the crucible surface from impurities and unnecessary charge buildup', relying on a more reliable charge balance at the edge to create a more powerful system. Alternatively, the field plate may be prepared from a conductive material other than polysilicon or metal. In other embodiments, only a single field plate is required or the cut-off unit cell is omitted. If the cut-off structure does not contain the end-stop cell 'the last cut-off cell 2〇54z, then only the P-doped region needs to be connected to the previous N-doped region. Since there is no further connection, the last cut-off cell 2〇54z does not require N-doped region 2062 (with or without N+ region). The above description is for explaining the exemplary embodiment of the present invention, and is not intended to limit the scope. Many modifications or variations are possible within the scope of the invention. For example, see the preparation process shown in Figures 9(a) through 9(u) for the preparation of a single nanotube instead of a double nanotube. Moreover, the preparation process shown in Figures 16(a) and 16(b) can be used to prepare a single nanotube instead of a double. Further, in the above description, the present invention (a) uses a metal oxide transistor, 峨, in an embodiment of the N+ substrate, which is a low or heavily doped N+ substrate. Bipolar transistors, Schottky diodes are prepared using either a heavily doped substrate or an extremely heavily doped N++ substrate. In addition, for the single-nano tube or the double-neck process, it is only necessary to electrically connect the N-type nanotube to the fine-type substrate. Also 099119030 is to say that the bottom is used as the starting material. The growth of the material is carried out on the basis of the plan (4) into a mesa structure, as in the 3rd (a) 3rd ('Form No. A0101 Page 50 / 123 pages 圃 201101497 and 4 (a) to 4 ( d) The preparation method shown in the figure. Under this erotic condition, the 'N-type substrate is outwardly diffused and electrically connected to the N-type nanotube. Alternatively, the substrate is used as an N-type layer through ion implantation. Or epitaxial growth, formed on the P-type mesa structure for easy back grinding, as shown in Figures 9(a) to 9(11). Form an N-type "substrate" N-type layer through the back Grinding and subsequent ion implantation or epitaxy processes are electrically connected to the N-type nanotube. The above embodiment only has a pin-channel metal oxide effect tube. However, by inverting the conductive polarity of each semiconductor region, the above-mentioned The rice tube crystal structure can also be used to prepare the P_channel metal oxide material effect tube. The above description of the preferred embodiments has been described in detail, but it should be understood that the above description should not be construed as limiting the invention. It is obvious that the scope of the invention should be limited by the scope of the appended claims.

〇 [Simple diagram description] '="V

The graph of Fig. 1 shows a cross-sectional view of a (four) straight channel metal emulsifier stone field effect sound device according to the present invention. Fig. 2 is a cross-sectional view showing a vertical channel metal oxide tantalum field effect device according to a second embodiment of the present invention. 3(a) to 3(h) are cross-sectional views showing the process of preparing a vertical channel metal oxide effect tube device as shown in Fig. 1 according to an embodiment of the present invention. 4(a) to 4(d) show an embodiment according to the present invention, as shown in Fig. 2, a vertical channel metal oxide stone MOSFET device 099119030 Form No. A0101 Page 51 / Total 123 pages 201101497 Cross-section of the preparation process. The fifth graph is not a simulation result of the electric field distribution of the nanotube drain drift region of the n-type metal oxide semiconductor transistor as shown in the 1B|throwth state. Figure 6 is a cross-sectional view showing an insulated gate bipolar crystal device in accordance with an embodiment of the present invention. Figure 6 (a) shows the circuit symbol of an insulated gate bipolar transistor device. 〇 The seventh chart is a cross-sectional view of the Schottky diode. Figure 7 (a) shows the circuit symbol of a Schottky diode. Fig. 8 is a cross-sectional view showing an embodiment of an apparatus according to the present invention, a type of junction type diode. Figure 8(a) shows the circuit symbol of a P-N junction diode. 9(a) to 9(k) are diagrams showing an alternate embodiment of a vertical channel metal oxide tantalum field effect device and an insulated gate bipolar transistor device in accordance with an alternative embodiment of the present invention Sectional view. 9(fl) to 9(11) are views showing a cross section of a vertical channel metal oxide tantalum field effect device and an insulated gate bipolar transistor device according to an alternative embodiment of the present invention. Figure. Figure 10 is a diagram showing the vertical N-type metal oxidation of an integrated N-type insulated gate bipolar transistor using the process shown in Figures g(a) through 9(k) in accordance with one embodiment of the present invention. A cross-sectional view of the material field effect tube device. Figure 11 (a) shows an equivalent circuit diagram of the integrated metal oxide stone field effect transistor and the insulated gate bipolar transistor device as shown in Fig. 10. 099119030 Form No. A0101 Page 52 of 123 0993278454-0 201101497 Figure 11 (b) shows the operation time of the metal oxide tantalum field effect transistor and the insulated gate bipolar transistor device as shown in Figure 11 (a) table. Figure 12 is a diagram showing an integrated Schott prepared by the processes shown in Figures 9(a) through 9(e) and 9(fl) through 9(11) in accordance with one embodiment of the present invention. A cross-sectional view of a vertical N-type metal oxide tantalum transistor of a base diode. Fig. 13 is a view showing an equivalent circuit diagram of the integrated metal oxide tantalum field effect transistor and the 宵-based diode as shown in Fig. 12. 0 is a cross-sectional view showing an insulated gate bipolar transistor device of an integrated p_N type dipole fabricated by the processes shown in the 9th (&) to 9th (k) diagrams according to an embodiment of the present invention. Figure. ϊ Fig. 15 shows an equivalent circuit diagram of the base-insulated gate bipolar transistor and the P-N junction diode as shown in Fig. 14. Figures 16(a) through 16(b) illustrate an alternative process for fabricating a vertical channel metal oxide tantalum field effector device in accordance with one embodiment of the present invention. .? V: ,

Figure 17 shows a top view of a hexagonal array of cell crystal cells in accordance with one embodiment of the present invention. Figure 18 is a top plan view of a square transistor cell array in accordance with one embodiment of the present invention. Figure 19 is a plan view of an integrated circuit (wafer) of a power semiconductor device including an active region and a cutoff region, in accordance with an embodiment of the present invention. The 20th chart is not a top view of a cutoff structure in accordance with an embodiment of the present invention, wherein the cutoff structure is part of an integrated circuit including an active device fabricated using a double nanotube process. 099119030 Form No. A0101 Page 53 of 123 0993278454-0 201101497 Figure 21 shows a cross-sectional view of the cut-off structure taken along line A-A' as shown in Fig. 20, in accordance with an embodiment of the present invention. Figure 22 is a cross-sectional view of the cutoff structure shown in Fig. 20 taken along the line B-B' in accordance with an embodiment of the present invention. Figure 23 is a graph showing the relationship between the voltage and the cut-off cell properties of the cutoff structure in accordance with one embodiment of the present invention. Figure 24 is a top plan view of an integrated circuit showing the interface between the active region of the cutoff structure and the first termination ring in accordance with an alternative embodiment of the present invention. Figure 25 is a plan view showing a cut-off structure as a part of an integrated circuit including an active device fabricated using a double nanotube process in accordance with a first alternative embodiment of the present invention. Figure 26 is a cross-sectional view showing a cut-off structure as a part of an integrated circuit including an active device fabricated using a double nanotube process in accordance with a second alternative embodiment of the present invention. Figure 27 is a cross-sectional view showing a cut-off structure as a part of an integrated circuit including an active device fabricated using a double nanotube process in accordance with a third alternative embodiment of the present invention. Figure 28 is a cross-sectional view showing a cut-off structure as a part of an integrated circuit including an active device fabricated using a single nanotube process in accordance with a fourth alternative embodiment of the present invention. Figure 29 is a cross-sectional view showing an end stop cell of a cutoff structure as part of an integrated circuit containing an active device fabricated using a double nanotube process, in accordance with one embodiment of the present invention. [Main component symbol description] [0006] 200 N-type vertical channel metal oxide tantalum field effect device 099119030 Form No. A0101 Page 54 / 123 Page 0993278454-0 201101497 118, 218, 318 Polysilicon gate electrode 116, 216, 1216, 1316, 1516 gate oxide layers 112, 212, 312, 606, 1512 channels 110, 210, 310'410, 510, 610, 1210, 1310 thin germanium-type epitaxial layers 208, 308, 408, 608 1, 208, 1308 thin germanium-type epitaxial layer 202 Ν ++ basic bottom Ο 104, 204, 304, 404, 504 Ρ - mesa structure - epitaxial layer 120, 220, 320, 620 Ρ - body region 230 source electrode 124 , 224, 624, 1 524 Ρ + body contact regions 122, 222, 322, 622, 1 522 Ν + source region 226 dielectric layer 102, 202 Ν + + substrate 113, 213 oxide layer 114, 214, 692 dotted line ❹ 126, 226 deposition medium layer BPSG borosilicate layer 550 with electric field along the length of the nanotube drift drift line 552 electric field distribution line in the Ρ-mesa structure epitaxial layer 5 5 4 Crystalline gate and oxide filled channel direction distribution 300, 680, 780, IGBT insulated gate bipolar Crystal device 330, 334, 630 metal layer 326, 626 bismuth glass 316, 616 containing boric acid Gate dielectric 099119030 Form number Α 0101 Page 55 / 123 page 0993278454-0 201101497 302 N-type buffer layer 332 P + internal emitter region 400 Schottky diode 440, 442, 542 metal layer 446 Schottky junction 424, 520, 627 shallow P + anode contact region 438 shallow P-doped region 402, 502, 1 502 N + substrate 500 PN junction diode Body 540 ohm metal layer 546 PN junction 604 P-type single crystal germanium substrate 612 cerium oxide 618 polycrystalline germanium layer 600 oxide germanium transistor 660 N + doped layer 664 bottom metallization 662 P + doped layer 661 N + layer 663 P+ layer 800, 900 semiconductor device 801b, 1 555 vertical N-type metal oxide germanium transistor 801a, 1001a insulated gate bipolar transistor device MOSFET metal oxide field effect transistor 901b Schottky diode 901a N-type metal oxide矽Electrical Crystal 099119030 Form No. A0101 Page 56 / Total 123 Page 0993278454-0 201101497 1001b PN junction diode 604, 1204, 1304, 1504, 1504a, 1504b, 1804 P-mesa structure 1180 Thin mask oxide layer 1182, 1563 N+ zone 118 4 dotted line 1 200, 1 300 transistor array 1201 > 1301 transistor cell ❹ 1218, 1318, 1518 polysilicon gate 1400 wafer 1452, 1552, 1752, 1952 wearing area 1454 source metal joint 1456 gate metal joint 1450 , 1550, 1 750 active area 1 500 active semiconductor device integrated circuit 1 5 3 0 source electrode Ο 1 560, 1860 P-doped region 1 562, 1862 N-doped region 1561 P + region 1573 metal connector 1572 metal interconnect connector 1554 ' 1554a ' 1554b cut-off cell 1 508, 1 508a, 1 508b, 1810 P- epitaxial nanotubes 1510, 1510a, 1510b, 1910 N- epilayer nanotube νρτ punch-through voltage 1612 curve 099119030 0993278454 -0 Form No. A0101 Page 57 / Total 123 Page 201101497 1 700, 1 800, 1 900 Integrated Circuit 1 754 Cut-Off Ring 1 880, 1 808 P-Type Implant Area 099119030 Form No. A0101 Page 58 of 123

0993278454-0

Claims (1)

201101497 VII. Patent application scope: A semiconductor device, characterized in that: the semiconductor device comprises: a first semiconductor layer comprising a plurality of formed in a dicing channel, wherein the lining is formed in a 台-semiconductor layer fI; a second bottom surface of the second conductivity type; the + lead is located in the di-semiconductor layer, and the first epitaxial layer of the first conductivity type is formed on the sidewall of the trench to cover the first layer a sidewall of the mesa structure in the semiconductor layer; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the first epitaxial layer # is connected to the second semiconducting layer; the first medium in the dip a layer 'directly adjacent to the second epitaxial layer, the L, the first; the enamel layer filling at least a portion of the channel; 2 forming a gate dielectric layer on the sidewall of the at least one first channel above the first dielectric layer; a gate-conducting layer in the first-channel of the gate dielectric layer on the first-fourth (four) and the second-stage epitaxial layer, and the sidewalls of the second epitaxial layer and the second epitaxial layer a parallel doped 2'-th epitaxial layer and The second epitaxial layer each has a uniform sentence Holding the second impurity layer, the second epitaxial layer has a first thickness and a first doping concentration, and the mesa structures of the first epitaxial layer and the first semiconductor layer each have a second thickness and a second translational mismatch, #〇第The second thickness and the first and second average doping concentrations achieve charge balance. 2. The semiconductor device according to claim 1, wherein the second semiconductor layer is made of an extremely heavily doped semiconductor layer or weight 099119030 Form No. A0101 Page 59 of 123 0993278454-0 201101497 A doped semiconductor layer is formed, the first semiconductor layer being a lightly doped epitaxial layer of a first conductivity type. 3. The semiconductor device according to claim 1, wherein the first semiconductor layer is composed of a lightly doped semiconductor substrate of a first conductivity type, and the second semiconductor layer is implanted. The layer or epitaxial layer is formed on the bottom surface of the first semiconductor layer after back grinding the first semiconductor layer. 4. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: a body region of a first conductivity type formed on top of at least one first mesa structure of the first semiconductor layer a body region extending to a depth near a bottom edge of the gate conductive layer in the first channel; and a heavily doped source region of the second conductivity type formed in the body region proximate the sidewall of the first channel, a source region extending from above the first semiconductor layer to a depth near a top edge of the gate conductive layer; and a vertical channel metal ytterbium oxide field effect transistor formed therein, the second semiconductor layer being a vertical channel A semiconductor device according to the first aspect of the invention, wherein the semiconductor device of the first aspect of the invention is characterized in that: The thickness of the second epitaxial layer is about 10 nm, and the thickness of the first epitaxial layer is about 250 nm. 6. The semiconductor device according to claim 1, wherein the first epitaxial layer has a larger doping concentration than the first semiconductor layer. 7. The semiconductor device according to claim 1, wherein the product of the first thickness of the second epitaxial layer and the first doping concentration is substantially 099119030. Form number A0101 page 60/123 page 0993278454 -0 201101497 is equal to - half of the product of the second average doping concentration of the mesa structure of the first epitaxial layer and the first semiconductor layer. The semiconductor device according to claim 1, wherein the first conductivity type is composed of a Ν-type conductivity type, and the first conductivity type is formed. ! The semiconductor device according to claim i, wherein the first conductivity type is composed of a P-type conductivity type, and the second conductivity type is composed of an N-type conductivity type.疋 Ο A semiconductor device according to the invention of claim 1, wherein the bottom region of the channel is counter-doped such that the second epitaxial layer is electrically connected to the second semiconductor layer at the bottom region of the channel. 11. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: a body of a first conductivity type at the top of at least one of the first mesa structures of the first semiconductor layer a region 'the body region extending to a depth near a bottom edge of the gate conductive layer in the first channel; forming a second type of heavily doped source region in the body region adjacent to the sidewall of the first channel, the a source 卩 类 类 类 的 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; An internal emitter region, and a collector electrically connected to the third semiconductor layer, wherein an insulated gate bipolar transistor is formed, and the second semiconductor layer serves as a buffer or field column for the shirt-enhanced thumb bipolar transistor The area 'body area as the internal voltage 0993278454-0 pole area 'source electrode as the emitter electrode pole form number delete 1 ^ 61 I / * 123 w material for the gate electricity 201101497 pole 0 12 . If the patent application scope 1 The half The conductor device, further comprising: an anode contact region of a first conductivity type formed in a second mesa structure of the first semiconductor layer, the second mesa structure being in close proximity with or without a gate conduction a channel filled with a first dielectric layer of the layer; and a Schottky metal layer formed on a top surface of the first semiconductor layer, the Schottky metal connecting the first and second epitaxial layers and the anode contact region, Schottky The metal is connected to the second epitaxial layer to form a Schottky junction in which a Schottky diode is formed, the second semiconductor layer serves as a cathode, and the Schottky metal layer serves as an anode terminal. The semiconductor device of claim 12, wherein the semiconductor device further comprises: a lightly doped first conductivity type formed on a top surface of the second mesa structure of the first semiconductor layer a shallow implant region surrounding the anode contact region, the lightly doped region extending over the entire surface of the second mesa structure, including first and second epitaxial layers, the doping concentration of the lightly doped implant region is greater than the anode contact region smaller. 14. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: an anode contact region of a first conductivity type formed in a third mesa structure of the first semiconductor layer, An anode contact region and extending to a second epitaxial layer formed on a sidewall of the third mesa structure, the third mesa structure being in close proximity to a channel filled with a first dielectric layer with or without a gate conductive layer, a PN junction being located Between the anode contact region and the second epitaxial layer; and an ohmic metal layer on the top surface of the third mesa structure, in electrical contact with the anode contact region, 099119030 Form No. A0101 Page 62 / Total 123 Page 0993278454-0 201101497 Where The formed P-Ν junction diode has a second semiconductor layer as a cathode and an ohmic metal layer as an anode terminal. 15. The semiconductor device of claim 1, wherein the semiconductor device is formed by an active region carrying an active device and a cut-off region around the active region, the cut-off region including a cut-off region The cell array, from the first cut-off cell that intersects the active region, to the last turn-off cell, wherein each of the turn-off cells contains: a mesa structure of a first semiconductor layer having a first epitaxial layer formed on a sidewall thereof and a second epitaxial layer formed on the first epitaxial layer, the mesa structure being located in a trench filled with the first dielectric layer instead of the gate conductive layer a channel neighbor; a first region of a first conductivity type formed in a top surface of the mesa structure is electrically connected to the first epitaxial layer and the first semiconductor layer; and a first region formed on the top surface of the mesa structure a second region of the type: electrically connected to the second epitaxial layer, the second region being away from the first region in the mesa structure, and formed in each of the cut-off cells except the last one of the cut-off cells, wherein the first one is cut off The first cell of the unit cell is electrically connected to the source or emitter potential of the semiconductor device, and the last multi-printed cell is electrically connected to the drain or collector of the semiconductor device. Or the vicinity of the collector potential, the second regions of the remaining cut-off cells are electrically connected to the first region of the next one of the cut-off cells in the array. 16. The semiconductor device according to claim 15 is characterized in that Wherein each of the cut-off cells further comprises: a third region of a first conductivity type formed in the first region, the doping concentration of the third region is greater than the first region; and one is formed in the second region The fourth region of the second conductivity type, the doping concentration of the fourth region is greater than that of the second region. 099119030 Form No. A0101 Page 63 / Total 123 Page 0993278454-0 201101497 17 as described in claim 15 The semiconductor device is characterized in that each of the cut-off cells is pinched off at a punch-through voltage, and the array of the cut-off cells will cut off the voltage of the region, in the step of the punch-through voltage, from the lowest potential to the highest The semiconductor device according to claim 15, wherein the first region and the second region of one of the cut-off cells are staggered with the first region and the second region of the next cut-off unit cell. The semiconductor device of claim 15, wherein each of the cut-off cells further comprises: an implant region having a first conductivity type dopant formed in the mesa structure, The doping concentration of the implanted region is used to adjust the doping concentration of the second epitaxial layer to reduce the punch-through voltage of the cut-off cell. 20. The semiconductor device according to claim 19, The invention is characterized in that the implanted region is formed in the mesa structure, below the bottom surface of the first or second region. The semiconductor device according to claim 15, wherein the cut-off region is further ordered An end-cut cell formed in the vicinity of the last one of the cut-off cells, the end-off cell comprising: a terminal mesa structure of the first semiconductor layer, having a first epitaxial layer formed on the sidewall thereof and forming the first epitaxial layer a second epitaxial layer on the layer, the end mesa structure being located adjacent to the channel filled with the first epitaxial layer, rather than the gate conductive layer, the first width of the end mesa structure being greater than the width of the mesa structure of the other off cell And at least one field plate on the top surface of the end mesa structure, insulated from the end mesa structure by the dielectric layer, wherein the last cut cell further comprises a shape In the top surface of the mesa structure, and 099119030, the form number A0101, page 64 / 123 pages 0993278454-0 201101497 is electrically connected to the second region of the second conductivity type on the second epitaxial layer, the second region being away from the mesa structure a first region, and wherein at least one of the field plates is coupled between a second region of the last off cell and a drain or collector potential of the semiconductor device. The semiconductor device according to claim 21, wherein the at least one field plate of the end-cut cell comprises: a first field plate on a top surface of the end mesa structure, through the dielectric layer and the end mesa Structural insulation; and 第二 a second field plate on the top surface of the end mesa structure, insulated from the end mesa structure by the dielectric layer, the second field plate being adjacent to the first field plate, wherein the first and second field plates are connected in series at the end a semiconductor device between the source region of the cell and the drain or collector potential of the semiconductor device. A semiconductor device comprising: a first semiconductor layer of a first conductivity type, comprising: a plurality of channels in a top surface of the first half of the germanium conductor layer, the channels forming a mesa structure in the first semiconductor layer; and f - a second semiconductor layer of the second conductivity type on the bottom surface of the first semiconductor layer a second epitaxial layer of a second conductivity type formed on the sidewall of the trench covering at least a sidewall of the mesa structure of the first semiconductor layer; a first dielectric layer adjacent to the second epitaxial layer, the first dielectric layer filling at least a portion of the trench; a gate dielectric layer formed on at least one of the first trench sidewalls above the first dielectric layer; And a gate conductive layer formed in the upper trace of the first dielectric layer, and a first trench adjacent to the gate dielectric layer. 099119030 Form No. A0101 Page 65 / 123 Page 0993278454-0 201101497 Wherein the second epitaxial layer is along the channel The sidewall forms a parallel doped region, the second epitaxial layer has a uniform doping concentration, the second epitaxial layer has a first thickness and a first doping concentration, and the mesa structure of the first semiconductor layer has a second thickness and a second Doping concentration, selecting suitable first and second thicknesses, and first doping concentration and second doping concentration to obtain charge balance; and wherein said semiconductor device is an active region carrying an active device and A cut-off region around an active region, the cut-off region includes an array of cut-off cells, from the first cut-off cell to the active region, until the last load a cell, each of which has a mesa structure of a first semiconductor layer having a second epitaxial layer formed on a sidewall thereof, wherein the mesa structure is filled with a first dielectric layer instead of a gate conductive layer a channel adjacent; a first region of a first conductivity type formed in a top surface of the mesa structure electrically connected to the first semiconductor layer; and a second region of a second conductivity type formed in a top surface of the mesa structure, Electrically connected to the second epitaxial layer, the second region being away from the first region in the mesa structure, and formed in each of the cut-off unit cells except the last one of the cut-off cells, wherein the first region of the first cut-off unit cell Electrically connected to the source or emitter potential of the semiconductor device, the second epitaxial layer of the last turn-off cell is electrically connected to the drain or collector potential of the semiconductor device, or near the drain or collector potential, and the remaining cutoff The second region of the unit cell is electrically connected to the first region of its next cut-off unit cell in the array, respectively. 24. A method of fabricating a semiconductor device, the method comprising: forming a plurality of channels on a top surface of a first semiconductor layer of a first conductivity type, the channels forming a mesa in the first semiconductor layer Structure; forming a second conductive material on the surface of the first semiconductor layer by epitaxial growth 099119030 Form No. A0101 Page 66 / 123 page 0993278454-0 201101497 Type first epitaxial layer covering at least the sidewall of the channel; Forming a first dielectric layer, wherein the first dielectric layer is filled with at least a portion of the channel; forming a gate dielectric layer over the first dielectric layer and adjacent to sidewalls of the at least one first trench of the first epitaxial layer; Forming a gate conductive layer in the first channel, wherein the gate conductive layer is above the first dielectric layer and adjacent to the gate dielectric layer; and on the bottom surface of the first semiconductor layer, preparing a second semiconductor layer of the second conductivity type Wherein the first epitaxial layer is electrically connected to the second semiconductor layer, wherein the first epitaxial layer is arranged along the sidewall of the trench, and Having a uniform doping concentration, the first epitaxial layer has a first thickness and a first doping concentration, and the mesa structure of the first semiconductor layer has a second thickness and a second doping concentration in the horizontal direction, and a suitable first sum is selected The second thickness and the first and second doping concentrations are such that charge balance is achieved in actual operation. The method of fabricating a semiconductor device according to claim 24, wherein the second semiconductor layer of the second conductivity type comprises a heavily doped semiconductor substrate of a second conductivity type, and is formed Prior to the plurality of channels, the method further comprises: preparing a heavily doped semiconductor substrate of a second conductivity type; and preparing a first semiconductor layer of the first conductivity type on a top surface of the semiconductor substrate. The method of fabricating a semiconductor device according to claim 24, wherein the first semiconductor layer of the first conductivity type is a lightly doped semiconductor substrate, and after the gate conductive layer is prepared, The method further comprises: grinding the back of the lightly doped semiconductor substrate, removing the semiconductor substrate until 099119030 Form No. A0101 Page 67 / 123 Page 0993278454-0 201101497 27 28 · 29 . 30 . 31 . 32 , 099119030 Near the bottom surface of the channel; and on the back of the barely doped semiconductor substrate, a second semiconductor layer of the second conductivity type is prepared, the second semiconductor layer being heavily doped. The method of fabricating a semiconductor device according to claim 26, wherein the preparing the second heavily doped semiconductor layer comprises: performing a second conductivity type on the back of the barely lightly doped semiconductor substrate injection. The method for fabricating a semiconductor device according to claim 26, wherein the polishing the lightly doped semiconductor substrate back further comprises: grinding the back of the semiconductor substrate, removing the semiconductor substrate until the first dielectric layer Up to the bottom. The method for fabricating a semiconductor device according to claim 26, wherein the second conductive layer of the second conductive germanium is prepared by: On the back of the bare lightly doped semiconductor substrate, a heavily doped second semiconductor layer of a second conductivity type is epitaxially grown. A method of fabricating a semiconductor device according to claim 29, wherein the back of the lightly doped semiconductor substrate is polished to remove the semiconductor substrate until a distance away from the bottom surface of the trench filled with the dielectric. The method for fabricating a semiconductor device according to claim 24, wherein the method further comprises: performing an anisotropic ion implantation of the second conductivity type before preparing the first dielectric layer in the channel, A heterogeneous ion implantation forms a doped region of the second conductivity type at the bottom of the channel. The method of fabricating a semiconductor device according to claim 24, wherein the method further comprises: preparing a body region of a first conductivity type on top of the mesa structure of the at least one first semiconductor layer, the body The gate extends to the first channel in the gate form number A0101 page 68 / 123 pages 0993278454-0 201101497 33 . Ο 34 . Ο 35 . 36 . 37 . The depth near the bottom edge of the conductive layer; in close proximity to the first channel In the body region of the sidewall, a heavily doped source region of a second conductivity type is formed, the source region extending to a depth near a top edge of the gate conductive layer; and a vertical channel metal yttrium oxide field is prepared therein The effect transistor, the second semiconductor layer serves as a drain region of the vertical channel metal ytterbium oxide field effect transistor, the first epitaxial layer serves as a drain drift region, and the gate conductive layer functions as a gate electrode. The method of fabricating a semiconductor device according to claim 32, further comprising: preparing a second dielectric layer on top of the first semiconductor layer over the gate conductive layer and the first semiconductor layer An opening is formed in the second dielectric layer on the surface; and a source electrode is prepared in the opening to connect the source region and the body region. The method for fabricating a semiconductor device according to claim 24, wherein the first epitaxial layer of the second conductivity type is prepared by epitaxial growth, comprising: preparing a thickness equal to or less than 200 nm by epitaxial growth A first epitaxial layer of two conductivity types. The method of fabricating a semiconductor device according to claim 24, wherein the preparing the first dielectric layer in the trench comprises: depositing an oxide layer in the trench, and depositing the oxide layer to fill the trench, And covering the mesa structure of the first semiconductor layer; and etching the deposited oxide layer until the oxide layer fills only a part of the channel. The method of fabricating a semiconductor device according to claim 24, wherein the first semiconductor layer has a smaller doping concentration than the first epitaxial layer. The method for fabricating a semiconductor device according to claim 24, wherein the method of the first epitaxial layer and the first doping concentration is characterized by a 099119030 form number A0101 page 69/123 page 0993278454-0 201101497 The product is substantially equal to half the product of the second thickness of the mesa structure of the first semiconductor layer and the second doping concentration, the second thickness being a level dimension of the mesa structure of the first semiconductor layer. 38. The method of fabricating a semiconductor device according to claim 24, wherein before the first epitaxial layer of the second conductivity type is prepared by epitaxial growth, the method further comprises: by epitaxial growth, at the first Preparing a second epitaxial layer of a first conductivity type on the semiconductor layer, the second epitaxial layer covering the sidewall of the trench; wherein, by epitaxial growth, the step of preparing the first epitaxial layer comprises: by epitaxial growth, at the second epitaxy Forming a first epitaxial layer of a second conductivity type on the layer, wherein the first epitaxial layer and the second epitaxial layer form a parallel doped region along the sidewall of the trench, and the first epitaxial layer and the second epitaxial layer are respectively uniform a doping concentration, the first epitaxial layer has a first thickness of a private first doping concentration, and the second epitaxial layer and a mesa structure of the first semiconductor layer each have a third thickness and a third average doping concentration, and a suitable first The first and third thicknesses and the first doping concentration and the third average doping concentration are used to obtain a charge balance. 39. A method of fabricating a semiconductor device according to claim 38, wherein the second semiconductor layer of the second conductivity type is composed of a heavily doped semiconductor substrate of a second conductivity type, wherein Before preparing the plurality of channels, the method further comprises: preparing a heavily doped semiconductor substrate of a second conductivity type; and preparing a first semiconductor layer 5 of a first conductivity type on a top surface of the semiconductor substrate, wherein The first epitaxial layer on the second epitaxial layer is externally diffused and electrically connected to the semiconductor substrate through a semiconductor liner 099119030 Form No. A0101, page 70 / 123 pages 0993278454-0 201101497. 40. A method of fabricating a semiconductor device according to claim 38, wherein the second epitaxial layer has a larger doping concentration than the first semiconductor layer. The method of fabricating a semiconductor device according to claim 38, characterized in that the product of the first thickness of the first epitaxial layer and the first doping concentration is substantially equal to the second epitaxial layer and the first semiconductor layer. The third thickness of the mesa structure is half the product of the third average doping concentration. The method of fabricating a semiconductor device according to claim 24, wherein the first conductivity type is composed of an N-type conductivity type, and the second conductivity type is composed of a P-type conductivity type. The method of fabricating a semiconductor device according to claim 24, wherein the first conductivity type is composed of a P-type conductivity type, and the second conductivity type is composed of an N-type conductivity type. The method of producing a semiconductor device according to claim 24, wherein the process after the epitaxial process is carried out at a temperature of 1 000 ° C or less. The method of fabricating a semiconductor device according to claim 38, characterized in that the bottom region of the channel is counter-doped such that the first epitaxial layer is electrically connected to the second semiconductor layer. The method of fabricating a semiconductor device according to claim 24, further comprising: preparing a body region of a first conductivity type on top of at least one first mesa structure of the first semiconductor layer, The body region extends to a depth near a bottom edge of the gate conductive layer in the first channel; in a body region adjacent to the sidewall of the first channel, a heavily doped source region of the second conductivity type is prepared, the source The region extends to the top edge of the gate conductive layer 099119030 Form No. A0101 Page 71 / 123 Page 0993278454-0 201101497 The depth near; Prepare a source electrode on the top surface to electrically contact the source region and the body region in the second Preparing an internal emitter layer of a first conductivity type on a bottom surface of the semiconductor layer; and preparing a collector electrode on the bottom surface to connect the internal emitter layer, wherein an insulated gate bipolar transistor is formed, and the second semiconductor layer is used as a second semiconductor layer The buffer or field block of the insulated gate bipolar transistor, the body region acts as the inner collector region * the source electrode serves as the emitter electrode 'the thumb The method of manufacturing the semiconductor device according to claim 24, further comprising: preparing the first conductivity type in the second mesa structure of the first semiconductor layer An anode contact region, a second mesa structure adjacent to the channel filled with the first dielectric layer with or without the gate conductive layer; and a top surface of the second mesa structure and the first epitaxial layer and the anode contact region, Preparing a Schottky metal layer, the Schottky metal is connected to the first epitaxial layer to form a Schottky junction. A Schottky diode formed therein has a second semiconductor layer, and the second semiconductor layer serves as a cathode. The terminal, the Schottky metal layer serves as an anode terminal. The method of fabricating a semiconductor device according to claim 24, further comprising: performing shallow implanting of the first conductivity type in the first epitaxial layer to adjust the first epitaxial layer The height of the special barrier. 49. The method for fabricating a semiconductor device according to claim 24, further comprising: 099119030 Form No. A0101, page 72/123, 0993278454-0 201101497 In the third mesa structure of the first semiconductor layer, prepare a An anode contact region of a first conductivity type and extending to a first epitaxial layer formed on a sidewall of the third mesa structure, the third mesa structure being located in a trench filled by the first dielectric layer with or without a gate conductive layer a PN junction is formed between the anode contact region and the first epitaxial layer; and an ohmic metal layer is formed on the top surface of the third mesa structure to be in electrical contact with the anode contact region; a PN junction formed therein The polar body has a second semiconductor layer, the second semiconductor layer serves as a cathode terminal, and the ohmic metal layer serves as an anode terminal. 0993278454-0 099119030 Form Number A0101 Page 73 of 123