CN108346701B - Shielding gate power DMOS device - Google Patents
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- CN108346701B CN108346701B CN201810326836.9A CN201810326836A CN108346701B CN 108346701 B CN108346701 B CN 108346701B CN 201810326836 A CN201810326836 A CN 201810326836A CN 108346701 B CN108346701 B CN 108346701B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 170
- 210000000746 body region Anatomy 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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Abstract
一种屏蔽栅功率DMOS器件，属于半导体功率器件技术领域。本发明基于传统屏蔽栅DMOS器件进行改进，器件两侧的沟槽栅结构之间的漂移区顶层具有体区，在体区的顶层具有交替排列的源区和接触区，通过合理设置源区和接触区的交替排列方向并且在接触区和沟槽的侧壁之间引入重掺杂的电流引导层形成导通电阻较低的电流通道，而使源区和沟槽侧壁的介质层直接接触。这样设计能够将雪崩击穿电流固定于电流引导层中，并引导雪崩电流直接经由电流引导层从接触区流走而不经过源区下方的体区，这样就防止了寄生BJT的开启，提升了器件的UIS耐量及抗UIS失效能力。另外，由于屏蔽栅电极的横向耗尽作用，能够避免电流引导层对于器件耐压性能的负面影响。
A shielded gate power DMOS device belongs to the technical field of semiconductor power devices. The invention is improved based on the traditional shielded gate DMOS device. The top layer of the drift region between the trench gate structures on both sides of the device has a body region, and the top layer of the body region has alternately arranged source regions and contact regions. Alternate arrangement of the contact regions and the introduction of a heavily doped current guide layer between the contact region and the sidewall of the trench to form a current channel with lower on-resistance, and direct contact between the source region and the dielectric layer on the sidewall of the trench . This design can fix the avalanche breakdown current in the current guide layer and guide the avalanche current to flow away from the contact area directly through the current guide layer without passing through the body area under the source area, thus preventing the parasitic BJT from turning on and improving the The UIS tolerance of the device and the ability to resist UIS failure. In addition, due to the lateral depletion effect of the shielded gate electrode, the negative influence of the current guiding layer on the withstand voltage performance of the device can be avoided.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a shielded gate power DMOS device.
Background
The power DMOS has the advantages of high switching speed, low loss, high input impedance, low driving power, good frequency characteristic and the like, and plays an important role in the field of power conversion. The ever-increasing system performance requires that the power DMOS have higher reliability under high electrical stress while having lower power loss. In order to improve the performance of DMOS, new structures such as floating island unipolar devices and shielded gate (Split-gate) have been proposed. Floating island unipolar device pass through at N-The P-type voltage division island is added in the epitaxial layer, so that the maximum electric field of the drift region is divided into two parts, and the breakdown voltage is improved under the same epitaxial layer doping concentration; the power DMOS of the shielding grid isThe first polycrystalline layer is used as an 'in-vivo field plate' to reduce the electric field of the drift region, and higher breakdown voltage is obtained. Shielded gate power DMOS have lower on-resistance and higher breakdown voltage than floating island unipolar devices.
Switching process under Unclamped Inductive Switching (UIS) is generally considered to be the most extreme electrical stress situation that power DMOS can face in an application. Therefore, the UIS failure resistance of the device is often used for evaluating the reliability of the power DMOS, and the UIS tolerance is an important parameter for measuring the UIS failure resistance of the power DMOS. The turning on of a parasitic BJT (Bipolar Junction Transistor) is one of the important causes of UIS failure. Failure of the UIS is generally considered to be the "active" mode of the device, since the parasitic BJT between the source and drain is turned on during the UIS avalanche, and the large current flowing through the body after conduction will rapidly heat up the device, damaging the device. Fig. 1 shows a schematic structural diagram of a conventional N-channel shielded gate power DMOS device, in which an N + source region of the device serves as an emitter region of a parasitic BJT, an N-drift region constitutes a collector region of the parasitic BJT, and a P-body region serves as a base region. When the power DMOS device is subjected to avalanche breakdown, avalanche current reaches a P + contact region through a P-body region below an N + source region, and the avalanche current flows through a base region of a parasitic BJT, forward voltage drop is inevitably generated due to resistance of the P-body region, and when the voltage drop is larger than the forward conduction voltage drop of the parasitic BJT, an emitter of the parasitic BJT is positively biased and enters a forward amplification working region to amplify the avalanche current, so that the device is thermally burnt. As the physical level failure mechanism makes it clear that the conduction of the parasitic BJT allows for thermal breakdown, it is generally desirable to improve the internal structure of the device to suppress the conduction of the parasitic BJT.
The current industry approach to improving the UIS failure resistance of a shielded gate power DMOS device is similar to that of a conventional power DMOS device, primarily by reducing the base resistance of the parasitic BJT to inhibit its turn-on. However, this method cannot prevent the parasitic BJT from being turned on, and thus cannot avoid the active failure mode of the device UIS caused by avalanche breakdown; in addition, the base resistance can only be reduced to a certain extent by high-energy boron implantation or deep diffusion, and the base resistance of the parasitic BJT cannot be infinitely reduced, otherwise the threshold voltage of the power DMOS device is increased.
Disclosure of Invention
In view of the above, the present invention aims to: provided is a shielded gate power DMOS device capable of preventing a parasitic BJT inside the device from being turned on and having a high capability of resisting UIS failure.
In order to achieve the above purpose, the invention provides the following technical scheme:
the first technical scheme is as follows:
a shielded gate power DMOS device, the cell structure of which comprises: the structure comprises a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor drift region 3 and a metalized source 12 which are sequentially stacked from bottom to top, wherein both sides of the top layer of the first conductive type semiconductor drift region 3 are provided with a trench gate structure, the trench gate structure comprises a shielding gate electrode 9 arranged at the bottom of a trench 7, a control gate electrode 8 arranged at the top of the trench 7 and a dielectric layer 10 arranged at the periphery of the control gate electrode 8 and the shielding gate electrode 9, and the control gate electrode 8 and the shielding gate electrode 9 are isolated by the dielectric layer 10; a second conductive type semiconductor body region 4 is also arranged between the trench gate structures on two sides of the top layer of the first conductive type semiconductor drift region 3, and the method is characterized in that: the top layer of the second conductive type semiconductor body region 4 is provided with a plurality of second conductive type semiconductor contact regions 5 and first conductive type semiconductor source regions 6 which are alternately arranged, and two sides of each second conductive type semiconductor contact region 5 and each first conductive type semiconductor source region 6 are in contact with the dielectric layer 10 on the side wall of the groove 7; a second conductive type semiconductor current guiding layer 11 is arranged between the second conductive type semiconductor body region 4 and the first conductive type semiconductor drift region 3 below the second conductive type semiconductor contact region 5 and the dielectric layer 10 on the side wall of the groove 7, the junction depth of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4 and smaller than that of the groove 7, and the doping concentration of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4.
The second technical scheme is as follows:
a shielded gate power DMOS device, the cell structure of which comprises: the structure comprises a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor drift region 3 and a metalized source 12 which are sequentially stacked from bottom to top, wherein both sides of the top layer of the first conductive type semiconductor drift region 3 are provided with a trench gate structure, the trench gate structure comprises a shielding gate electrode 9 arranged at the bottom of a trench 7, a control gate electrode 8 arranged at the top of the trench 7 and a dielectric layer 10 arranged at the periphery of the control gate electrode 8 and the shielding gate electrode 9, and the control gate electrode 8 and the shielding gate electrode 9 are isolated by the dielectric layer 10; a second conductive type semiconductor body region 4 is also arranged between the trench gate structures on two sides of the top layer of the first conductive type semiconductor drift region 3, and the method is characterized in that: the top layer of the second conductive type semiconductor body region 4 is provided with a plurality of second conductive type semiconductor contact regions 5 and first conductive type semiconductor source regions 6 which are alternately arranged, and two sides of each second conductive type semiconductor contact region 5 and each first conductive type semiconductor source region 6 are in contact with the dielectric layer 10 on the side wall of the groove 7; a second conductive type semiconductor current guiding layer 11 is arranged between the second conductive type semiconductor contact region 5, the second conductive type semiconductor body region 4, the first conductive type semiconductor drift region 3 and the dielectric layer 10 on the side wall of the groove 7, the junction depth of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4 and smaller than that of the groove 7, and the doping concentration of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4.
In the above two technical solutions, as a preferable mode, the junction depths of the second conductivity type semiconductor contact region 5 and the first conductivity type semiconductor source region 6 are close, and the junction depths of the second conductivity type semiconductor contact region 5 and the first conductivity type semiconductor source region 6 are both greater than the depth of the upper surface of the control gate electrode 8.
In the above two embodiments, preferably, the junction depth of the second conductivity type semiconductor body region 4 is smaller than the depth of the lower surface of the control gate electrode 8.
In the above two embodiments, the thickness of the dielectric layer 10 around the control gate electrode 8 is preferably smaller than the thickness of the dielectric layer 10 around the shield gate electrode 9.
In the two technical solutions, further, the semiconductor material is silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.
The concept of the invention is as follows:
the invention is improved based on the structure of the traditional shielded gate power DMOS device, the top layer of a drift region between trench gate structures at two sides of the device is provided with a body region, the top layer of the body region is provided with a source region and a contact region which are alternately arranged, a heavily doped current guide layer is introduced between the contact region and the side wall of a trench by reasonably setting the alternate arrangement direction of the source region and the contact region to form a current channel with lower on-resistance, so that dielectric layers of the source region and the side wall of the trench are directly contacted, and the current guide layer vertically and downwards extends along the side wall of the trench from the contact position where the current guide layer is contacted with the contact region. Therefore, the invention improves the UIS tolerance of the device by blocking the conduction of the parasitic BJT, thereby improving the UIS failure resistance of the device. Meanwhile, transverse electric fields are generated between the shielding gate electrode and the drift region and between the current guiding layer and the drift region, and the current guiding layer and the drift region are transversely depleted due to the transverse electric fields, so that the current guiding layer is prevented from generating negative effects on the device.
Compared with the prior art, the invention has the beneficial effects that: the shielding gate power DMOS device provided by the invention can effectively prevent the starting of a parasitic BJT, and meanwhile, the lateral depletion effect of the shielding gate electrode avoids the negative influence of a current guiding layer on the voltage resistance.
Drawings
Fig. 1 is a schematic cross-sectional view of a cell structure of a conventional shielded gate power DMOS device.
Fig. 2 is a schematic cross-sectional view of a cell structure of a shielded gate power DMOS device according to embodiment 1 of the present invention.
Fig. 3 is a schematic perspective view of a cell structure of a shielded gate power DMOS device according to embodiment 2 of the present invention.
FIG. 4 is a schematic cross-sectional view of a cell structure along line AA' in example 2 of the present invention.
FIG. 5 is a schematic cross-sectional view of a cell structure along line BB' according to embodiment 2 of the present invention.
In the figure, 1 is a metalized drain, 2 is a first conductive type semiconductor substrate, 3 is a first conductive type semiconductor drift region, 4 is a second conductive type semiconductor body region, 5 is a second conductive type semiconductor contact region, 6 is a first conductive type semiconductor source region, 7 is a trench, 8 is a control gate electrode, 9 is a shield gate electrode, 10 is a dielectric layer, 11 is a second conductive type semiconductor current guiding layer, and 12 is a metalized source.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1:
a shielded gate power DMOS device having a cell structure with a cross-sectional view as shown in fig. 2, comprising: the structure comprises a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor drift region 3 and a metalized source 12 which are sequentially stacked from bottom to top, wherein both sides of the top layer of the first conductive type semiconductor drift region 3 are provided with a trench gate structure, the trench gate structure comprises a shielding gate electrode 9 arranged at the bottom of a trench 7, a control gate electrode 8 arranged at the top of the trench 7 and a dielectric layer 10 arranged at the periphery of the control gate electrode 8 and the shielding gate electrode 9, and the control gate electrode 8 and the shielding gate electrode 9 are isolated by the dielectric layer 10; a second conductive type semiconductor body region 4 is also arranged between the trench gate structures on two sides of the top layer of the first conductive type semiconductor drift region 3, the junction depth of the second conductive type semiconductor body region 4 is smaller than the depth of the lower surface of the control gate electrode 8, and the method is characterized in that: the top layer of the second conductive type semiconductor body region 4 is provided with a plurality of second conductive type semiconductor contact regions 5 and first conductive type semiconductor source regions 6 which are alternately arranged, and two sides of each second conductive type semiconductor contact region 5 and each first conductive type semiconductor source region 6 are in contact with the dielectric layer 10 on the side wall of the groove 7; the second conductive type semiconductor contact region 5 and the first conductive type semiconductor source region 6 are both heavily doped, the junction depths of the second conductive type semiconductor contact region 5 and the first conductive type semiconductor source region 6 are similar, and the junction depths of the second conductive type semiconductor contact region 5 and the first conductive type semiconductor source region 6 are both greater than the depths of the upper surfaces of the control gate electrodes 8; a second conductive type semiconductor current guiding layer 11 is arranged between the second conductive type semiconductor body region 4 and the first conductive type semiconductor drift region 3 below the second conductive type semiconductor contact region 5 and the dielectric layer 10 on the side wall of the groove 7, the junction depth of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4 and smaller than that of the groove 7, and the doping concentration of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4.
Example 2:
a shielded gate power DMOS device, wherein a schematic perspective view of a cell structure is shown in fig. 3, and fig. 4 and 5 are schematic cross-sectional views taken along lines AA 'and BB' of the cell structure, respectively, and the device comprises: the method comprises the following steps: the structure comprises a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor drift region 3 and a metalized source 12 which are sequentially stacked from bottom to top, wherein both sides of the top layer of the first conductive type semiconductor drift region 3 are provided with a trench gate structure, the trench gate structure comprises a shielding gate electrode 9 arranged at the bottom of a trench 7, a control gate electrode 8 arranged at the top of the trench 7 and a dielectric layer 10 arranged on the periphery of the control gate electrode 8 and the shielding gate electrode 9, the control gate electrode 8 and the shielding gate electrode 9 both extend along the x-axis direction shown in fig. 3 and are isolated from each other through the dielectric layer 10; a second conductive type semiconductor body region 4 is also arranged between the trench gate structures on two sides of the top layer of the first conductive type semiconductor drift region 3, the junction depth of the second conductive type semiconductor body region 4 is smaller than the depth of the lower surface of the control gate electrode 8, and the method is characterized in that: the top layer of the second conductive type semiconductor body region 4 is provided with a plurality of second conductive type semiconductor contact regions 5 and first conductive type semiconductor source regions 6 which are alternately arranged, and two sides of each second conductive type semiconductor contact region 5 and each first conductive type semiconductor source region 6 are in contact with the dielectric layer 10 on the side wall of the groove 7; as shown in fig. 3, the second conductivity type semiconductor contact regions 5 and the first conductivity type semiconductor source regions 6 are alternately arranged in the y-axis direction so that the second conductivity type semiconductor contact regions 5 and the first conductivity type semiconductor source regions 6 are not located on the same cross section formed along the x-axis at the same time; the second conductive type semiconductor contact region 5 and the first conductive type semiconductor source region 6 are both heavily doped, the junction depths of the second conductive type semiconductor contact region 5 and the first conductive type semiconductor source region 6 are similar, and the junction depths of the second conductive type semiconductor contact region 5 and the first conductive type semiconductor source region 6 are both greater than the depths of the upper surfaces of the control gate electrodes 8; a second conductive type semiconductor current guiding layer 11 is arranged between the second conductive type semiconductor contact region 5, the second conductive type semiconductor body region 4, the first conductive type semiconductor drift region 3 and the dielectric layer 10 on the side wall of the groove 7, the junction depth of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4 and smaller than that of the groove 7, and the doping concentration of the second conductive type semiconductor current guiding layer 11 is larger than that of the second conductive type semiconductor body region 4.
The working principle of the present invention is specifically explained below with reference to embodiment 2 of the present invention, and those skilled in the art can obtain the working principle of embodiment 1 on the basis of the working principle of embodiment 2 disclosed. The specific working principle is detailed as follows:
in the forward conduction mode, the electrode connection mode of the device in example 2 is as follows: the metalized source 14 is connected with a low potential, the metalized drain 1 is connected with a high potential, the control gate electrode 8 is connected with a high potential, and the shielding gate electrode 9 and the metalized source 14 have the same potential; when a forward bias voltage applied to the control gate electrode 8 reaches a threshold voltage, an inversion channel is formed in the second conductivity type semiconductor body 4 near the sidewall of the trench 7; at this time, first conductivity type free carriers are injected into the first conductivity type semiconductor drift region 3 from the heavily doped first conductivity type semiconductor source region 6 through the inversion channel in the second conductivity type semiconductor body region 4 to form a forward conduction current;
in the reverse blocking mode, the electrode connection mode of the device in example 2 is: the metalized source 14 is connected with a low potential, the metalized drain 1 is connected with a high potential, the control gate electrode 8 is connected with a low potential, and the shielding gate electrode 9 and the metalized source 14 are at the same potential. Since the shield gate electrode 9 is at a low potential, the second conductivity type semiconductor current guiding layer 11 connected to the heavily doped second conductivity type semiconductor contact region 5 is also at a low potential, and lateral electric fields will be generated between the shield gate electrode 9 and the first conductivity type semiconductor drift region 3 and between the shield gate electrode 9 and the second conductivity type semiconductor current guiding layer 11; under the condition that the doping concentrations of the second conduction type semiconductor current guiding layer 11 and the first conduction type semiconductor drift region 3 are both proper, the lateral electric field enables the second conduction type semiconductor current guiding layer 11 and the first conduction type semiconductor drift region 3 to be laterally depleted, and therefore negative effects of the second conduction type semiconductor current guiding layer 11 on the voltage resistance of the device are avoided.
The shielded gate power DMOS device provided in this embodiment is capable of being used to form a power DMOS device with a high breakdown voltage during UIS, if the device is subject to avalanche breakdown, since the second conductivity type semiconductor current guiding layer 11 having a relatively high doping concentration has a low on-resistance, and carriers always select a path having the smallest resistance, so that an avalanche breakdown current can be fixed in the second conductivity type semiconductor current guiding layer 11, while since the second conductivity type semiconductor current guiding layer 11 is connected to the heavily doped second conductivity type semiconductor contact region 5, so that the avalanche current can be guided away from the heavily doped second conductivity type semiconductor contact region 5 via the second conductivity type semiconductor current guiding layer 11, and the semiconductor body region 4 of the second conduction type below the source region 6 of the heavily doped semiconductor of the first conduction type can not pass through, so that the starting of a parasitic BJT is avoided, and the UIS failure resistance of the device is improved.
The above embodiments are merely illustrative and not restrictive, and those skilled in the art can make modifications and changes without departing from the spirit of the present invention and the scope of the appended claims.
Claims (6)
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| CN113690301B (en) | 2020-05-18 | 2024-01-26 | 华润微电子（重庆）有限公司 | Semiconductor device and method for manufacturing the same |
| CN113838915B (en) * | 2021-09-23 | 2023-03-28 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| CN113838917B (en) * | 2021-09-23 | 2023-03-28 | 电子科技大学 | Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof |
| CN114122113B (en) * | 2022-01-27 | 2022-05-03 | 江苏游隼微电子有限公司 | High-reliability MOSFET power semiconductor device structure |
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| CN101924137A (en) * | 2009-06-12 | 2010-12-22 | 万国半导体股份有限公司 | Nanotube semiconductor device and its preparation method |
| CN104051534A (en) * | 2012-12-19 | 2014-09-17 | 万国半导体股份有限公司 | vertical DMOS transistor |
| WO2018049641A1 (en) * | 2016-09-17 | 2018-03-22 | 电子科技大学 | Single event burnout resistance-improved trench gate mos device |
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Patent Citations (4)
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|---|---|---|---|---|
| CN101454882A (en) * | 2006-03-24 | 2009-06-10 | 飞兆半导体公司 | High Density Trench FET with Integrated Schottky Diode and Method of Fabrication |
| CN101924137A (en) * | 2009-06-12 | 2010-12-22 | 万国半导体股份有限公司 | Nanotube semiconductor device and its preparation method |
| CN104051534A (en) * | 2012-12-19 | 2014-09-17 | 万国半导体股份有限公司 | vertical DMOS transistor |
| WO2018049641A1 (en) * | 2016-09-17 | 2018-03-22 | 电子科技大学 | Single event burnout resistance-improved trench gate mos device |
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