CN114335180A - Shielded gate trench transistor with triangularly arranged source region and preparation method thereof - Google Patents

Abstract

The present application relates to a shielded gate trench transistor having a source region arranged in a triangular shape, comprising: the transistor comprises a substrate region, a drift region, a base region, a source region, a shielding grid, a control grid, an insulating layer, a source electrode, a drain electrode and a metal grid; the drift region, the base region and the source region are sequentially arranged at the top of the substrate region, and the drain electrode is positioned at the bottom of the substrate region; the control grid and the shielding grid are sequentially arranged on the side of the drift region from top to bottom and are respectively connected with the drift region, the substrate region and the source region through insulating layers; the source region comprises a P-type source region and an N-type source region; the P-type source region is a triangular source region with a triangular cross section, and the vertex angle of the triangular source region is connected with the insulating layer; the N-type source region comprises a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are respectively arranged at two sides of the vertex angle and are respectively connected with the insulating layer. The scheme provided by the application can effectively inhibit the parasitic triode from being started, and effectively improves the avalanche tolerance.

Description

Shielded gate trench transistor with triangularly arranged source region and preparation method thereof

Technical Field

The application relates to the technical field of semiconductors, in particular to a shielded gate trench transistor with a triangular arrangement source region and a preparation method thereof.

Background

The shielded gate trench field effect transistor SGT has the advantages of low specific on resistance, low static and dynamic loss, high switching speed, and the like. This is because it effectively isolates the control gate to drain coupling, with significant advantages in terms of channel density, charge compensation effects and shielded gate structure.

The maximum current of a transistor in inductive load application is limited by the avalanche tolerance in the traditional SGT, a base region is in short circuit with an N-type source region connected with a channel through a heavily doped P-type source region, when the transistor is in forward high-voltage blocking or forward high-voltage conduction, a hole is possibly generated due to an avalanche effect, and therefore a hole current which enables a parasitic triode to be started is formed by flowing through a channel of the base region.

In the related art, a source structure having a composite type of a P-type source region and an N-type source region is adopted in a transistor, wherein the P-type source region short-circuits a body region and a source of the transistor. The source region structure generally adopts an interdigital strip structure, namely a P-type source region and an N-type source region are arranged on a base region in parallel, and the source region structure can cause the area of the source region for receiving avalanche current to be limited, so that the maximum avalanche tolerance of the transistor is limited.

Disclosure of Invention

In order to overcome the problems in the related art, the invention provides a shielded gate trench transistor with a triangular arrangement source region and a preparation method thereof, which can effectively inhibit the parasitic triode from being turned on and effectively improve the avalanche tolerance.

A first aspect of the present application provides a shielded gate trench transistor having source regions arranged in a triangular shape, comprising: the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode, a drain electrode 8 and a metal grid electrode; the source is arranged on top of the source region 4 and the metal gate is arranged on top of the control gate 6; the drift region 2, the body region 3 and the source region 4 are sequentially arranged at the top of the substrate region 1, and the drain electrode 8 is positioned at the bottom of the substrate region 1;

the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the substrate region 3 and the source region 4 through the insulating layer 7;

the source region 4 comprises a P-type source region 41 and an N-type source region 42; the P-type source region 41 is a triangular source region with a triangular cross section, and the vertex angle of the triangular source region is connected with the insulating layer 7;

the N-type source region 42 includes a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are respectively arranged on two sides of the vertex angle and are respectively connected with the insulating layer 7.

In one embodiment, the shielded gate trench transistor having a triangularly arranged source region further comprises: a P-type super junction column 9;

the top of the P-type super junction column 9 is attached to the bottom of the P-type source region 41; the side surface of the P-type super junction column 9 is respectively connected with the base region 3 and the drift region 2.

In one embodiment, the P-type super-junction pillar 9 and the P-type source region 41 form a triangular prism structure, and the body region 3 includes a first body region and a second body region, which are disposed at two sides of the triangular prism structure and respectively connected to bottom surfaces of the first N-type source region and the second N-type source region.

In one embodiment, the P-type source region 41 is an isosceles triangle source region with a cross section of an isosceles triangle, and the cross sections of the first N-type source region and the second N-type source region are both right-angled triangles; the oblique edges of the first N-type source region and the second N-type source region are respectively attached to the two waists of the P-type source region 41.

In one embodiment, the height of P-type super junction pillar 9 is less than or equal to the sum of the heights of body region 3 and drift region 2.

In one embodiment, the doping concentration of the P-type super junction pillar 9 is a medium doping concentration.

In one embodiment, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavily doped;

the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is heavy doping concentration;

the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is medium doping concentration;

the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration;

the doping type of the shielding gate 5 and the control gate 6 is P-type doping or N-type doping, and the doping concentration of the shielding gate 5 and the control gate 6 is heavy doping concentration.

A second aspect of the present application provides a method for manufacturing a shielded gate trench transistor having a source region with a triangular arrangement, the method being used for manufacturing the shielded gate trench transistor having a source region with a triangular arrangement as described above, and including:

manufacturing a substrate region by using a semiconductor material;

epitaxially forming a drift region on the substrate region;

forming a base region on the drift region in an ion implantation or diffusion mode;

doping on the substrate region to form an N-type source region;

respectively etching a first groove and a second groove on two sides of the drift region;

depositing oxide and polysilicon in the first trench to form an insulating layer, a shielding gate and a control gate;

doping in the second groove to form a P-type source region;

manufacturing source electrodes above the P-type source region and the N-type source region;

manufacturing a metal grid above the first groove;

and manufacturing a drain electrode at the bottom of the substrate region.

In an embodiment, a first trench and a second trench are respectively etched on two sides of the drift region, and the depth of the second trench is greater than the height of the N-type source region;

the doping in the second groove forms a P-type source region, and the method comprises the following steps:

and depositing in the second groove in sequence to form a P-type super junction column and a P-type source region.

In one embodiment, the depositing oxide and polysilicon in the first trench to form an insulating layer, a shield gate and a control gate includes:

and depositing an oxide, polysilicon, an oxide and polysilicon in the first trench in sequence to form the insulating layer, the shielding gate and the control gate.

The technical scheme provided by the application can comprise the following beneficial effects:

the application provides a shielded gate trench transistor with a triangular arrangement source region, wherein the source region comprises a P-type source region with a triangular cross section, and a first N-type source region and a second N-type source region which are respectively arranged at two sides of the P-type source region; because the apex angle of P type source region meets with the insulating layer, first N type source region and second N type source region divide and establish on the both sides of apex angle, and meet with the insulating layer respectively, make the triangular arrangement source region in this application, compare with the interdigital strip structure source region that adopts in traditional shielded gate trench type transistor, its P type source region is more close to the ditch groove district, thereby when making when taking place the avalanche breakdown, the path that the hole current flows to P type source region from the ditch groove district shortens, the opening of parasitic triode has been suppressed, shielded gate trench type field effect transistor's avalanche tolerance has been improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.

Fig. 1 is a schematic structural diagram of a shielded gate trench transistor having a triangular arrangement of source regions according to an embodiment of the present application;

fig. 2 is a schematic diagram of another structure of a shielded gate trench transistor having a source region arranged in a triangular shape according to an embodiment of the present application;

fig. 3 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench transistor having a source region arranged in a triangular shape according to an embodiment of the present application;

fig. 4 is another schematic flow chart of a method for manufacturing a shielded gate trench transistor having a triangular arrangement of source regions according to an embodiment of the present application.

Detailed Description

Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Example one

The source region structure in the conventional shielded gate trench transistor generally adopts an interdigital strip structure, that is, a P-type source region and an N-type source region are arranged on a base region in parallel, and the source region structure can cause the area of a source region for receiving avalanche current to be limited, so that the maximum avalanche tolerance of the transistor is limited.

In view of the above problems, embodiments of the present application provide a shielded gate trench transistor having a triangular arrangement source region, which can effectively suppress the turn-on of a parasitic triode and effectively improve avalanche tolerance.

The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a shielded gate trench transistor having a triangular arrangement of source regions according to an embodiment of the present application.

Referring to fig. 1, a shielded gate trench type transistor having a source region arranged in a triangular shape includes:

the transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding grid 5, a control grid 6, an insulating layer 7, a source electrode, a drain electrode 8 and a metal grid electrode;

wherein, the source electrode is arranged on the top of the source region 4, the metal gate electrode is arranged on the top of the control gate 6, and the drain electrode 8 is positioned at the bottom of the substrate region 1; the drift region 2, the base region 3 and the source region 4 are sequentially arranged at the top of the substrate region 1; the control grid 6 and the shielding grid 5 are sequentially arranged on the side of the drift region 2 from top to bottom and are respectively connected with the drift region 2, the base region 3 and the source region 4 through the insulating layer 7.

Wherein, the source region 4 includes a P-type source region 41 and an N-type source region 42; the P-type source region 41 is a triangular source region with a triangular cross section, and the vertex angle of the triangular source region is connected with the insulating layer 7; the N-type source region 42 includes a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are respectively arranged at two sides of the vertex angle and are respectively connected with the insulating layer 7.

In the embodiment of the present application, the P-type source region 41 is located in the middle of the source region 4, and the P-type source region 41 is connected to the insulating layer 7, which is equivalent to that the P-type source region 41 is connected to the trench region of the transistor, compared with the source region structure of the interdigital strip structure adopted by the conventional shielded gate trench transistor, the P-type source region in the embodiment of the present application is closer to the trench region, and the P-type source region, that is, the vertex angle of the triangular source region is connected to the insulating layer 7, and the space of the N-type source region is not squeezed, so that under the condition that the area of the N-type source region is ensured, the moving path of the hole current is reduced, the opening of the parasitic triode is effectively inhibited, and the avalanche tolerance of the shielded gate trench field effect transistor is improved.

Further, the P-type source region 41 is an isosceles triangle source region with a cross section in the shape of an isosceles triangle, and the cross sections of the first N-type source region and the second N-type source region are both in the shape of a right triangle; the oblique edges of the first N-type source region and the second N-type source region are respectively attached to the two waists of the P-type source region 41.

In the embodiment of the present application, the P-type source region is of a symmetric structure with the height in the vertical control gate length direction as a symmetry axis, and accordingly, the first N-type source region and the second N-type source region respectively disposed at two sides of the vertex angle of the triangular source region are of two symmetric right triangles, so that the hole current generated by the trench region uses the height in the vertical control gate length direction as a boundary, the hole current at two sides of the boundary flows to the P-type source region in a symmetric moving path, and the moving path is shortened compared with the transistor in the conventional source region with the interdigital strip structure.

In the embodiment of the present application, the doping concentrations of the P-type source region 41 and the N-type source region 42 are both heavy doping concentrations; the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is medium doping concentration; the doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration; the doping type of the shielding gate 5 and the control gate 6 is P-type doping or N-type doping, and the doping concentration of the shielding gate 5 and the control gate 6 is heavy doping concentration.

In the embodiment of the present application, the value range of the lightly doped concentration is 1 × 10¹⁵cm^-3To 5X 10¹⁶cm^-3(ii) a The value range of the medium doping concentration is 1 multiplied by 10¹⁷cm^-3To 5X 10¹⁸cm^-3(ii) a The value range of the heavy doping concentration is 1 multiplied by 10¹⁹cm^-3To 5X 10²⁰cm^-3。

The shielded gate trench transistor with the triangularly arranged source region provided by the embodiment of the application comprises a P-type source region with a triangular cross section, and a first N-type source region and a second N-type source region which are respectively arranged at two sides of the P-type source region; because the apex angle of P type source region meets with the insulating layer, first N type source region and second N type source region divide and establish on the both sides of apex angle, and meet with the insulating layer respectively, make the triangular arrangement source region in this application, compare with the interdigital strip structure source region that adopts in traditional shielded gate trench type transistor, its P type source region is more close to the ditch groove district, thereby when making when taking place the avalanche breakdown, the path that the hole current flows to P type source region from the ditch groove district shortens, the opening of parasitic triode has been suppressed, shielded gate trench type field effect transistor's avalanche tolerance has been improved.

Example two

Based on the shielded gate trench transistor with the triangular arrangement source region provided by the first embodiment, the embodiment of the application provides another shielded gate trench transistor with the triangular arrangement source region, which can improve the electric field distribution in the drift region by using a charge compensation principle, so that the effect of improving the breakdown voltage is achieved.

Referring to fig. 2, the shielded gate trench type transistor having a delta arrangement source region includes:

the super-junction transistor comprises a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding gate 5, a control gate 6, an insulating layer 7, a source electrode, a drain electrode 8, a metal gate and a P-type super-junction column 9;

the structures of the substrate region 1, the drift region 2, the body region 3, the source region 4, the shielding gate 5, the control gate 6, the insulating layer 7, the source electrode, the drain electrode 8 and the metal gate are the same as those in the first embodiment, and are not described herein again.

In the embodiment of the present application, the shielded gate trench transistor having the triangular arrangement source region further includes a P-type super junction pillar 9, and the top of the P-type super junction pillar 9 is attached to the bottom of the P-type source region 41; the side surface of the P-type super junction column 9 is respectively connected with the base region 3 and the drift region 2.

Namely, the drift region 2 is also provided with a P-type super-junction column 9, the P-type super-junction column 9 forms a P-type compensation region in the drift region 2 for inhibiting the lateral impurity diffusion of the drift region 2 in a high-temperature process, and the electric field distribution in the drift region 2 is improved through a charge compensation principle, so that the electric fields which are densely distributed at the corners of the shielding gate tend to be uniformly distributed, and the breakdown voltage is further improved.

Further, the P-type super-junction column 9 and the P-type source region 41 form a triangular prism structure, the base region 3 includes a first base region and a second base region, and the first base region and the second base region are respectively disposed on two sides of the triangular prism structure and are respectively connected to the bottom surfaces of the first N-type source region and the second N-type source region.

The shape of the P-type super-junction column 9 is not limited uniquely in the embodiment of the application, in the practical application process, the P-type super-junction column 9 can be set to be a quadrangular prism or other shapes, preferably, the P-type super-junction column 9 is set to be a triangular prism, and the cross section of the triangular prism is consistent with that of the P-type source region 41, so that the bottom surface of the P-type source region 41 and the top surface of the P-type super-junction column 9 can be completely attached to form a triangular prism structure, and a regular hole current flowing channel is formed.

Further, the height of the P-type super junction pillar 9 is less than or equal to the sum of the heights of the body region 3 and the drift region 2.

In practical application, the P-type super-junction pillar 9 may be set such that the bottom surface is connected to the substrate region 1, forming a super-junction structure penetrating the drift region 2; or the bottom surface of the drift region 2 is connected with the drift region, and the specific structure can be selected according to the actual situation, which is not limited here.

In the embodiment of the present application, the doping type of the P-type super junction column 9 is P-type doping, and the doping concentration thereof is medium doping concentration.

The shielding grid groove type transistor with the triangular arrangement source region provided by the embodiment of the application has the advantages that the P type super-junction column connected with the base region and the drift region is introduced below the P type source region, so that the transverse impurity diffusion of the P type doping region and the N type doping region in a high-temperature process is effectively inhibited, namely the transverse diffusion of the drift region, the electric field distribution in the drift region is improved through a charge compensation principle, the electric field which is densely distributed at the corners of the shielding grid originally tends to be uniformly distributed, and the breakdown voltage is further improved.

EXAMPLE III

Corresponding to the shielded gate trench transistor with the triangular arrangement source region in the first embodiment, the application also provides a preparation method of the shielded gate trench transistor with the triangular arrangement source region and a corresponding embodiment.

Fig. 3 is a schematic flow chart illustrating a method for manufacturing a shielded gate trench transistor having a triangular arrangement of source regions according to an embodiment of the present application.

Referring to fig. 3, the method for manufacturing the shielded gate trench transistor having the triangularly arranged source region includes:

301. manufacturing a substrate region by using a semiconductor material;

in the embodiment of the present application, the substrate region is made of an N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration is a heavily doped concentration.

302. Epitaxially forming a drift region on the substrate region;

in the embodiment of the present application, different epitaxy processes may be adopted according to actual requirements, including but not limited to: vapor Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD).

303. Forming a base region on the drift region in an ion implantation or diffusion mode;

the ion implantation process is a process of doping silicon materials, in the practical application process, a power device product is placed at one end of an ion implanter, and a doping ion source is arranged at the other end of the ion implanter. At one end of the doping ion source, doping body atoms are ionized to carry certain charges, the charges are added to the super high speed by an electric field, penetrate through the surface layer of a product, and the doping atoms are injected into a power device by utilizing the momentum of the atoms to form a doping area.

The diffusion process is a process of doping pure impurity atoms on the surface of the silicon material, and in the practical application process, diborane or phosphine is usually used as an ion source, and the pure impurity atoms are doped on the surface of the silicon material by adopting an intermittent diffusion or displacement diffusion mode.

It should be noted that, in the embodiment of the present application, the preparation method adopted for the substrate region is not strictly limited, and in an actual process, the different processes may be selected according to actual requirements to complete the preparation of the substrate region.

304. Doping on the substrate region to form an N-type source region;

in the embodiment of the application, an N-type heavily doped semiconductor material is doped on a base region to form an N-type source region, the top surface of the base region is completely covered with the N-type heavily doped semiconductor material, namely the N-type source region completely covers the base region, and then part of the N-type source region is etched and removed through an etching process to expose a space for doping to form a P-type source region with a triangular cross section.

305. Respectively etching a first groove and a second groove on two sides of the drift region;

in the embodiment of the present application, the second trench has a triangular prism shape, and a depth of the second trench is equal to a height of the N-type source region.

306. Depositing oxide and polysilicon in the first trench to form an insulating layer, a shielding gate and a control gate;

in this embodiment, an oxide, a polysilicon, an oxide, and a polysilicon are sequentially deposited in the first trench to form the insulating layer, the shielding gate, and the control gate.

In the embodiment of the application, the polysilicon may be P-type doped polysilicon or N-type doped polysilicon, the doping concentration of the polysilicon is medium doping concentration or heavy doping concentration, and preferably, the polysilicon is heavy doping polysilicon.

307. Doping in the second groove to form a P-type source region;

in the embodiment of the application, the second groove is triangular prism-shaped, and the depth of the second groove is equal to the height of the N-type source region, so that the triangular source region is formed by doping a P-type heavily doped semiconductor material in the second groove, that is, the P-type source region is obtained, and the vertex angle of the triangular source region is connected with the insulating layer, so that compared with the traditional transistor adopting an interdigital strip structure, the P-type source region in the transistor of the embodiment of the application is closer to the first groove, thereby shortening the moving path of hole current in avalanche and achieving the effect of improving the avalanche tolerance of the transistor.

308. Manufacturing source electrodes above the P-type source region and the N-type source region;

309. manufacturing a metal grid above the first groove;

in an embodiment of the present application, a metal gate is fabricated over the first trench such that the metal gate is located on top of the control gate.

310. And manufacturing a drain electrode at the bottom of the substrate region.

In the embodiment of the present application, the execution timing of the steps 308 to 310 is not strictly limited, that is, in the actual application process, the steps 308 to 310 may be executed in any order, or the three may be executed in parallel.

It should be noted that, in practical applications, the following steps may be adopted to form the delta-shaped arrangement source region of the transistor according to the first embodiment:

doping a P-type semiconductor material on a base region to form a P-type source region, removing part of the P-type source region through an etching process to enable the reserved P-type source region to be triangular prism-shaped, forming two grooves for doping to form an N-type source region on the base region, and filling the grooves with an N-type doped semiconductor material to obtain the N-type source region.

The embodiment of the application provides a preparation method of a shielded gate trench type transistor with a triangular arrangement source region, after an N-type source region is formed by doping on a substrate region, part of the N-type source region is removed by etching by using an etching process to form a triangular prism-shaped second trench, a P-type semiconductor material is doped in the second trench to obtain a P-type source region with a triangular cross section, and the vertex angle of the P-type source region is connected with an insulating layer, so that the P-type source region in the transistor is closer to the first trench, and therefore when avalanche breakdown occurs, the path of a hole current flowing from the trench region to the P-type source region is shortened, the starting of a parasitic triode is inhibited, and the avalanche tolerance of the shielded gate trench type field effect transistor is improved.

Example four

Corresponding to the shielded gate trench transistor with the triangular arrangement source region in the second embodiment, the application also provides a preparation method of the shielded gate trench transistor with the triangular arrangement source region and a corresponding embodiment.

Fig. 4 is another schematic flow chart of a method for manufacturing a shielded gate trench transistor having a triangular arrangement of source regions according to an embodiment of the present application.

Referring to fig. 4, the method for manufacturing the shielded gate trench transistor having the triangularly arranged source region includes:

401. manufacturing a substrate region by using a semiconductor material;

402. epitaxially forming a drift region on the substrate region;

403. forming a base region on the drift region in an ion implantation or diffusion mode;

404. doping on the substrate region to form an N-type source region;

in the embodiment of the present application, the contents of the steps 401 to 404 are the same as those of the steps 301 to 304 in the third embodiment, and are not described herein again.

405. Respectively etching a first groove and a second groove on two sides of the drift region;

in an embodiment of the present application, a depth of the second trench is greater than a height of the N-type source region.

406. Depositing oxide and polysilicon in the first trench to form an insulating layer, a shielding gate and a control gate;

in this embodiment, an oxide, a polysilicon, an oxide, and a polysilicon are sequentially deposited in the first trench to form the insulating layer, the shielding gate, and the control gate.

In the embodiment of the application, the polysilicon may be P-type doped polysilicon or N-type doped polysilicon, the doping concentration of the polysilicon is medium doping concentration or heavy doping concentration, and preferably, the polysilicon is heavy doping polysilicon.

407. Depositing in the second groove in sequence to form a P-type super junction column and a P-type source region;

in the embodiment of the application, a P-type super-junction column is obtained by depositing a P-type medium-doped semiconductor material in the second trench, so that the top surface of the P-type super-junction column is flush with the top surface of the base region, and a P-type source region is obtained by depositing a P-type heavily-doped semiconductor material on the top surface of the P-type super-junction column.

In practical application, the depth of the second trench may be set to be the sum of the heights of the N-type source region and the drift region, so that the bottom surface of the deposited P-type super junction column is attached to the top surface of the substrate region.

408. Manufacturing source electrodes above the P-type source region and the N-type source region;

409. manufacturing a metal grid above the first groove;

410. and manufacturing a drain electrode at the bottom of the substrate region.

In the embodiment of the present application, the execution timing of the steps 408 to 410 is not strictly limited, that is, in the actual application process, the steps 408 to 410 may be executed in any order, or the three may be executed in parallel.

The embodiment of the application provides a preparation method of a shielded gate trench type transistor with a triangular arrangement source region, wherein after an N-type source region is formed by doping on a substrate region, part of the N-type source region is removed by etching by utilizing an etching process to form a second trench, a P-type doped semiconductor material and a P-type heavily doped semiconductor material are sequentially doped in the second trench to obtain a P-type super junction column and a P-type source region with a triangular cross section, and the vertex angle of the P-type source region is connected with an insulating layer, so that the P-type source region in the transistor disclosed by the embodiment of the application is closer to the first trench, and therefore when avalanche breakdown occurs, the path of a hole current flowing from the trench region to the P-type source region is shortened, the starting of a parasitic triode is inhibited, and the avalanche tolerance of the shielded gate trench type field effect transistor is improved;

the electric field distribution in the drift region is improved by the introduced P-type super-junction column by utilizing a charge compensation principle, so that the electric fields which are densely distributed at the corners of the shielding gate tend to be uniformly distributed, and the breakdown voltage is further improved.

The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. Those skilled in the art should also appreciate that the acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A shielded gate trench transistor having source regions arranged in a triangular pattern, comprising: the transistor comprises a substrate region (1), a drift region (2), a base region (3), a source region (4), a shielding gate (5), a control gate (6), an insulating layer (7), a source electrode, a drain electrode (8) and a metal gate; the source is arranged on top of the source region (4) and the metal gate is arranged on top of the control gate (6); the drift region (2), the base region (3) and the source region (4) are sequentially arranged at the top of the substrate region (1), and the drain electrode (8) is positioned at the bottom of the substrate region (1);

the control grid (6) and the shielding grid (5) are sequentially arranged on the side of the drift region (2) from top to bottom and are respectively connected with the drift region (2), the substrate region (3) and the source region (4) through the insulating layer (7);

the source region (4) comprises a P-type source region (41) and an N-type source region (42); the P-type source region (41) is a triangular source region with a triangular cross section, and the vertex angle of the triangular source region is connected with the insulating layer (7);

the N-type source region (42) comprises a first N-type source region and a second N-type source region; the first N-type source region and the second N-type source region are respectively arranged on two sides of the vertex angle and are respectively connected with the insulating layer (7).

2. The shielded gate trench transistor having a delta arrangement source region of claim 1 further comprising: a P-type super junction column (9);

the top of the P-type super-junction column (9) is attached to the bottom of the P-type source region (41); the side surface of the P-type super-junction column (9) is respectively connected with the base region (3) and the drift region (2).

3. The shielded gate trench transistor having a delta arrangement source region as set forth in claim 2,

the P type surpasses knot post (9) with P type source region (41) forms the triangular prism structure, base region (3) include first base region and second base region, first base region with the second base region is distinguished and is established the both sides of triangular prism structure, and respectively with first N type source region with the bottom surface in second N type source region meets.

4. The shielded gate trench transistor having a delta arrangement source region as set forth in claim 1,

the P-type source region (41) is an isosceles triangle source region with an isosceles triangle cross section, and the cross sections of the first N-type source region and the second N-type source region are both right-angled triangles; the oblique edges of the first N-type source region and the second N-type source region are respectively attached to the two waists of the P-type source region (41).

5. The shielded gate trench transistor having a delta arrangement source region as set forth in claim 2,

the height of the P-type super junction column (9) is less than or equal to the sum of the heights of the base region (3) and the drift region (2).

6. The shielded gate trench transistor having a delta arrangement source region as set forth in claim 2,

the doping concentration of the P-type super junction column (9) is medium doping concentration.

7. The shielded gate trench transistor having a delta arrangement source region as set forth in claim 1,

the doping concentrations of the P-type source region (41) and the N-type source region (42) are heavy doping concentrations;

the doping type of the substrate region (1) is N-type doping, and the doping concentration of the substrate region (1) is heavy doping concentration;

the doping type of the drift region (2) is N-type doping, and the doping concentration of the drift region (2) is medium doping concentration;

the doping type of the substrate region (3) is P-type doping, and the doping concentration of the substrate region (3) is medium doping concentration;

the doping type of the shielding gate (5) and the doping type of the control gate (6) are P-type doping or N-type doping, and the doping concentration of the shielding gate (5) and the doping concentration of the control gate (6) are heavy doping concentration.

8. A method for manufacturing a shielded gate trench transistor having source regions arranged in a triangular shape, which is used for manufacturing the shielded gate trench transistor having source regions arranged in a triangular shape according to any one of claims 1 to 7, comprising:

manufacturing a substrate region by using a semiconductor material;

epitaxially forming a drift region on the substrate region;

forming a base region on the drift region in an ion implantation or diffusion mode;

doping on the substrate region to form an N-type source region;

respectively etching a first groove and a second groove on two sides of the drift region;

depositing oxide and polysilicon in the first trench to form an insulating layer, a shielding gate and a control gate;

doping in the second groove to form a P-type source region;

manufacturing source electrodes above the P-type source region and the N-type source region;

manufacturing a metal grid above the first groove;

and manufacturing a drain electrode at the bottom of the substrate region.

9. The method of manufacturing a shielded gate trench transistor having source regions arranged in a triangular pattern according to claim 8,

etching a first groove and a second groove on two sides of the drift region respectively, wherein the depth of the second groove is greater than the height of the N-type source region;

the doping in the second groove forms a P-type source region, and the method comprises the following steps:

and depositing in the second groove in sequence to form a P-type super junction column and a P-type source region.

10. The method of claim 8, wherein depositing oxide and polysilicon in the first trench to form an insulating layer, a shield gate and a control gate comprises:

and depositing an oxide, polysilicon, an oxide and polysilicon in the first trench in sequence to form the insulating layer, the shielding gate and the control gate.

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