CN106158631A - Band buried regions groove power device and preparation method thereof - Google Patents
Band buried regions groove power device and preparation method thereof Download PDFInfo
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- CN106158631A CN106158631A CN201510132292.9A CN201510132292A CN106158631A CN 106158631 A CN106158631 A CN 106158631A CN 201510132292 A CN201510132292 A CN 201510132292A CN 106158631 A CN106158631 A CN 106158631A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000000407 epitaxy Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 13
- -1 compound ion Chemical class 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses a kind of band buried regions groove power device and preparation method thereof, wherein, manufacture method includes: form the first oxide layer on the substrate being formed with the first epitaxial layer and the second epitaxial layer, and the second epitaxial layer is positioned at above the first epitaxial layer；First oxide layer, the second epitaxial layer and the first epitaxial layer are performed etching the first groove that formation runs through the first oxide layer, the bottom of the second epitaxial layer is positioned in the first epitaxial layer；At the first channel bottom, the first epitaxial layer is carried out the formation of p-type ion implanting and be positioned at the p type buried layer above the first epitaxial layer；Second oxide layer identical with the first epitaxial layer height is formed at the first trench wall；In the first groove that the second oxide layer covers, fill polysilicon, remove first and second oxide layer higher than the second epitaxial layer and polysilicon layer.It is pressure that the method can improve groove power device depletion layer, and identical resistance to pressure can reduce device on-resistance, and can improve the voltage endurance capability of channel bottom corner, is substantially improved breakdown characteristic of device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of band buried regions groove power device
And preparation method thereof.
Background technology
Trench vertical bilateral diffusion field-effect tranisistor (Vertical Double Diffused
Metal Oxide Semiconductor, be called for short VDMOS) transistor have concurrently bipolar transistor and
Common metal oxides quasiconductor (Metal Oxide Semiconductor is called for short MOS) device
The advantage of part, either switch application or linear application, VDMOS is preferable power
Device, drain-source the two poles of the earth of VDMOS, respectively in the both sides of device, make electric current hang down at device inside
Direct current leads to, and adds electric current density, improves rated current, and the conducting resistance of unit are is also
Less, it is a kind of purposes power device widely.
In the design process of groove power device, the contradiction of breakdown voltage and conducting resistance is device
The bottleneck of part performance improvement.The breakdown point of groove power device concentrates on channel bottom corner,
Reduction and the increasing of the degree of depth of drift region N-type epitaxy layer concentration are conducive to reducing the big of corner
Electric field, but electric conduction resistive also can be made big simultaneously.
In consideration of it, how to reduce the conducting resistance of groove power device, improve device puncture spy
Property becomes to be presently required and solves the technical problem that.
Summary of the invention
For defect of the prior art, the invention provides a kind of band buried regions groove power device
And preparation method thereof, it is possible to increase device depletion layer is pressure, and identical resistance to pressure can reduce groove
The conducting resistance of power device device, and the voltage endurance capability of channel bottom corner can be improved,
Thus it is substantially improved breakdown characteristic of device.
First aspect, the present invention provides the manufacture method of a kind of band buried regions groove power device, bag
Include:
The substrate being formed with the first epitaxial layer and the second epitaxial layer is formed the first oxide layer, institute
State the second epitaxial layer to be positioned at above described first epitaxial layer；
Performing etching described first oxide layer, the second epitaxial layer and the first epitaxial layer, formation is passed through
Wear the first groove of described first oxide layer, the second epitaxial layer, the position, bottom of described first groove
In described first epitaxial layer；
At described first channel bottom, described first epitaxial layer is carried out p-type ion implanting, formed
P type buried layer, described p type buried layer is positioned at above described first epitaxial layer；
The second oxide layer is formed, the second oxidation in described first groove at described first trench wall
The height of layer is identical with the height of described first epitaxial layer；
In the first groove that described second oxide layer covers, fill polysilicon, and removal is higher than
First oxide layer of described second epitaxial layer, the second oxide layer and polysilicon layer.
Optionally, described first epitaxial layer is N-type epitaxy layer, and described second epitaxial layer is P
Type epitaxial layer.
Optionally, described described first oxide layer, the second epitaxial layer and the first epitaxial layer are carried out
Etching, is formed and runs through the first groove of described first oxide layer, the second epitaxial layer, and described first
The bottom of groove is positioned in described first epitaxial layer, including:
Carry out described first oxide layer etching for the first time, form the second groove, described second ditch
The bottom of groove and described second epitaxial layer upper surface；
In the position same with first time etching phase, described second epitaxial layer and the first epitaxial layer are entered
Row second time etching, forms the first groove running through described first oxide layer, the second epitaxial layer,
The bottom of described first groove is positioned in described first epitaxial layer.
Optionally, described carry out described first oxide layer etches for the first time, forms the second groove,
The bottom of described second groove and described second epitaxial layer upper surface, including:
The part surface of described first oxide layer is formed photoresist layer；
Using described photoresist layer as mask, carry out described first oxide layer etching for the first time,
Form the second groove, the bottom of described second groove and described second epitaxial layer upper surface.
Optionally, described with first time etching phase with position to described second epitaxial layer and the
One epitaxial layer carries out second time and etches, and is formed and runs through described first oxide layer, the second epitaxial layer
First groove, the bottom of described first groove is positioned in described first epitaxial layer, including:
Remove described photoresist layer；
Using the first oxide layer of the part that is not etched after etching for the first time as mask, with first
Secondary etching phase position together carries out second time and etches described second epitaxial layer and the first epitaxial layer,
Form the first groove running through described first oxide layer, the second epitaxial layer, described first groove
Bottom is positioned in described first epitaxial layer.
Optionally, described first oxide layer and/or described second oxide layer pass through thermal oxidation technology
Formed；
And/or,
Described first oxide layer and described second oxide layer are silicon oxide layer.
Optionally, dry etching or chemically mechanical polishing is used to remove higher than described second extension
First oxide layer, the second oxide layer and the polysilicon of layer.
Optionally, the thickness of described first oxide layer is 1-10um；
And/or,
Described p-type ion includes: isolated son or compound ion, and described isolated attached bag includes: hydrogen from
Son, or helium ion, or boron ion, or arsenic ion, or aluminium ion.
Optionally, removing higher than the first oxide layer of described second epitaxial layer, the second oxide layer
And after polysilicon layer, described manufacture method also includes:
Formed above the second uncovered epitaxial layer, the second oxide layer and polysilicon layer
Dielectric layer, and described dielectric layer is performed etching formation contact hole；
Metal level is formed above the dielectric layer not being etched and described contact hole.
Second aspect, the present invention provides a kind of band buried regions groove power device, described band buried regions ditch
Groove power device uses above-mentioned manufacture method to make.
The manufacture method of band buried regions groove power device that the present invention provides, by being formed with the
Forming the first oxide layer on the substrate of one epitaxial layer and the second epitaxial layer, the second epitaxial layer is positioned at
Above one epitaxial layer；First oxide layer, the second epitaxial layer and the first epitaxial layer are performed etching shape
The first ditch that one-tenth runs through the first oxide layer, the bottom of the second epitaxial layer is positioned in the first epitaxial layer
Groove；At the first channel bottom, the first epitaxial layer is carried out the formation of p-type ion implanting to be positioned at outside first
Prolong the p type buried layer above layer；Formed identical with the first epitaxial layer height at the first trench wall
Second oxide layer；Filling polysilicon in the first groove that the second oxide layer covers, removal is higher than
First and second oxide layer of the second epitaxial layer and polysilicon layer, use deep etching to coordinate impurity note
The method entered introduces p type buried layer in N-type drift region, can improve groove power device depletion layer
Pressure, identical resistance to pressure can reduce device on-resistance, forms the second oxide layer at channel bottom
The voltage endurance capability of channel bottom corner can be improved, be substantially improved breakdown characteristic of device.
Accompanying drawing explanation
The making of a kind of band buried regions groove power device that Fig. 1 provides for first embodiment of the invention
The schematic flow sheet of method；
The making of a kind of band buried regions groove power device that Fig. 2 provides for second embodiment of the invention
The schematic flow sheet of method；
Fig. 3 is that step S10 of second embodiment of the invention forms N-type epitaxy layer, p-type epitaxial layer
And first schematic diagram of oxide layer；
Fig. 4 is the schematic diagram that step S20 of second embodiment of the invention forms the second groove；
Fig. 5 is the schematic diagram that step S30 of second embodiment of the invention forms the first groove；
Fig. 6 is the schematic diagram of the step S40 formation p type buried layer of second embodiment of the invention；
Fig. 7 is the schematic diagram that step S50 of second embodiment of the invention forms the second oxide layer；
Fig. 8 is the schematic diagram of the step S60 filling polysilicon of second embodiment of the invention；
Fig. 9 is that step S70 of second embodiment of the invention removes the first oxygen higher than p-type epitaxial layer
Change layer, the second oxide layer and the schematic diagram of polysilicon layer；
Figure 10 is that step S80 of second embodiment of the invention forms dielectric layer, contact hole and metal
The schematic diagram of layer；
Figure 11 is the band buried regions groove power device using embodiment of the present invention manufacture method to make
Active area 104 and street area 101, cut-off ring region territory 102 and the position in dividing potential drop region 103
Put schematic diagram；
Reference:
In Fig. 3 to Figure 10: 1, monocrystalline substrate；2, N-type epitaxy layer；3, p-type extension
Layer；4, the first oxide layer；5, photoresist layer；6, p type buried layer；7, polysilicon；8、
Dielectric layer；9, metal level；
In Figure 11: 101, street area；102, cut-off ring region territory；103, dividing potential drop region；
104, active area.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, the detailed description of the invention of the present invention is made the most in detail
Describe.Following example are used for illustrating the present invention, but are not limited to the scope of the present invention.
First embodiment
Fig. 1 shows the system of the band buried regions groove power device that first embodiment of the invention provides
Make method, as it is shown in figure 1, the band buried regions groove power device that first embodiment of the invention provides
Manufacture method as described below.
S1, formation the first oxidation on the substrate being formed with the first epitaxial layer and the second epitaxial layer
Layer, described second epitaxial layer is positioned at above described first epitaxial layer.
In a particular application, described first epitaxial layer is N-type epitaxy layer, described second extension
Layer is p-type epitaxial layer.
In a particular application, substrate described in the present embodiment and/or described first epitaxial layer and/or institute
The substrate stating the second epitaxial layer can be monocrystal silicon etc..
S2, described first oxide layer, the second epitaxial layer and the first epitaxial layer are performed etching, shape
Become to run through the first groove of described first oxide layer, the second epitaxial layer, the end of described first groove
Portion is positioned in described first epitaxial layer.
In a particular application, this step S2 can include step S2a not shown in figure and
S2b:
S2a, carry out described first oxide layer etching for the first time, form the second groove, described
The bottom of the second groove and described second epitaxial layer upper surface.
In a particular application, above-mentioned steps S2a, may include that
The part surface of described first oxide layer is formed photoresist layer；
Using described photoresist layer as mask, carry out described first oxide layer etching for the first time,
Form the second groove, the bottom of described second groove and described second epitaxial layer upper surface.
S2b, with first time etching phase with position to described second epitaxial layer and the first extension
Layer carries out second time and etches, and forms the first ditch running through described first oxide layer, the second epitaxial layer
Groove, the bottom of described first groove is positioned in described first epitaxial layer.
In a particular application, above-mentioned steps S2b, may include that
Remove described photoresist layer；
Using the first oxide layer of the part that is not etched after etching for the first time as mask, with first
Secondary etching phase position together carries out second time and etches described second epitaxial layer and the first epitaxial layer,
Form the first groove running through described first oxide layer, the second epitaxial layer, described first groove
Bottom is positioned in described first epitaxial layer.
S3, at described first channel bottom, described first epitaxial layer is carried out p-type ion implanting,
Forming p type buried layer, described p type buried layer is positioned at above described first epitaxial layer.
S4, form the second oxide layer at described first trench wall, in described first groove second
The height of oxide layer is identical with the height of described first epitaxial layer.
S5, described second oxide layer cover the first groove in fill polysilicon, and remove
The first oxide layer, the second oxide layer and polysilicon layer higher than described second epitaxial layer.
In a particular application, the first oxygen higher than described second epitaxial layer is removed at this step S5
When changing layer, the second oxide layer and polysilicon layer, in addition to using dry etching, it is also possible to adopt
By the mode of chemically mechanical polishing (Chemical mechanical polishing, be called for short CMP),
Or, it would however also be possible to employ the mode that two kinds of methods combine, the present invention is without limitation.
In a particular application, the first oxide layer in the present embodiment step S1 can pass through hot oxygen
Metallization processes is formed, and the second oxide layer in step S4 can also be formed by thermal oxidation technology,
Described first oxide layer and described second oxide layer all can be preferably silicon oxide layer, and described
The thickness of one oxide layer is 1-10um, the top of described second oxide layer and described second extension
The height of layer lower surface is identical.
In a particular application, for example, the p-type ion implanting in the present embodiment step S3
During, described p-type ion may include that isolated son or compound ion, described isolated son
May include that hydrion, or helium ion, or boron ion, or arsenic ion, or aluminium ion etc..
And, in order to form the gate electrode of device further, after above-mentioned steps S5, also
Can include step S6 not shown in figure and S7:
Above S6, the second epitaxial layer, the second oxide layer and polysilicon layer uncovered
Form dielectric layer, and described dielectric layer is performed etching formation contact hole.
In a particular application, for example, can make with photoresist as mask, to being given an account of
Matter layer performs etching, and forms contact hole.
S7, above the dielectric layer not being etched and described contact hole formed metal level.
Can be formed through above-mentioned steps S6 and S7 can be as the metal level of gate electrode, and this gold
Belong to mutually isolated by the second oxide layer and dielectric layer between layer and above-mentioned polysilicon layer.It addition, device
Source electrode can be connected with above-mentioned polysilicon layer, and can also deposit on the opposite side surface of substrate
Layer of metal layer is as the drain electrode of device.The doping of the polysilicon that above-mentioned steps S4 is filled
Type can be N-type or p-type, but ion doping concentration should with in substrate (drain region) from
Sub-doping content is suitable, to ensure its conductive characteristic.It addition, the doping type of substrate is preferably
N-type, to ensure the device property of VDMOS.
Being substantially of the manufacture method of the band buried regions groove power device of the embodiment of the present invention: band buries
The manufacture method of the active area of layer groove power device, as shown in figure 11, Figure 11 shows use
The active area 104 of the band buried regions groove power device that the manufacture method of the embodiment of the present invention makes with
Other region (includes street area 101, cut-off ring region territory 102 and dividing potential drop region 103)
Position view.
The manufacture method of the band buried regions groove power device of the present embodiment, by being formed with first
Forming the first oxide layer on the substrate of epitaxial layer and the second epitaxial layer, the second epitaxial layer is positioned at first
Above epitaxial layer；First oxide layer, the second epitaxial layer and the first epitaxial layer are performed etching formation
Run through the first oxide layer, the first groove that the bottom of the second epitaxial layer is positioned in the first epitaxial layer；
At the first channel bottom, the first epitaxial layer is carried out the formation of p-type ion implanting and be positioned at the first epitaxial layer
The p type buried layer of top；Second identical with the first epitaxial layer height is formed at the first trench wall
Oxide layer；In the first groove that the second oxide layer covers, fill polysilicon, remove higher than second
First and second oxide layer of epitaxial layer and polysilicon layer, use deep etching to coordinate impurity to inject
Method introduces p type buried layer in N-type drift region, can improve groove power device depletion layer pressure,
Identical resistance to pressure can reduce device on-resistance, and forming the second oxide layer at channel bottom can improve
The voltage endurance capability of channel bottom corner, is substantially improved breakdown characteristic of device.
Second embodiment
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, enumerate one below more
Specific embodiment, Fig. 2 shows a kind of band buried regions groove that second embodiment of the invention provides
The schematic flow sheet of the manufacture method of power device, as in figure 2 it is shown, in the present embodiment with list
Crystal silicon as substrate, a kind of band buried regions groove power device that second embodiment of the invention provides
Manufacture method is as described below.
S10, formation in the monocrystalline substrate 1 be formed with N-type epitaxy layer 2 and p-type epitaxial layer 3
First oxide layer 4, p-type epitaxial layer 3 is positioned at above N-type epitaxy layer 2, as shown in Figure 3.
It should be noted that the selection of backing material depends primarily on the following aspects: structure is special
Property, interfacial characteristics, chemical stability, thermal property, electric conductivity, optical property and machine
Tool performance, selects to need to consider above-mentioned several aspect when substrate and corresponding epitaxial layer.Due to
Silicon is the good conductor of heat, and the heat conductivility of device is preferable, thus reaches the mesh extending device lifetime
, therefore the present embodiment illustrates as a example by monocrystalline substrate, it should be understood that,
Backing material is in addition to can being silicon (Si), it is also possible to be carborundum (SiC), gallium nitride
Or GaAs (GaAS) etc. (GaN).The N-type formed in monocrystalline substrate 1
The thickness of epitaxial layer 2 and p-type epitaxial layer 3 can be adjusted according to actual application scenarios, no
The pressure voltage size of the VDMOS device that same epitaxial thickness directly determines.Such as high pressure
Product, then epitaxy layer thickness needs to increase；For low voltage product, then need not the thickest extension
Layer.
S20, on the part surface of the first oxide layer 4 formed photoresist layer 5, by photoresist layer 5
As mask, carry out the first oxide layer 4 etching for the first time, form the second groove, described the
The bottom of two grooves and the upper surface of p-type epitaxial layer 3, as shown in Figure 4.
S30, removal photoresist layer 5, the first oxygen of the part that will not be etched after etching for the first time
Change layer 4 is as mask, in the position same with first time etching phase to p-type epitaxial layer 3 and N
Type epitaxial layer 2 carries out second time and etches, and is formed and runs through the first oxide layer 4, p-type epitaxial layer 3
The first groove, the bottom of described first groove is positioned in N-type epitaxy layer 2, such as Fig. 5 institute
Show.
S40, at described first channel bottom, N-type epitaxy layer 2 is carried out p-type ion implanting,
Forming p type buried layer 6, p type buried layer 6 is positioned at above N-type epitaxy layer 2, as shown in Figure 6.
S50, form the second oxide layer 10 at described first trench wall, in described first groove
The height of the second oxide layer 10 is identical with the height of N-type epitaxy layer 2, as shown in Figure 7.
S60, second oxide layer 10 cover the first groove in fill polysilicon 7, such as Fig. 8
Shown in.
S70, remove higher than p-type epitaxial layer 3 first oxide layer the 4, second oxide layer 10 and
Polysilicon layer 7, as shown in Figure 9.
In a particular application, whole first higher than p-type epitaxial layer 3 is removed at this step S60
When oxide layer the 4, second oxide layer 10 and polysilicon 7, in addition to using dry etching,
Chemically mechanical polishing (Chemical mechanical polishing is called for short CMP) can also be used
Mode, or, it would however also be possible to employ the mode that two kinds of methods combine, this is not done by the present invention
Limit.
S80, at uncovered p-type epitaxial layer the 3, second oxide layer 10 and polysilicon layer
The top of 7 forms dielectric layer 8, and dielectric layer 8 is performed etching formation contact hole, not by
The dielectric layer 8 of etching and the top of described contact hole form metal level 9, as shown in Figure 10.
In a particular application, the first oxide layer 4 in the present embodiment step S10 can be by heat
Oxidation technology is formed, and the second oxide layer 10 in step S50 can also pass through thermal oxidation technology
Being formed, the first oxide layer 4 and the second oxide layer 10 all can be preferably silicon oxide layer, and the
The thickness of one oxide layer 4 is 1-10um, the top of the second oxide layer 10 and p-type epitaxial layer 3
The height of lower surface is identical.
In a particular application, for example, the p-type ion implanting in the present embodiment step S40
During, described p-type ion may include that isolated son or compound ion, described isolated son
May include that hydrion, or helium ion, or boron ion, or arsenic ion, or aluminium ion etc..
It addition, the metal level 9 of device can be as gate electrode, and between metal level 9 and polysilicon layer 7
Mutually isolated by the second oxide layer 10 and dielectric layer 8, the source electrode of device can be with polysilicon layer 7
It is connected, and layer of metal layer can also be deposited as device on the opposite side surface of monocrystalline substrate 1
The drain electrode of part.
Being substantially of the manufacture method of the band buried regions groove power device of the embodiment of the present invention: band buries
The manufacture method of the active area of layer groove power device, as shown in figure 11, Figure 11 shows use
The active area 104 of the band buried regions groove power device that the manufacture method of the embodiment of the present invention makes with
Other region (includes street area 101, cut-off ring region territory 102 and dividing potential drop region 103)
Position view.
The manufacture method of the band buried regions groove power device of the present embodiment, is coordinated by deep etching
The method that impurity injects introduces p type buried layer in N-type drift region, it is possible to increase groove power
Device depletion layer is pressure, and identical resistance to pressure can reduce device on-resistance, in channel bottom shape
Become the second oxide layer can improve the voltage endurance capability of channel bottom corner, be substantially improved device and hit
Wear characteristic.
3rd embodiment
Present embodiments provide a kind of band buried regions groove power device, described band buried regions groove power
Device uses the first or two manufacture method described in embodiments to make.
The band buried regions groove power device of the present embodiment, the p type buried layer in N-type drift region can
Improving groove power device depletion layer pressure, identical resistance to pressure can reduce device on-resistance,
Second oxide layer of channel bottom can improve the voltage endurance capability of channel bottom corner, significantly changes
Kind breakdown characteristic of device.
In describing the invention it should be noted that term " top " etc. instruction orientation or
Position relationship is based on orientation shown in the drawings or position relationship, is for only for ease of and describes this
Bright and simplification describes rather than indicates or imply that the device of indication or element must have specifically
Orientation, with specific azimuth configuration and operation, be therefore not considered as limiting the invention.
Unless otherwise clearly defined and limited, term " is installed ", " being connected ", " connection " should do extensively
Reason and good sense solution, connects for example, it may be fixing, it is also possible to be to removably connect, or connect integratedly
Connect；Can be to be mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to logical
Cross intermediary to be indirectly connected to, can be the connection of two element internals.General for this area
For logical technical staff, above-mentioned term in the present invention concrete can be understood as the case may be
Implication.
Also, it should be noted in this article, the relational terms of such as first and second or the like
It is used merely to separate an entity or operation with another entity or operating space, and differs
Provisioning request or imply these entities or operation between exist any this reality relation or
Sequentially.And, term " includes ", " comprising " or its any other variant are intended to non-
Comprising of exclusiveness, so that include the process of a series of key element, method, article or set
For not only including those key elements, but also include other key elements being not expressly set out, or
Also include the key element intrinsic for this process, method, article or equipment.The most more
In the case of restriction, statement " including ... " key element limited, it is not excluded that at bag
Include and the process of described key element, method, article or equipment there is also other identical element.
It is last it is noted that various embodiments above is only in order to illustrate technical scheme,
It is not intended to limit；Although the present invention being described in detail with reference to foregoing embodiments,
It will be understood by those within the art that: it still can be to described in foregoing embodiments
Technical scheme modify, or the most some or all of technical characteristic carried out equivalent replace
Change；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the present invention's
Protective scope of the claims.
Claims (10)
1. the manufacture method of a band buried regions groove power device, it is characterised in that including:
The substrate being formed with the first epitaxial layer and the second epitaxial layer is formed the first oxide layer, institute
State the second epitaxial layer to be positioned at above described first epitaxial layer；
Performing etching described first oxide layer, the second epitaxial layer and the first epitaxial layer, formation is passed through
Wear the first groove of described first oxide layer, the second epitaxial layer, the position, bottom of described first groove
In described first epitaxial layer；
At described first channel bottom, described first epitaxial layer is carried out p-type ion implanting, formed
P type buried layer, described p type buried layer is positioned at above described first epitaxial layer；
The second oxide layer is formed, the second oxidation in described first groove at described first trench wall
The height of layer is identical with the height of described first epitaxial layer；
In the first groove that described second oxide layer covers, fill polysilicon, and removal is higher than
First oxide layer of described second epitaxial layer, the second oxide layer and polysilicon layer.
Manufacture method the most according to claim 1, it is characterised in that outside described first
Prolonging layer is N-type epitaxy layer, and described second epitaxial layer is p-type epitaxial layer.
Manufacture method the most according to claim 1, it is characterised in that described to described
First oxide layer, the second epitaxial layer and the first epitaxial layer perform etching, and are formed and run through described first
Oxide layer, the first groove of the second epitaxial layer, the bottom of described first groove is positioned at described first
In epitaxial layer, including:
Carry out described first oxide layer etching for the first time, form the second groove, described second ditch
The bottom of groove and described second epitaxial layer upper surface；
In the position same with first time etching phase, described second epitaxial layer and the first epitaxial layer are entered
Row second time etching, forms the first groove running through described first oxide layer, the second epitaxial layer,
The bottom of described first groove is positioned in described first epitaxial layer.
Manufacture method the most according to claim 3, it is characterised in that described to described
First oxide layer carries out etching for the first time, forms the second groove, the bottom of described second groove with
Described second epitaxial layer upper surface, including:
The part surface of described first oxide layer is formed photoresist layer；
Using described photoresist layer as mask, carry out described first oxide layer etching for the first time,
Form the second groove, the bottom of described second groove and described second epitaxial layer upper surface.
Manufacture method the most according to claim 4, it is characterised in that described with
Etching phase with position described second epitaxial layer and the first epitaxial layer carried out second time carve
Erosion, forms the first groove running through described first oxide layer, the second epitaxial layer, described first ditch
The bottom of groove is positioned in described first epitaxial layer, including:
Remove described photoresist layer；
Using the first oxide layer of the part that is not etched after etching for the first time as mask, with first
Secondary etching phase position together carries out second time and etches described second epitaxial layer and the first epitaxial layer,
Form the first groove running through described first oxide layer, the second epitaxial layer, described first groove
Bottom is positioned in described first epitaxial layer.
Manufacture method the most according to claim 1, it is characterised in that described first oxygen
Change layer and/or described second oxide layer is formed by thermal oxidation technology；
And/or,
Described first oxide layer and described second oxide layer are silicon oxide layer.
Manufacture method the most according to claim 1, it is characterised in that use dry method to carve
Erosion or chemically mechanical polishing are removed higher than the first oxide layer of described second epitaxial layer, the second oxygen
Change layer and polysilicon.
Manufacture method the most according to claim 1, it is characterised in that described first oxygen
The thickness changing layer is 1-10um；
And/or,
Described p-type ion includes: isolated son or compound ion, and described isolated attached bag includes: hydrogen from
Son, or helium ion, or boron ion, or arsenic ion, or aluminium ion.
9. according to the manufacture method according to any one of claim 1-8, it is characterised in that
Remove higher than the first oxide layer of described second epitaxial layer, the second oxide layer and polysilicon layer it
After, described manufacture method also includes:
Formed above the second uncovered epitaxial layer, the second oxide layer and polysilicon layer
Dielectric layer, and described dielectric layer is performed etching formation contact hole；
Metal level is formed above the dielectric layer not being etched and described contact hole.
10. a band buried regions groove power device, it is characterised in that described band buried regions groove merit
Rate device uses the manufacture method according to any one of claim 1-9 to make.
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| CN201510132292.9A CN106158631A (en) | 2015-03-25 | 2015-03-25 | Band buried regions groove power device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109427884A (en) * | 2017-08-23 | 2019-03-05 | 深圳市敦为技术有限公司 | A kind of manufacturing method of dual buried layer groove power device |
| CN112531026A (en) * | 2019-09-17 | 2021-03-19 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | Electrostatic protection chip based on power management and preparation method thereof |
| CN116435335A (en) * | 2023-03-22 | 2023-07-14 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field shielding protection structure and preparation method |
| CN118073423A (en) * | 2024-04-17 | 2024-05-24 | 深圳市冠禹半导体有限公司 | Silicon carbide trench gate MOSFET device and method of making same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109427884A (en) * | 2017-08-23 | 2019-03-05 | 深圳市敦为技术有限公司 | A kind of manufacturing method of dual buried layer groove power device |
| CN112531026A (en) * | 2019-09-17 | 2021-03-19 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor device and manufacturing method thereof |
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| CN116435335A (en) * | 2023-03-22 | 2023-07-14 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field shielding protection structure and preparation method |
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| CN118073423A (en) * | 2024-04-17 | 2024-05-24 | 深圳市冠禹半导体有限公司 | Silicon carbide trench gate MOSFET device and method of making same |
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