CN110391302A - Using the super node MOSFET structure and production method of shield grid - Google Patents
Using the super node MOSFET structure and production method of shield grid Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 210000000746 body region Anatomy 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 112
- 238000010586 diagram Methods 0.000 description 11
- 238000000407 epitaxy Methods 0.000 description 8
- 230000001413 cellular effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Abstract
The present invention relates to the manufacturing technology fields for belonging to semiconductor devices, specifically a kind of super node MOSFET structure and production method using shield grid, the MOSFET using shield grid superjunction includes: semiconductor substrate, the semiconductor substrate includes the first conductivity type substrate layer and epitaxial layer, the epitaxial layer is set on the first conductivity type substrate layer, X is offered on the epitaxial layer to first groove side by side, the first groove extends along Y-direction, the first groove is divided into upper and lower part, the first groove lower part is shielding grid region, top is gate regions, it is separated between shielding grid region and the gate regions by oxide layer；The shielding grid region includes shield grid and the shielding gate oxide positioned at the shield grid two sides and bottom surface, and the gate regions include grid polycrystalline silicon and the gate oxide positioned at the grid polycrystalline silicon two sides.The device becomes a three-dimensional charge balance device, can be while raising reduces pressure resistance, adjusting means dynamic characteristic.
Description
Technical field
The present invention relates to a kind of MOSFET structure and its manufacturing method, specifically a kind of super node MOSFET using shield grid
Structure and production method belong to the manufacturing technology field of semiconductor devices.
Background technique
Traditional N-type MOSFET structure, there are two disadvantages: one is to only exist the area Y-direction Ji CongPXing Ti in pressure resistance
It is exhausted between N-type epitaxy layer, so needing very thick high resistant N-type epitaxy layer to bear voltage, this will increase drift zone resistance
(i.e. N-type epitaxy layer resistance).The other is since lateral dimension is larger, so using planar gate structure, but between the area PXing Ti
There are an areas JFET, have biggish JFET resistance.Thus there is super node MOSFET structure and trench gate structure, however it is existing
Some groove grid super node node MOSFETs still have Railway Project:
1) it is that trench gate bottom still can have stronger electric field concentration, will affect breakdown voltage；
2) be trench bottom oxidization layer be it is thick as grid oxygen, so gate leakage capacitance Cgd is directly determined by grid oxygen, be not easy to adjust
Section；
It 3) is the Ppillar structure introduced and Trench Gate structure all in X-direction, it is desirable to further decrease lateral dimension just
It is restricted very much.
Summary of the invention
In order to solve the deficiencies in the prior art, the present invention provides a kind of MOSFET structure using shield grid superjunction
And production method, the MOSFET structure and production method using shield grid superjunction become a three-dimensional charge balance device,
The concentration of N-type epitaxy layer can be improved to the greatest extent, reduce device resistance.
The technical solution provided according to the present invention, as the first aspect of the present invention:
A kind of MOSFET using shield grid superjunction is provided, the MOSFET using shield grid superjunction includes: semiconductor substrate,
The semiconductor substrate includes the first conductivity type substrate layer and epitaxial layer, and the epitaxial layer is served as a contrast set on first conduction type
On bottom, the upper surface of the epitaxial layer is the first surface of semiconductor substrate, and the lower surface of epitaxial layer is semiconductor substrate
Second surface；
X is offered on the epitaxial layer to first groove side by side, the first groove extends along Y-direction, the first groove point
For upper and lower part, the first groove lower part is shielding grid region, and top is gate regions, between shielding grid region and the gate regions
It is separated by oxide layer；The shielding grid region includes shield grid and the shielding gate oxidation positioned at the shield grid two sides and bottom surface
Layer, the gate regions include grid polycrystalline silicon and the gate oxide positioned at the grid polycrystalline silicon two sides；
The second conductivity type body region is equipped in epitaxial layer between the first groove, second conductivity type body region is equipped with
First conductive type source area, the first interarea of the semiconductor substrate are equipped with insulating medium layer, in the insulating medium layer
Equipped with source contact openings, metal is filled in the source contact openings, the insulating medium layer is equipped with source metal, described
Source metal is connect by the metal in the source contact openings with the second conductivity type body region, and with the first conduction type source
Polar region Ohmic contact.
Further, the epitaxial layer includes connected or the first conductive type epitaxial layer being linked together and the second conductive-type
Type epitaxial layer, first conductive type epitaxial layer and the second conductive type epitaxial layer are alternately arranged in Z-direction.
Further, it is described shielding gate oxide with a thickness of 3000A ~ 10000A.
Further, the gate oxide with a thickness of 500A ~ 1000A.
Further, for N-type MOS device, first conduction type is that N-type is conductive, and second conduction type is P
Type is conductive；For p-type MOS device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
As a second aspect of the invention:
A kind of MOSFET production method using shield grid superjunction, the MOSFET production method using shield grid superjunction are provided
Specifically includes the following steps:
S1: providing the first conduction type doped substrate, grows in the first conduction type doped substrate and is connected or is linked as
The first conductive type epitaxial layer and the second conductive type epitaxial layer of one, first conductive type epitaxial layer and the second conduction
Type epitaxial layer is alternately arranged in Z-direction；
S2: performing etching the first interarea of semiconductor substrate, forms X in the epitaxial layer to first groove side by side, and described the
One groove extends along Y-direction；
S3: hot oxide growth technique is used, the first oxide layer is grown on the surface of first groove；
S4: the depositing polysilicon in the first groove, and polysilicon carve, only retain the polycrystalline of first groove lower part
Silicon forms shield grid；
S5: etching away the first oxide layer of first groove upper face, retains the first oxide layer shape of first groove lower surface
At shielding gate oxide；
S6: the second oxide layer is grown in first groove top side surface and shield grid upper surface；
S7: depositing polysilicon in the first groove top, and polysilicon carve and forms grid polycrystalline silicon, the grid
The two sides of polysilicon are gate oxide；
S8: the second conductive type impurity is first injected between two first grooves and forms the second conductivity type body region, described the
The first conductive type impurity is reinjected on two conductivity type body regions forms the first conductive type source area；
S9: depositing insulating medium layer on the first interarea, perform etching to insulating medium layer, above the second conductivity type body region
Form the source contact openings of the first conductive type source area of break-through；
S10: filling metal in source contact openings, and perform etching to metal, forms source metal.
Further, step described in S1 specifically includes:
S110: providing the first conduction type doped substrate, and the first conduction is grown in the first conduction type doped substrate
Type epitaxial layer:
S120: in the first conductive type epitaxial layer, second groove is etched in X direction, second groove is arranged at Z-direction interval
Column；
S130: growing the second conductive type epitaxial layer in the second groove, to form the first conductive type epitaxial layer
With the second conductive type epitaxial layer in Z-direction alternately arranged epitaxial layer structure.
Further, it is described shielding gate oxide with a thickness of 3000A ~ 10000A.
Further, it is described shielding gate oxide with a thickness of 500A ~ 1000A.
Further, for N-type MOS device, first conduction type is that N-type is conductive, and second conduction type is P
Type is conductive；For p-type MOS device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
It can be seen that the MOSFET structure and production method provided by the invention using shield grid superjunction from the above,
Have following advantages compared with prior art: compared with prior art, it is conductive that the present invention forms alternately arranged first in Z-direction
Type epitaxial layer and the second conductive type epitaxial layer, to form a kind of super-junction structure, and the present invention in X to by traditional ditch
Slot grid are transformed to shielded gate structures, i.e., using thick oxide layer (shielding gate oxide) and discrete screen in first groove lower part
Cover grid, thus X to constitute shield grid ← → oxide layer ← → epitaxial layer MOS structure；Above structure have the advantage that from
And make device can occur Y-direction (area PXing Ti ← → epitaxial layer) simultaneously exhausts in practical pressure resistance, Z-direction (N-type epitaxy layer ← →
P-type epitaxial layer) it exhausts, X is exhausted to the MOS of (shield grid ← → oxide layer ← → epitaxial layer), and device becomes a three-dimensional charge
Balancing device can improve the concentration of N-type epitaxy layer to the greatest extent, reduce device resistance.
In addition, thicker shielding gate oxide (with a thickness of 3000A ~ 10000A), can reduce the electricity of first groove bottom
Field concentration problem, and make gate leakage capacitance Cgd separately adjustable, so as to improve the dynamic characteristic of device.
Finally, due to shielded gate structures and super-junction structure respectively X to and Z-direction, therefore be different from conventional trench gate superjunction
MOSFET can utmostly improve cellular density so that the diminution of device size is no longer influenced by the limitation of structure.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of first aspect present invention.
Fig. 2 is the structural schematic diagram in second aspect of the present invention after S110 process.
Fig. 3 is the structural schematic diagram in second aspect of the present invention after S130 process.
Fig. 4 is the structural schematic diagram in second aspect of the present invention after S2 process.
Fig. 5 is the structural schematic diagram in second aspect of the present invention after S3 process.
Fig. 6 is the structural schematic diagram of depositing polysilicon during S4 in second aspect of the present invention.
Fig. 7 is that polysilicon carries out back carving the structural schematic diagram for forming shield grid during S4 in second aspect of the present invention.
Fig. 8 is the structural schematic diagram in second aspect of the present invention after S5 process.
Fig. 9 is the structural schematic diagram in second aspect of the present invention during S7 after depositing polysilicon.
Figure 10 is that the structure that polysilicon carve after forming grid polycrystalline silicon during S7 in second aspect of the present invention is shown
It is intended to.
Figure 11 is the structural schematic diagram in second aspect of the present invention after S9 process.
Figure 12 is the structural schematic diagram in second aspect of the present invention after S10 process.
1. the first conductivity type substrate layer, 2. epitaxial layers, 210. first conductive type epitaxial layers, 220. second is conductive
Type epitaxial layer, 3. first grooves, 310. first oxide layers, 320. second oxide layers, 4. shielding grid regions, 410. shieldings
Grid, 420. cover gate oxide, 5. gate regions, 510. grid polycrystalline silicons, 520. gate oxides, 6. second conduction type bodies
Area, 7. first conductive type source areas, 8. insulating medium layers, 9. source contact openings, 10. source metals.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.Wherein identical components are presented with like reference characters.It needs to illustrate
It is that word "front", "rear" used in the following description, "left", "right", "up" and "down" refer to the direction in attached drawing.It uses
Word "inner" and "outside" refer respectively to the direction towards or away from geometric center of specific component.
It is following for ease of description that solid space is divided into X to, Y-direction and Z-direction, it is laterally as shown in drawings defined
X is to longitudinal is defined Y-direction, to the direction with plane where Y-direction is Z-direction perpendicular to X.
Existing MOS structure includes cellular region and terminal protection area, and the cellular region is located at the center of device, the end
End protection zone is looped around around the cellular region, and the cellular region is formed in parallel by several MOSFET element cell cubes.This
The invention MOSFET using 410 superjunction of shield grid include: as shown in Figure 1,
Semiconductor substrate, the semiconductor substrate include the first conductivity type substrate layer 1 and epitaxial layer 2, and the epitaxial layer 2 is set to
On the first conductivity type substrate layer 1, the upper surface of the epitaxial layer 2 is the first surface of semiconductor substrate, epitaxial layer 2
Lower surface is the second surface of semiconductor substrate；And the epitaxial layer 2 includes outside the first conduction type that is connected or being linked together
Prolong layer 210 and the second conductive type epitaxial layer 220, first conductive type epitaxial layer 210 and the second conductive type epitaxial layer
220 are alternately arranged in Z-direction；Preferably, the first conductivity type substrate layer 1 is n-type doping substrate, first conductive-type
Type epitaxial layer 210 is N-type epitaxy layer 2, and second conductivity type substrate is p-type epitaxial layer 2；
X is offered on the epitaxial layer 2 to first groove 3 side by side, the first groove 3 extends along Y-direction, the first groove
3 points are upper and lower part, and 3 lower part of first groove is shielding grid region 4, and top is gate regions 5, the shielding grid region 4 and grid
It is separated between polar region 5 by oxide layer；
The shielding grid region 4 includes shield grid 410 and the shielding gate oxide 420 positioned at 410 two sides of shield grid and bottom surface,
The gate regions 5 include grid polycrystalline silicon 510 and the gate oxide 520 positioned at 510 two sides of grid polycrystalline silicon；Preferably,
The shielding gate oxide 420 with a thickness of 3000A ~ 10000A, the gate oxide 520 with a thickness of 500A ~ 1000A.
The second conductivity type body region 6, the second conduction type body are equipped in epitaxial layer 2 between the first groove 3
Area 6 is equipped with the first conductive type source area 7, and the first interarea of the semiconductor substrate is equipped with insulating medium layer 8, described exhausted
It is equipped with source contact openings 9 in edge dielectric layer 8, is filled with metal in the source contact openings 9, the insulating medium layer 8 is equipped with
Source metal 10, the source metal 10 is connected by the metal in the source contact openings 9, and the source contact openings
9 extend to the second conductivity type body region 6, and contact with the first conductive type source area 7, so that the source metal 10 passes through
The source contact openings 9 are connect with the second conductivity type body region 6, and with 7 Ohmic contact of the first conductive type source area；It is preferred that
Ground, first conductive type source area 7 are N-type source region, and second conductivity type body region 6 is the area PXing Ti.
As a second aspect of the invention, a kind of MOSFET production method using 410 superjunction of shield grid is provided, as Fig. 2 ~
Shown in Figure 12, the MOSFET production method using 410 superjunction of shield grid the following steps are included:
S1: providing the first conduction type doped substrate, grows in the first conduction type doped substrate and is connected or is linked as
The first conductive type epitaxial layer 210 and the second conductive type epitaxial layer 220 of one, first conductive type epitaxial layer 210
It is alternately arranged in Z-direction with the second conductive type epitaxial layer 220；
S2: performing etching the first interarea of semiconductor substrate, and formation X is described to first groove 3 side by side in epitaxial layer 2
First groove 3 extends along Y-direction, so that first groove 3 sequentially passes through alternately arranged first conductive type epitaxial layer 210 and second
Conductive type epitaxial layer 220；
S3: hot oxide growth technique is used, the first oxide layer 310 is grown on the surface of first groove 3；
S4: the depositing polysilicon in the first groove 3, and polysilicon carve, only retain the more of 3 lower part of first groove
Crystal silicon forms shield grid 410；
S5: etching away the first oxide layer 310 of 3 upper face of first groove using wet-etching technology, retains under first groove 3
First oxide layer 310 on portion surface forms shielding gate oxide 420, the shielding gate oxide 420 with a thickness of 3000A ~
10000A；
S6: growing the second oxide layer 320 in the 3 top side surface of first groove and 410 upper surface of shield grid, and described second
Oxide layer 320 with a thickness of 500A ~ 1000A；
S7: the depositing polysilicon in 3 top of first groove, and polysilicon carve and forms grid polycrystalline silicon 510, institute
The two sides for stating grid polycrystalline silicon 510 are gate oxide 520；
S8: under the blocking of graphical photolithography plate, the second conductive type impurity is first injected between two first grooves 3 and forms the
Two conductivity type body regions 6 reinject the first conductive type impurity on second conductivity type body region 6 and form the first conductive-type
Type source area 7；
S9: insulating medium layer 8 is deposited on the first interarea, insulating medium layer 8 is performed etching, in the second conductivity type body region 6
The source contact openings 9 of top formation the first conductive type source area of break-through 7；
S10: filling metal in source contact openings 9, and perform etching to metal, forms source metal 10.
For S1: providing the first conduction type doped substrate, grow phase in the first conduction type doped substrate
Even or the first conductive type epitaxial layer 210 and the second conductive type epitaxial layer 220 that are linked together, outside first conduction type
Prolong layer 210 and the second conductive type epitaxial layer 220 is alternately arranged in Z-direction, specific steps include:
S110: providing the first conduction type doped substrate, and the first conduction is grown in the first conduction type doped substrate
Type epitaxial layer 210:
S120: in the first conductive type epitaxial layer 210, second groove is etched in X direction, second groove is at Z-direction interval
Arrangement；Deep first groove is alternatively arranged in Z-direction, and spacing is designed according to device property；
S130: growing the second conductive type epitaxial layer 220 in the second groove, to form the first conduction type extension
Layer 210 and the second alternately arranged 2 structure of epitaxial layer in Z-direction of conductive type epitaxial layer 220.
Compared with prior art, the present invention forms alternately arranged first conductive type epitaxial layer 210 and second in Z-direction
Conductive type epitaxial layer 220, to form a kind of super-junction structure, and the present invention changes in X to by traditional 3 grid of first groove
At 410 structure of shield grid, i.e., using thick oxide layer (shielding gate oxide 420) and discrete screen in 3 lower part of first groove
Cover grid 410, thus X to constitute shield grid 410 ← → oxide layer ← → epitaxial layer 2 MOS structure；Above structure has following
Advantage: so that device can occur Y-direction (area PXing Ti ← → epitaxial layer 2) simultaneously and exhaust, Z-direction is (outside N-type in practical pressure resistance
Prolong layer 2 ← → p-type epitaxial layer 2) exhaust, X is exhausted to the MOS of (shield grid 410 ← → oxide layer ← → epitaxial layer 2), device at
For a three-dimensional charge balance device, the concentration of N-type epitaxy layer 2 can be improved to the greatest extent, reduce device resistance.
In addition, thicker shielding gate oxide 420(is with a thickness of 3000A ~ 10000A), it can reduce 3 bottom of first groove
Electric field concentration problem, and make gate leakage capacitance Cgd separately adjustable, so as to improve the dynamic characteristic of device.
Finally, due to 410 structure of shield grid and super-junction structure respectively X to and Z-direction, therefore be different from traditional first groove
3 grid super node MOSFETs can utmostly improve cellular density so that the diminution of device size is no longer influenced by the limitation of structure.
It should be understood by those ordinary skilled in the art that: the above is only a specific embodiment of the present invention, and
It is not used in the limitation present invention, all any modification, equivalent substitution, improvement and etc. within purport of the invention, done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of MOSFET using shield grid superjunction, which is characterized in that the MOSFET using shield grid superjunction includes: half
Conductor substrate, the semiconductor substrate include the first conductivity type substrate layer (1) and epitaxial layer (2), and the epitaxial layer (2) is set to
On the first conductivity type substrate layer (1), the upper surface of the epitaxial layer (2) is the first surface of semiconductor substrate, extension
The lower surface of layer (2) is the second surface of semiconductor substrate；
X is offered on the epitaxial layer (2) to first groove (3) side by side, the first groove (3) extends along Y-direction, and described the
One groove (3) is divided into upper and lower part, and first groove (3) lower part is shielding grid region (4), and top is gate regions (5), described
It is separated between shielding grid region (4) and gate regions (5) by oxide layer；The shielding grid region (4) includes shield grid (410) and is located at
The shielding gate oxide (420) of shield grid (410) two sides and bottom surface, the gate regions (5) include grid polycrystalline silicon (510)
With the gate oxide (520) for being located at the grid polycrystalline silicon (510) two sides；
The second conductivity type body region (6) are equipped in epitaxial layer (2) between the first groove (3), second conduction type
Body area (6) is equipped with the first conductive type source area (7), and the first interarea of the semiconductor substrate is equipped with insulating medium layer
(8), source contact openings (9) are equipped in the insulating medium layer (8), metal is filled in the source contact openings (9), it is described exhausted
Edge dielectric layer (8) is equipped with source metal (10), and the source metal (10) passes through the gold in the source contact openings (9)
Category connect with the second conductivity type body region (6), and with the first conductive type source area (7) Ohmic contact.
2. using the MOSFET of shield grid superjunction as described in claim 1, which is characterized in that the epitaxial layer (2) includes phase
The first conductive type epitaxial layer (210) and the second conductive type epitaxial layer (220) for connecting or being linked together, first conductive-type
Type epitaxial layer (210) and the second conductive type epitaxial layer (220) are alternately arranged in Z-direction.
3. using the MOSFET of shield grid superjunction as described in claim 1, which is characterized in that the shielding gate oxide
(420) with a thickness of 3000A ~ 10000A.
4. using the MOSFET of shield grid superjunction as described in claim 1, which is characterized in that the gate oxide (520)
With a thickness of 500A ~ 1000A.
5. the MOSFET using shield grid superjunction as described in any one in Claims 1-4, which is characterized in that for N-type
MOS device, first conduction type are that N-type is conductive, and second conduction type is P-type conduction；For p-type MOS device, institute
Stating the first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
6. a kind of MOSFET production method using shield grid superjunction, which is characterized in that described using shield grid superjunction
MOSFET production method specifically includes the following steps:
S1: providing the first conduction type doped substrate, grows in the first conduction type doped substrate and is connected or is linked as
The first conductive type epitaxial layer (210) and the second conductive type epitaxial layer (220) of one, first conductive type epitaxial layer
(210) it is alternately arranged in Z-direction with the second conductive type epitaxial layer (220)；
S2: performing etching the first interarea of semiconductor substrate, X is formed in the epitaxial layer (2) to first groove (3) side by side,
The first groove (3) extends along Y-direction；
S3: hot oxide growth technique is used, the first oxide layer (310) are grown on the surface of first groove (3)；
S4: the depositing polysilicon in the first groove (3), and polysilicon carve, only retain first groove (3) lower part
Polysilicon formed shield grid (410)；
S5: etching away first oxide layer (310) of first groove (3) upper face, retains the of first groove (3) lower surface
One oxide layer (310) forms shielding gate oxide (420)；
S6: the second oxide layer (320) are grown in the first groove (3) top side surface and shield grid (410) upper surface；
S7: depositing polysilicon in first groove (3) top, and polysilicon carve and forms grid polycrystalline silicon (510),
The two sides of the grid polycrystalline silicon (510) are gate oxide (520)；
S8: first injecting the second conductive type impurity between two first grooves (3) and form the second conductivity type body region (6), In
The first conductive type impurity is reinjected on second conductivity type body region (6) forms the first conductive type source area (7)；
S9: insulating medium layer (8) are deposited on the first interarea, insulating medium layer (8) are performed etching, in the second conduction type body
The source contact openings (9) of the first conductive type source area of break-through (7) are formed above area (6)；
S10: filling metal in source contact openings (9), and perform etching to metal, is formed source metal (10).
7. using the MOSFET production method of shield grid superjunction as claimed in claim 6, which is characterized in that step described in S1
Suddenly it specifically includes:
S110: providing the first conduction type doped substrate, and the first conduction is grown in the first conduction type doped substrate
Type epitaxial layer (210):
S120: in the first conductive type epitaxial layer (210), second groove is etched in X direction, second groove is between Z-direction
Every arrangement；
S130: growing the second conductive type epitaxial layer (220) in the second groove, to be formed outside the first conduction type
Prolong layer (210) and the second conductive type epitaxial layer (220) alternately arranged epitaxial layer (2) structure in Z-direction.
8. using the MOSFET production method of shield grid superjunction as claimed in claim 6, which is characterized in that the shielding grid oxygen
Change layer (420) with a thickness of 3000A ~ 10000A.
9. using the MOSFET production method of shield grid superjunction as claimed in claim 6, which is characterized in that the shielding grid oxygen
Change layer (420) with a thickness of 500A ~ 1000A.
10. the MOSFET production method using shield grid superjunction as described in any bar in claim 6 ~ 9, which is characterized in that
For N-type MOS device, first conduction type is that N-type is conductive, and second conduction type is P-type conduction；For p-type MOS
Device, first conduction type are P-type conduction, and second conduction type is that N-type is conductive.
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