CN109461769A - A kind of trench gate IGBT device structure and preparation method thereof - Google Patents
A kind of trench gate IGBT device structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000001301 oxygen Substances 0.000 claims abstract description 30
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 210000000746 body region Anatomy 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 29
- 238000000407 epitaxy Methods 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 230000026267 regulation of growth Effects 0.000 claims description 2
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The invention belongs to the manufacturing technology fields of semiconductor devices, it is related to a kind of trench gate IGBT device structure, IGBT device unit includes the first conductivity type substrate, the first conductive type epitaxial layer in the first conductivity type substrate and the first conductive type epitaxial layer under the first conductivity type substrate, several gate grooves are equipped in the first conductive type epitaxial layer, the depth of gate groove is consistent with the adjacent junction depth of the second conductivity type body region in left and right, in gate groove filled with grid polycrystalline silicon and on the outside of grid polycrystalline silicon and be close to gate trench sidewall gate oxide, inverted trapezoidal thickness oxygen slot is equipped with below gate groove, inverted trapezoidal thickness oxygen slot is deep into the first conductive type epitaxial layer；The present invention can enhance the electron injection amount of emitter region, and then reduce conduction voltage drop Vceon by the way that inverted trapezoidal thickness oxygen slot is arranged in channel bottom, improve conduction loss when device work, gate leakage capacitance Cgd can be reduced simultaneously, and then reduces feedback capacity Crss, reduce the switching loss of device.
Description
Technical field
The present invention relates to a kind of IGBT device structure and preparation method thereof, specifically a kind of trench gate IGBT device structure and
Its production method belongs to the manufacturing technology field of semiconductor devices.
Background technique
Compared to MOSFET element, the conductivity modulation effect of the drift region IGBT can greatly reduce forward conduction voltage drop
Vceon, static power consumption is smaller, and the higher performance of voltage is all the more significant.Thus, IGBT is occupied very in mesohigh application
The big market share.IGBT mainly has tri- kinds of punch PT- IGBT, non-punch NPT- IGBT and field cut-off type FS-IGBT
Structure, the main difference between three are different substrate PN junction structure (P+ and Nbuffer) and different drift regions (N-EPI)
Thickness.For opposite PT-IGBT and NPT-IGBT, FS-IGBT has most thin drift region thickness, and forward conduction voltage drop obtains
Apparent decline, the structure are widely used in IGBT product, as shown in Figure 1, being existing FS-IGBT device list
The schematic cross-sectional view of member.But with the continuous improvement of semiconductor die size, the limitation such as cost, complex process, fragment rate
IGBT(especially low pressure IGBT) performance continuous promotion, that how in the case where not influencing device other parameters further
The conduction voltage drop for reducing FS-IGBT device is the urgent problem being faced with.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, provide a kind of trench gate IGBT device structure and its
Production method can enhance the electron injection amount of emitter region, and then reduce and lead by the way that inverted trapezoidal thickness oxygen slot is arranged in channel bottom
Logical pressure drop Vceon improves conduction loss when device work, while can reduce gate leakage capacitance Cgd, and then reduces feedback capacity
Crss reduces the switching loss of device.
To realize the above technical purpose, the technical scheme is that a kind of trench gate IGBT device structure, active area
Including several IGBT device units, the IGBT device unit includes the first conductivity type substrate, is located at the first conduction type
The first conductive type epitaxial layer on substrate and the first conductive type epitaxial layer under the first conductivity type substrate, feature
It is, several gate grooves, the depth of the gate groove and the second of left and right adjoining is equipped in the first conductive type epitaxial layer
The junction depth of conductivity type body region is consistent, and grid polycrystalline silicon is filled in gate groove and is located on the outside of grid polycrystalline silicon and is close to grid
The gate oxide of trenched side-wall, is equipped with inverted trapezoidal thickness oxygen slot below the gate groove, and inverted trapezoidal thickness oxygen slot is deep into first and leads
In electric type epitaxial layer.
Further, the first conduction type source region, and the first conduction type are equipped in second conductivity type body region
Source region and gate groove are adjacent, and insulating medium layer is equipped on the gate groove, and insulating medium layer is equipped with source metal, the source
Pole metal pass through insulating medium layer respectively with the second conductivity type body region, the first conduction type source region Ohmic contact.
Further, the angle between the side wall and bottom of the inverted trapezoidal thickness oxygen slot is less than 80 °, and inverted trapezoidal thickness oxygen slot
With a thickness of 1.8um ~ 2.2um.
In order to further realize the above technical purpose, the present invention also proposes a kind of production side of trench gate IGBT device structure
Method, characterized in that include the following steps:
Step 1: the first conduction type silicon substrate is chosen, is led using epitaxy technique first as the first conductivity type substrate
One conductive type epitaxial layer of electric type substrates upper surface growth regulation, the upper surface of first conductive type epitaxial layer are first main
Face, the lower surface of the first conductivity type substrate are the second interarea；
Step 2 injects the second conductive type ion on the first interarea, then pushes away trap, forms the second conductivity type body region；
Step 3 is under the blocking of graphical mask blank, and Selective implantation first is conductive in the second conductivity type body region
Types of ion forms the first conduction type source region；
Step 4 performs etching the first interarea under the blocking of graphical mask blank, obtains several and leads with first
The adjacent gate groove of electric type source region；
Step 5 continues to perform etching the first conductive type epitaxial layer, and controls etching angle, obtains below gate groove
Inverted trapezoidal groove；
Step 6 deposited oxide layer in inverted trapezoidal groove obtains inverted trapezoidal thickness oxygen slot；
Step 7 continues deposited oxide layer and polysilicon in the gate groove above inverted trapezoidal thickness oxygen slot, and is sequentially etched polycrystalline
Silicon and oxide layer are obtained positioned at the gate oxide of gate groove inner sidewall and by the grid polycrystalline silicon of gate oxide encirclement；
Step 8 deposits insulating medium layer on the first interarea, and to insulating medium layer selective etch, obtains metal contact
Through-hole；
Step 9 on insulating medium layer and deposits metal in metal contact through hole, and performs etching to metal, obtains and the
The source metal of one conduction type source region and the second conductivity type body region Ohmic contact；
Step 10 carries out the second interarea thinned, and the second conductive type ion is injected on the second interarea, obtains being located at the
Buffer layers of the first conduction type below one conductive type epitaxial layer and positioned at the of buffer layers of lower section of the first conduction type
Two conduction type hole injection layers；
Step 11 deposits metal below the second conduction type hole injection layer, obtains collector electrode metal.
Further, in the step 4, the depth of gate groove is consistent with the junction depth of the second conductivity type body region.
Further, in the step 5, during etching inverted trapezoidal groove, using dry etching, by carving
It loses and inputs protective gas in equipment, control the etching pressure of etching apparatus, while the gas become step by step in dynamic adjustment etching machine bench
Body protects atmosphere, to control etching angle and bottom pattern.
Further, in the step 5, the angle between the inverted trapezoidal trenched side-wall etched and bottom is less than
80 °, and depth is 1.8um ~ 2.2um.
Further, the IGBT device includes N-type power semiconductor and p-type power semiconductor, for N-type
Power semiconductor, first conduction type are N-type, and second conduction type is p-type, for P-type semiconductor device,
First conduction type is p-type, and the second conduction type is N-type.
Compared with existing Trench FS-IGBT device, the invention has the following advantages that
1) present invention uses the inverted trapezoidal thickness oxygen slot below gate groove and gate groove instead of existing gate groove, so that being located at P
The width of N-type epitaxy layer below the area Xing Ti increases, so that the resistance in this region increases, is injected into outside N-type when from collector
N-type epitaxy layer when prolonging the hole of floor by the area PXing Ti inflow N-type emitter (N-type source region), below the area HuiPXing Ti of hole
Accumulation.According to principle of charge conservation, N-type emitter must inject more electronics to N-type epitaxy layer by conducting channel, so that
The regional carrier concentration greatly increases, and as shown in figure 13, carrier concentration increases so that conductivity modulation effect enhances, in turn
Reduce conduction voltage drop Vceon and on-state loss；
2) due to being provided with inverted trapezoidal thickness oxygen slot below gate groove, existing structure, the oxide layer of grid polycrystalline silicon bottom are compared
Thickness increases, and thereby reduces the interelectrode capacitor of grid sum aggregate, under the conditions of not influencing side wall cut-in voltage VTH, device
Feedback capacity Crss reduces；
3) etching inclination angle and thickness of the present invention by adjusting inverted trapezoidal thickness oxygen slot below grid polycrystalline silicon is guaranteeing Vth, BV not
In the case where change, the present invention can further decrease the conduction voltage drop Vceon of Trench FS-IGBT, improve when device works
Conduction loss, while reducing feedback capacity Crss, reduce the switching loss of device；
4) the manufacturing method of the present invention is compatible with prior art, does not need to increase additional development cost.
Detailed description of the invention
The drawings are intended to provide a further understanding of the invention, and constitutes part of specification, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of tradition Trench FS-IGBT device unit.
Fig. 2 is the structural schematic diagram of the Trench FS-IGBT device unit of the embodiment of the present invention 1.
Fig. 3 is the schematic cross-sectional view that the embodiment of the present invention 1 forms N-type epitaxy layer in N-type substrate.
Fig. 4 is the schematic cross-sectional view that the embodiment of the present invention 1 forms the area PXing Ti.
Fig. 5 is the schematic cross-sectional view that the embodiment of the present invention 1 forms N-type source region.
Fig. 6 is the schematic cross-sectional view that the embodiment of the present invention 1 forms gate groove.
Fig. 7 is the schematic cross-sectional view that the embodiment of the present invention 1 forms inverted trapezoidal groove.
Fig. 8 is the schematic cross-sectional view that the embodiment of the present invention 1 forms inverted trapezoidal thickness oxygen slot.
Fig. 9 is the schematic cross-sectional view that the embodiment of the present invention 1 forms gate oxide and grid polycrystalline silicon.
Figure 10 is the schematic cross-sectional view that the embodiment of the present invention 1 forms insulating medium layer.
Figure 11 is the schematic cross-sectional view that the embodiment of the present invention 1 forms source metal.
Figure 12 is the schematic cross-sectional view that the embodiment of the present invention 1 forms N-type buffer layers and p-type hole injection layer.
Figure 13 is the Trench FS-IGBT device list of tradition Trench FS-IGBT device unit and the embodiment of the present invention 1
Carrier concentration curve graph of the member along A-A '.
Description of symbols: 1, N-type substrate；2, N-type epitaxy layer；3, gate groove；4, inverted trapezoidal thickness oxygen slot；5, the area PXing Ti；
6, grid polycrystalline silicon；7, gate oxide；8, N-type source region；9, insulating medium layer；10, source metal；11, inverted trapezoidal groove；12,N
Buffer layers of type；13, p-type hole injection layer；14, collector electrode metal；001, the first interarea；002, the second interarea.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
The present invention is not limited to the following embodiments and the accompanying drawings, and each figure of institute's reference is to be able to this hair in the following description
Bright content is understood and is arranged that is, the present invention is not limited to the device architectures that each figure is illustrated；
Embodiment 1: as shown in Fig. 2, by taking N-type trench gate IGBT device structure as an example, first conduction type is N-type, second
Conduction type is p-type, and active area includes several IGBT device units, and the IGBT device unit includes N-type substrate 1 and position
In the N-type epitaxy layer 2 in N-type substrate 1, in N-type epitaxy layer 2 be equipped with several gate grooves 3, the depth of the gate groove 3 with
The junction depth in the adjacent area PXing Ti 5 in left and right is consistent, filled with grid polycrystalline silicon 6 and outside grid polycrystalline silicon 6 in gate groove 3
Side and the gate oxide 7 for being close to 3 side wall of gate groove, are equipped with inverted trapezoidal thickness oxygen slot 4, inverted trapezoidal thickness oxygen below the gate groove 3
Slot 4 is deep into N-type epitaxy layer 2；
N-type source region 8 is equipped in the area PXing Ti 5, and N-type source region 8 and gate groove 3 are adjacent, are equipped on the gate groove 3
Insulating medium layer 9, the insulating medium layer 9 are equipped with source metal 10 and gate metal, and the source metal 10 passes through insulation
Dielectric layer 9 is respectively with the area PXing Ti 5,8 Ohmic contact of N-type source region, and the gate metal is across insulating medium layer 9 and gate polycrystalline
6 Ohmic contact of silicon, it is well known for capital and interest and technical staff here, and gate metal is not indicated in figure.
A kind of production method of trench gate IGBT device structure in embodiment as above, includes the following steps:
As shown in figure 3, step 1: N-type silicon substrate is chosen, as N-type substrate 1, using epitaxy technique, in 1 upper surface of N-type substrate
N-type epitaxy layer 2 is grown, the upper surface of the N-type epitaxy layer 2 is the first interarea 001, and the lower surface of N-type substrate 1 is the second interarea
002；
As shown in figure 4, step 2 injecting p-type ion on the first interarea 001, then pushes away trap, the area PXing Ti 5 is formed；
As shown in figure 5, step 3 is under the blocking of graphical mask blank, in the area PXing Ti 5 Selective implantation N-type from
Son forms the N-type source region 8 being located in the area PXing Ti 5, and removes graphical mask blank；
As shown in fig. 6, step 4 under the blocking of graphical mask blank, performs etching the first interarea 001, in p-type
Several gate grooves 3 adjacent with N-type source region 8, and the junction depth one of the depth of gate groove 3 and the area PXing Ti 5 are obtained between body area 5
It causes；
As shown in fig. 7, step 5 continues to perform etching N-type epitaxy layer 2, and etching angle is controlled, below gate groove 3
To inverted trapezoidal groove 11；And remove graphical mask blank；
During etching inverted trapezoidal groove 11, using dry etching, by inputting protective gas in etching apparatus, control is carved
Lose the etching pressure of equipment, while the gas shield atmosphere that becomes step by step in dynamic adjustment etching machine bench, come control etching angle and
Bottom pattern, the angle between 11 side wall of inverted trapezoidal groove etched and bottom is less than 80 °, and depth is about .2um；
As shown in figure 8, step 6 deposited oxide layer, selective etch oxygen in inverted trapezoidal groove 11 and on the first interarea 001
Change layer, retain the oxide layer in inverted trapezoidal groove 11, obtains the inverted trapezoidal thickness oxygen slot 4 being located in inverted trapezoidal groove 11, inverted trapezoidal
Angle between thick 4 side wall of oxygen slot and bottom is less than 80 °, and thickness is about 2um；
As shown in figure 9, step 7 continues deposited oxide layer and polysilicon in the gate groove 3 above inverted trapezoidal thickness oxygen slot 4, and
It is sequentially etched polysilicon and oxide layer, obtains the grid for being located at the gate oxide 7 of 3 inner sidewall of gate groove and being surrounded by gate oxide 7
Pole polysilicon 6；
As shown in Figure 10, step 8 deposits insulating medium layer 9, and selective etch insulating medium layer on the first interarea 001
9, obtain metal contact through hole；
As shown in figure 11, step 9 on insulating medium layer 9 and deposits metal in metal contact through hole, and carves to metal
Erosion, obtains the grid with the source metal 10 of 5 Ohmic contact of N-type source region 8 and the area PXing Ti and with 6 Ohmic contact of grid polycrystalline silicon
Metal (herein and being not drawn into)；
As shown in figure 12, step 10 carries out the second interarea 002 thinned, is then injected into P-type ion, obtains being located at N-type extension
The N-type buffer layer 12 and the p-type hole injection layer 13 below N-type buffer layer 12 of 2 lower section of layer；
Step 11 deposits metal below p-type hole injection layer 13, obtains collector electrode metal 14.
For existing routine Trench FS-IGBT device, the hole of N-type epitaxy layer 2 is injected into hardly from collector
N-type epitaxy layer 2 below the area PXing Ti 5 accumulates, and therefore, electronics passes through conducting channel to 2 note of N-type epitaxy layer from N-type emitter
Enter, also hardly by the N-type epitaxy layer 2 of 5 lower section of the area PXing Ti, the carrier concentration in this region not will increase, such as Figure 13 institute
Show；And the present invention uses the inverted trapezoidal thickness oxygen slot 4 of 3 lower section of gate groove 3 and gate groove instead of existing conventional gate groove, so that
Width positioned at the N-type epitaxy layer 2 of 5 lower section of the area PXing Ti increases, so that the resistance in this region increases, injects when from collector
When flowing into N-type emitter (i.e. N-type source region 8) by the area PXing Ti 5 to the hole of N-type epitaxy layer 2, under the hole area HuiPXing Ti 5
The N-type epitaxy layer 2 of side accumulates, and according to principle of charge conservation, N-type emitter must be injected by conducting channel to N-type epitaxy layer 2
More electronics, so that the regional carrier concentration greatly increases, as shown in figure 13, carrier concentration increases so that conductance modulation
Effect enhances, and thereby reduces conduction voltage drop Vceon and on-state loss；Simultaneously because being provided with ladder below gate groove 3
Shape thickness oxygen slot 4 compares existing structure, and the oxidated layer thickness of 6 bottom of grid polycrystalline silicon increases, and thereby reduces grid and collector
Between capacitor Cgd, under the conditions of not influencing side wall cut-in voltage VTH, so that the feedback capacity Crss of device reduces；
Therefore, etching inclination angle and thickness of the present invention by adjusting 6 lower section inverted trapezoidal thickness oxygen slot 4 of grid polycrystalline silicon, is guaranteeing
In the case that Vth, BV are constant, the present invention can further decrease the conduction voltage drop Vceon of Trench FS-IGBT, improve device
Conduction loss when work, while reducing feedback capacity Crss, reduce the switching loss of device.
The present invention and its embodiments have been described above, description is not limiting, it is shown in the drawings also only
It is one of embodiments of the present invention, practical structures are not limited thereto.All in all if those skilled in the art
It is enlightened by it, without departing from the spirit of the invention, is not inventively designed similar with the technical solution
Frame mode and embodiment, are within the scope of protection of the invention.
Claims (8)
1. a kind of trench gate IGBT device structure, active area includes several IGBT device units, the IGBT device unit
The first conductive type epitaxial layer (2) including the first conductivity type substrate (1) and on the first conductivity type substrate (1),
It is characterized in that, several gate grooves (3), the depth of the gate groove (3) and a left side is equipped in the first conductive type epitaxial layer (2)
The junction depth of the second conductivity type body region (5) of right adjoining is consistent, and grid polycrystalline silicon (6) are filled in gate groove (3) and are located at
Grid polycrystalline silicon (6) outside and the gate oxide (7) for being close to gate groove (3) side wall, are equipped with terraced below the gate groove (3)
Shape thickness oxygen slot (4), inverted trapezoidal thickness oxygen slot (4) are deep into the first conductive type epitaxial layer (2).
2. a kind of trench gate IGBT device structure according to claim 1, which is characterized in that in second conduction type
The first conduction type source region (8) is equipped in body area (5), and the first conduction type source region (8) and gate groove (3) are adjacent, described
Gate groove (3) is equipped with insulating medium layer (9), and the insulating medium layer (9) is equipped with source metal (10), the source metal
(10) pass through insulating medium layer (9) respectively with the second conductivity type body region (5), first conduction type source region (8) Ohmic contact.
3. a kind of trench gate IGBT device structure according to claim 1, which is characterized in that the inverted trapezoidal thickness oxygen slot
(4) angle between side wall and bottom less than 80 °, and inverted trapezoidal thickness oxygen slot (4) with a thickness of 1.8um ~ 2.2um.
4. a kind of production method of trench gate IGBT device structure, characterized in that include the following steps
Step 1: the first conduction type silicon substrate is chosen, as the first conductivity type substrate (1), using epitaxy technique, first
One conductive type epitaxial layer (2) of conductivity type substrate (1) upper surface growth regulation, first conductive type epitaxial layer (2) it is upper
Surface is the first interarea (001), and the lower surface of the first conductivity type substrate (1) is the second interarea (002)；
Step 2 injects the second conductive type ion on the first interarea (001), then pushes away trap, forms the second conduction type body
Area (5)；
Step 3 is under the blocking of graphical mask blank, in the second conductivity type body region (5) interior Selective implantation first
Conductive type ion forms the first conduction type source region (8)；
Step 4 performs etching the first interarea (001) under the blocking of graphical mask blank, obtains several and
The adjacent gate groove (3) of one conduction type source region (8)；
Step 5 continues to perform etching the first conductive type epitaxial layer (2), and controls etching angle, under gate groove (3)
Side obtains inverted trapezoidal groove (11)；
Step 6 obtains inverted trapezoidal thickness oxygen slot (4) in inverted trapezoidal groove (11) interior deposited oxide layer；
Continue deposited oxide layer and polysilicon in gate groove (3) of the step 7 above inverted trapezoidal thickness oxygen slot (4), and successively carves
Polysilicon and oxide layer are lost, is obtained positioned at the gate oxide (7) of gate groove (3) inner sidewall and by the grid of gate oxide (7) encirclement
Pole polysilicon (6)；
Step 8 deposits insulating medium layer (9) on the first interarea (001), and to insulating medium layer (9) selective etch, obtains
To metal contact through hole；
Step 9 deposits metal on insulating medium layer (9) and in metal contact through hole, and performs etching to metal, obtain with
The source metal (10) of first conduction type source region (8) and the second conductivity type body region (5) Ohmic contact；
Step 10 carries out the second interarea (002) thinned, and injects the second conductive type ion on the second interarea (002),
It obtains being located at the first conduction type buffer layers (12) below the first conductive type epitaxial layer (2) and is located at the first conduction type
The second conduction type hole injection layer (13) below buffer layers (12)；
Step 11 deposits metal below the second conduction type hole injection layer (13), obtains collector electrode metal (14).
5. a kind of production method of trench gate IGBT device structure according to claim 4, which is characterized in that the step
In four, the depth of gate groove (3) is consistent with the junction depth of the second conductivity type body region (5).
6. a kind of production method of trench gate IGBT device structure according to claim 4, which is characterized in that in the step
In rapid five, during etching inverted trapezoidal groove (11), using dry etching, by inputting protective gas in etching apparatus,
The etching pressure of etching apparatus, while the gas shield atmosphere become step by step in dynamic adjustment etching machine bench are controlled, to control etching
Angle and bottom pattern.
7. a kind of production method of trench gate IGBT device structure according to claim 4, which is characterized in that in the step
In rapid five, angle of the inverted trapezoidal groove (11) etched between side wall and bottom is less than 80 °, and depth is 1.8um ~ 2.2um.
8. a kind of trench gate IGBT device structure according to claim 1 or 4 and preparation method thereof, which is characterized in that institute
Stating IGBT device includes N-type power semiconductor and p-type power semiconductor, described for N-type power semiconductor
First conduction type is N-type, and second conduction type is p-type, and for P-type semiconductor device, the first conduction type is p-type,
Second conduction type is N-type.
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