CN109119476A - Separate gate VDMOS device and its manufacturing method with internal field plate - Google Patents
Separate gate VDMOS device and its manufacturing method with internal field plate Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 118
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000001727 in vivo Methods 0.000 claims abstract description 6
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- 238000005516 engineering process Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 4
- 238000005520 cutting process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Abstract
The present invention provides a kind of separate gate VDMOS device and its manufacturing method with internal field plate, including the first conductive type semiconductor substrate, first conductive type semiconductor source contact zone, first conductive type semiconductor drift region, second conductive type semiconductor source contact zone, second conductive type semiconductor well region, field plate in polysilicon body, gate electrode, separate gate electrodes, source metal, separate gate slot, internal field plate slot, the gate oxide medium formed in separate gate slot, first medium layer, second dielectric layer is formed in field plate slot in vivo, third dielectric layer between gate electrode and separate gate electrodes, 4th dielectric layer；The present invention is on the basis of conventional separate gate VDMOS device, internal field plate is introduced in the drift region of separate gate VDMOS device, and the two-dimentional depletion mode of original conventional device is become into three-dimensional and is exhausted, enhance device exhausts ability, the drift doping concentration of device is improved, and then reduces and compares conducting resistance.
Description
Technical field
The invention belongs to power semiconductor fields.The present invention mainly proposes a kind of separate gate with internal field plate
VDMOS and its manufacturing method by introducing the depletion mode that internal field plate changes device in cellular, and then improve static characteristic.
Background technique
Relative to conventional VDMOS device, the VDMOS device with separate gate structures has more excellent because of the introducing of separate gate
Performance.Compared with conventional VDMOS device, the separate gate of introducing with source electrode are shorted, may be regarded as internal field plate, exhausted by MOS
Mode drift region electric field is modulated, allow identical resistance to pressure drift region concentration higher, it is lower than conducting resistance.Separately
On the one hand, due to the presence of separate gate, the capacitor between grid and drain electrode is shielded, therefore separated bar part has lower grid electricity
Lotus.It is exhausted, can be exhausted two dimension by introducing internal field plate by introducing the newly-increased lateral MOS of separate gate in conventional VDMOS device
Become three-dimensional to exhaust, drift region concentration during advanced optimizing.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of separation with internal field plate
Grid VDMOS device and its manufacturing method.
For achieving the above object, technical solution of the present invention is as follows:
A kind of separate gate VDMOS device with internal field plate, including the first conductive type semiconductor substrate 110, first
Conductive type semiconductor drift region 112, the second conductive type semiconductor well region 122, the first conductive type semiconductor source contact zone
111, the second conductive type semiconductor source contact zone 121, source metal 140, separate gate slot 161, internal field plate slot 162 are dividing
From the gate electrode 131 being formed by polysilicon formed in grid slot 161, the separate gate electrodes 132, the gate oxide that are formed by polysilicon
Third dielectric layer 153 between medium 150, first medium layer 151, gate electrode 131 and separate gate electrodes 132, in vivo field plate
Field plate 130 in the second dielectric layer 152 and polysilicon body formed in slot 162, the 4th dielectric layer 154；
Field plate 130 protrudes into the drift of the first conductive type semiconductor in the second dielectric layer 152 and polysilicon body realized by grooving
It moves in area 112, second dielectric layer 152 surrounds field plate 130 in polysilicon body；First conductive type semiconductor substrate 110 is heavily doped
It is miscellaneous, 121 heavy doping of the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone；Source electrode gold
Belong to 140 to be shorted the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone 121, and covers
Field plate 130 in polysilicon body are covered, internal 162 upper surface of field plate slot is surrounded by the second conductive type semiconductor source contact zone 121,
Internal field plate slot 162 periodically occurs in front-rear direction.
It is preferred that source metal 140 deposits metal shape by etching after surface silicon between internal field plate slot 162
At, source metal 140 by the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone 121
It is shorted, source metal 140 stretches in the first conductive type semiconductor drift region 112, internal field plate slot 162 and source metal
140 are alternately present in front-rear direction.
It is preferred that the depth of separate gate slot 161 is less than the depth of internal field plate slot 162.
It is preferred that internal field plate slot 162 protrudes into the first conductive type semiconductor substrate 110.
It is preferred that separate gate slot 161 and internal field plate slot 162 protrude into the first conductive type semiconductor substrate
110。
For achieving the above object, the present invention also provides a kind of systems of separate gate VDMOS device with internal field plate
Method is made, comprising steps of
(a) drift of device is formed by epitaxy technique in given first kind conductive type semiconductor material substrate on piece
Area forms separate gate slot 161 and internal field plate slot 162 by deep etching technique using mask plate on this basis；
(b) on the basis of (a), first medium layer 151 required for being formed simultaneously by thermally grown or depositing technics
With second dielectric layer 152, then polysilicon filled up in slot inner medium layer by depositing technics, exposure mask is utilized by etching polysilicon
Version falls the etching polysilicon in separate gate slot 161, to form separate gate electrodes 132, and etches away 161 top of separate gate slot
The dielectric layer divided；
(c) on the basis of (b), by deposit or thermally grown dielectric layer and etch media layer, separate gate slot 161 is formed
Third dielectric layer 153 between interior separate gate electrodes 132 and gate electrode, then gate oxide medium is formed by thermal oxidation technology
150, then deposit simultaneously CMP polysilicon and form gate electrode 131, and carry out surface C MP；
(d) on the basis of (c), using self-registered technology, the second conductive type semiconductor impurity is injected, and knot is formed
Second conductive type semiconductor well region 122 is used as channel；
(e) it on the basis of (d), successively injects the first conductive type semiconductor impurity and the second conductive type semiconductor is miscellaneous
Matter forms the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone 121, wherein first
Conductive type impurity is injected by self-registered technology, and the second conductive type impurity is injected using mask plate；Medium conduct is deposited again
4th dielectric layer 154, and etch the 4th dielectric layer and filling metal or polysilicon formed gate electrode and source electrode contact metal or
Polysilicon, the surface CMP form the separate gate VDMOS device with internal field plate after contacting metal or polysilicon.
For achieving the above object, the present invention also provides a kind of systems of separate gate VDMOS device with internal field plate
Method is made, separate gate slot 161 and being formed in actual process for internal field plate slot 162 use different mask plates；Internal field plate slot
The first medium layer 151 in second dielectric layer 152 and separate gate slot 161 in 162 is formed or is passed through thermally grown shape by deposit
At.
For achieving the above object, the present invention also provides a kind of systems of separate gate VDMOS device with internal field plate
Method is made, the third dielectric layer 153 between separate gate electrodes 132 and control gate 131 is same using the formation of gate oxide medium 150
Shi Shengchang is formed.
It is preferred that first kind conductive type semiconductor is N-type, the second class conductive type semiconductor is p-type, or
First kind conductive type semiconductor is p-type, and the second class conductive type semiconductor is N-type.
It is preferred that its semiconductor of the device is silicon or silicon carbide.
The invention has the benefit that the present invention is on the basis of conventional separate gate VDMOS device, in separate gate VDMOS
Internal field plate is introduced in the drift region of device, the two-dimentional depletion mode of original conventional device is become into three-dimensional and is exhausted, and enhances device
Exhaust ability, improve the drift doping concentration of device, and then reduce and compare conducting resistance.
Detailed description of the invention
Fig. 1 is conventional separate gate VDMOS device structure；
Fig. 2 is that a kind of separate gate VDMOS device with internal field plate of the embodiment of the present invention 1 peels off part of the surface medium
The three dimensional structure diagram of layer；
Fig. 3 is the technique manufacturing process schematic diagram of the separate gate VDMOS device with internal field plate of embodiment 1；
Fig. 4 (a)-Fig. 4 (e) is that the technique of the separate gate VDMOS device with internal field plate of embodiment 1 manufactures signal
Figure；
Fig. 5 is a kind of three-dimensional structure that part of the surface is peelled off with the separate gate VDMOS device of internal field plate of embodiment 2
Schematic diagram；
Fig. 6 (a)-Fig. 6 (c) is the three-dimensional of the separate gate VDMOS device with internal field plate of 3~embodiment of embodiment 5
Structural schematic diagram；
In Fig. 1,10 be the first conductive type semiconductor substrate, and 11 be the first conductive type semiconductor contact zone, and 12 be the
One conductive type semiconductor drift region, 21 be the second conductive type semiconductor contact zone, and 22 be the second conductive type semiconductor trap
Area, 31 be polysilicon gate, and 32 be polysilicon separate gate electrodes, and 41 be metal source, and 50 be A oxide layer medium, and 51 be B oxygen
Change layer medium, 52 be C oxide layer medium, and 53 be D oxide layer medium；
110 be the first conductive type semiconductor substrate, and 111 be the first conductive type semiconductor source contact zone, and 112 be first
Conductive type semiconductor drift region, 121 be the second conductive type semiconductor source contact zone, and 122 be the second conductive type semiconductor
Well region, 130 be field plate in polysilicon body, and 131 be gate electrode, and 132 be separate gate electrodes, and 140 be source metal, and 150 be grid oxygen
Change layer medium, 151 be first medium layer, and 152 be second dielectric layer, and 153 be third dielectric layer, and 154 be the 4th dielectric layer, 161
It is internal field plate slot for separate gate slot, 162.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
As shown in Figure 1, being traditional separate gate VDMOS device cross-sectional view of the structure, device includes: that the first conduction type is partly led
Body substrate 10, the first conductive type semiconductor drift region 12, the first conductive type semiconductor contact zone 11, the second conduction type half
Conductor well region 22, the second conductive type semiconductor contact zone 21, polysilicon gate 31, polysilicon separate gate electrodes 32, source metal
Electrode 41, A oxide layer medium 50, B oxide layer medium 51, C oxide layer medium 52, D oxide layer medium 53.Wherein, first is conductive
Type semiconductor substrate 10, the first conductive type semiconductor contact zone 11 and the second conductive type semiconductor contact zone 21 are generally adopted
With heavy doping, polysilicon separate gate electrodes 32 are drawn by other positions and source electrode is shorted, B oxide layer medium 52 and D oxidation
Layer medium 53 surrounds polysilicon gate 31.
Embodiment 1
A kind of separate gate VDMOS device with internal field plate, including the first conductive type semiconductor substrate 110, first
Conductive type semiconductor drift region 112, the second conductive type semiconductor well region 122, the first conductive type semiconductor source contact zone
111, the second conductive type semiconductor source contact zone 121, source metal 140, separate gate slot 161, internal field plate slot 162 are dividing
From the gate electrode 131 being formed by polysilicon formed in grid slot 161, the separate gate electrodes 132, the gate oxide that are formed by polysilicon
Third dielectric layer 153 between medium 150, first medium layer 151, gate electrode 131 and separate gate electrodes 132, in vivo field plate
Field plate 130 in the second dielectric layer 152 and polysilicon body formed in slot 162, the 4th dielectric layer 154；
Field plate 130 protrudes into the drift of the first conductive type semiconductor in the second dielectric layer 152 and polysilicon body realized by grooving
It moves in area 112, second dielectric layer 152 surrounds field plate 130 in polysilicon body；First conductive type semiconductor substrate 110 is heavily doped
It is miscellaneous, 121 heavy doping of the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone；Source electrode gold
Belong to 140 to be shorted the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone 121, and covers
Field plate 130 in polysilicon body are covered, internal 162 upper surface of field plate slot is surrounded by the second conductive type semiconductor source contact zone 121,
Internal field plate slot 162 periodically occurs in front-rear direction.
Its working principles are as follows: by taking first kind conductive type semiconductor material is N-type as an example, when gate bias is greater than threshold
When threshold voltage, there is electron inversion layer close to the surface of gate oxide medium 150 in the second conductive type semiconductor well region 122,
Under the action of drain terminal Vd, formed from first conductive type semiconductor substrate the first conductive type semiconductor of 110- drift region 112- the
The electricity of-the first conductive type semiconductor source contact zone 111- source metal 140 near two conductive type semiconductor well regions, 122 interface
Logical circulation road.When gate bias is 0, drain electrode is biased to Vd, the second conductive type semiconductor well region 122 and the first conduction type half
The PN junction that conductor drift region 112 is constituted starts to exhaust under backward voltage Vd effect, since separate gate electrodes 132 connect 0, polysilicon
Internal field plate 130 connects 0, and separate gate electrodes 132 and internal field plate 130 can rely on MOS depletion mode depletion drift region.With leakage
End voltage gradually rises, and PN junction and MOS exhaust two ways and depletion region gradually extended towards drain terminal, and final Vd is mainly dropped to
In depletion region, until breakdown.The concentration for the first conductive type semiconductor drift region 112 that device off state can exhaust determines
Resistance value of the device in grid open state.Conventional separate gate structures are exhausted to tie with longitudinal P N by the MOS of lateral separation grid and be consumed
To the greatest extent, embodiment 1 exhaust by lateral separation grid, the exhausting of field plate in weft element, longitudinal P N knot exhaust and body in the front-back direction
Interior field plate exhausts three kinds of modes, three kinds of direction depletion drift regions, therefore to exhaust ability stronger for embodiment 1, it is meant that in identical ruler
Separated bar part drift region concentration is higher under very little same breakdown voltage, lower than conducting resistance.
As shown in figure 3, a kind of manufacturing method of separate gate VDMOS device with internal field plate of embodiment 1, including such as
Lower step:
(a) first conduction is formed by epitaxy technique in given first kind conductive type semiconductor material substrate 110
Type semiconductor drift region 112, on this basis using mask plate by deep etching technique formed separate gate slot 161 and in vivo
Field plate slot 162；The structural schematic diagram being shown such as Fig. 4 (a) after etching groove, wherein the first conductive type semiconductor substrate 110
Generally heavy doping；
(b) on the basis of (a), first medium layer 151 required for being formed simultaneously by thermally grown or depositing technics
With second dielectric layer 152, then polysilicon filled up in slot inner medium layer by depositing technics, exposure mask is utilized by etching polysilicon
Version falls the etching polysilicon in separate gate slot 161, to form separate gate electrodes 132, and etches away 161 top of separate gate slot
The dielectric layer divided；Form the tomograph as shown in Fig. 4 (b)；
(c) on the basis of (b), by deposit or thermally grown dielectric layer and etch media layer, separate gate slot 161 is formed
Third dielectric layer 153 between interior separate gate electrodes 132 and gate electrode, then gate oxide medium is formed by thermal oxidation technology
150, then deposit simultaneously CMP polysilicon and form gate electrode 131, and carry out surface C MP；Form the signal of the three-dimensional structure as shown in Fig. 4 (c)
Figure；
(d) on the basis of (c), using self-registered technology, the second conductive type semiconductor impurity is injected, and knot is formed
Second conductive type semiconductor well region 122 is used as channel；As shown in Fig. 4 (d)；
(e) it on the basis of (d), successively injects the first conductive type semiconductor impurity and the second conductive type semiconductor is miscellaneous
Matter forms the first conductive type semiconductor source contact zone 111 and the second conductive type semiconductor source contact zone 121, wherein first
Conductive type impurity is injected by self-registered technology, and the second conductive type impurity is injected using mask plate；Medium conduct is deposited again
4th dielectric layer 154, and etch the 4th dielectric layer and filling metal or polysilicon formed gate electrode and source electrode contact metal or
Polysilicon, the surface CMP form the separate gate VDMOS as shown in Fig. 4 (e) with internal field plate after contacting metal or polysilicon
Device.
Preferably, the manufacturing method of the separate gate VDMOS device, the formation of separate gate slot 161 and internal field plate slot 162
Different mask plates are used in actual process；The in second dielectric layer 152 and separate gate slot 161 in internal field plate slot 162
One dielectric layer 151 is formed or is passed through thermally grown formation by deposit.
Preferably, the third dielectric layer 153 between separate gate electrodes 132 and gate electrode 131 utilizes gate oxide medium 150
Formation simultaneously grow to be formed.
First kind conductive type semiconductor is N-type, and the second class conductive type semiconductor is p-type or first kind conductive-type
Type semiconductor is p-type, and the second class conductive type semiconductor is N-type.
Its semiconductor of separate gate VDMOS device is silicon or silicon carbide.
Embodiment 2
As shown in figure 5, the difference of the present embodiment and embodiment 1 is: source metal 140 is by etching internal field plate slot
It deposits metal after surface silicon between 162 to be formed, source metal 140 is by 111 He of the first conductive type semiconductor source contact zone
Second conductive type semiconductor source contact zone 121 is shorted, and source metal 140 stretches to the first conductive type semiconductor drift region
In 112, internal field plate slot 162 and source metal 140 are alternately present in front-rear direction.The structure can be by adjusting source metal
The depth of 140 metals contact, forms the Schottky of source metal 140 and low-doped first conductive type semiconductor drift region 112
Contact, reduces the reverse recovery time of device.
Embodiment 3
As shown in Fig. 6 (a), the difference of the present embodiment and embodiment 1 is: the depth of separate gate slot 161 is less than internal field
The depth of board slot 162.So that the power line for being directed toward separate gate electrodes 132 originally is directed toward 130 bottom of field plate in polysilicon body, improve
161 bottom power line of separate gate slot and field distribution improve device electric breakdown strength.
Embodiment 4
As shown in Fig. 6 (b), the difference of the present embodiment and embodiment 1 is: internal field plate slot 162 protrudes into the first conductive-type
In type semiconductor substrate 110.Board slot 162 slot bottom material intersection in original device body internal field is avoided to hit as caused by curvature effect
It wears.
Embodiment 5
As shown in Fig. 6 (c), the difference of the present embodiment and embodiment 1 is: separate gate slot 161 and internal field plate slot 162 are equal
Protrude into the first conductive type semiconductor substrate 110.The structure by the design of slot it is possible to prevente effectively from original device there may be
Slot bottom material intersection because curvature effect caused by puncture in advance.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of separate gate VDMOS device with internal field plate, characterized by comprising: the first conductive type semiconductor substrate
(110), the first conductive type semiconductor drift region (112), the second conductive type semiconductor well region (122), the first conduction type
Semiconductor source contact zone (111), the second conductive type semiconductor source contact zone (121), source metal (140), separate gate slot
(161), internal field plate slot (162), in the interior gate electrode (131) being formed by polysilicon formed of separate gate slot (161), by polycrystalline
Separate gate electrodes (132), gate oxide medium (150), first medium layer (151), gate electrode (131) and the separate gate that silicon is formed
Third dielectric layer (153) between electrode (132), the second dielectric layer (152) formed in field plate slot (162) in vivo and polycrystalline
Field plate (130) in silicon body, the 4th dielectric layer (154)；
Field plate (130) protrudes into the first conduction type and partly leads in the second dielectric layer (152) and polysilicon body realized by cutting filling
In body drift region (112), second dielectric layer (152) surrounds field plate in polysilicon body (130)；First conductive type semiconductor lining
Bottom (110) heavy doping, the first conductive type semiconductor source contact zone (111) and the second conductive type semiconductor source contact zone
(121) heavy doping；Source metal (140) partly leads the first conductive type semiconductor source contact zone (111) and the second conduction type
Body source contact zone (121) is shorted, and covers field plate in polysilicon body (130), and internal field plate slot (162) upper surface is led by second
Electric type semiconductor source contact zone (121) surrounds, and internal field plate slot (162) periodically occurs in front-rear direction.
2. a kind of separate gate VDMOS device with internal field plate according to claim 1, it is characterised in that: source electrode gold
Belonging to (140), deposit metal is formed after surface silicon between internal field plate slot (162) by etching, and source metal (140) is by first
Conductive type semiconductor source contact zone (111) and the second conductive type semiconductor source contact zone (121) are shorted, source metal
(140) it stretches in the first conductive type semiconductor drift region (112), internal field plate slot (162) and source metal (140) are preceding
Rear direction is alternately present.
3. a kind of separate gate VDMOS device with internal field plate according to claim 1, it is characterised in that: separate gate
The depth of slot (161) is less than the depth of internal field plate slot (162).
4. a kind of separate gate VDMOS device with internal field plate according to claim 1, it is characterised in that: internal field
Board slot (162) protrudes into the first conductive type semiconductor substrate (110).
5. a kind of separate gate VDMOS device with internal field plate according to claim 1, it is characterised in that: separate gate
Slot (161) and internal field plate slot (162) protrude into the first conductive type semiconductor substrate (110).
6. a kind of manufacturing method of separate gate VDMOS device with internal field plate described in claim 1, it is characterised in that:
Comprising steps of
(a) drift region of device is formed by epitaxy technique in given first kind conductive type semiconductor material substrate on piece,
Separate gate slot (161) and internal field plate slot (162) are formed by deep etching technique using mask plate on this basis；
(b) on the basis of (a), by thermally grown or depositing technics be formed simultaneously required for first medium layer (151) and
Second dielectric layer (152), then polysilicon is filled up in slot inner medium layer by depositing technics, exposure mask is utilized by etching polysilicon
Version falls the etching polysilicon in separate gate slot (161), to form separate gate electrodes (132), and etches away separate gate slot
(161) dielectric layer of part on；
(c) it on the basis of (b), by deposit or thermally grown dielectric layer and etch media layer, is formed in separate gate slot (161)
Third dielectric layer (153) between separate gate electrodes (132) and gate electrode, then gate oxide medium is formed by thermal oxidation technology
(150), then simultaneously CMP polysilicon formation gate electrode (131) is deposited, and carries out surface C MP；
(d) on the basis of (c), using self-registered technology, the second conductive type semiconductor impurity is injected, and knot forms second
Conductive type semiconductor well region (122) is used as channel；
(e) on the basis of (d), the first conductive type semiconductor impurity and the second conductive type semiconductor impurity are successively injected,
The first conductive type semiconductor source contact zone (111) and the second conductive type semiconductor source contact zone (121) are formed, wherein first
Conductive type impurity is injected by self-registered technology, and the second conductive type impurity is injected using mask plate；Medium conduct is deposited again
4th dielectric layer (154), and etch the 4th dielectric layer and filling metal or polysilicon formation gate electrode and source electrode contact metal
Or polysilicon, the surface CMP form the separate gate VDMOS device with internal field plate after contacting metal or polysilicon.
7. the manufacturing method of the separate gate VDMOS device described in -5 any one with internal field plate according to claim 1,
Be characterized in that: separate gate slot (161) and being formed in actual process for internal field plate slot (162) use different mask plates；In vivo
The first medium layer (151) in second dielectric layer (152) and separate gate slot (161) in field plate slot (162) is formed by deposit
Or pass through thermally grown formation.
8. the manufacturing method of the separate gate VDMOS device according to claim 1 with internal field plate, it is characterised in that:
Third dielectric layer (153) between separate gate electrodes (132) and control gate (131) utilizes the formation of gate oxide medium (150)
It grows to be formed simultaneously.
9. the separate gate VDMOS device according to claim 1 with internal field plate, it is characterised in that: the first kind is conductive
Type semiconductor is N-type, and the second class conductive type semiconductor is p-type or first kind conductive type semiconductor is p-type, second
Class conductive type semiconductor is N-type.
10. the separate gate VDMOS device according to claim 1 with internal field plate, it is characterised in that: its semiconductor is
Silicon or silicon carbide.
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| CN110943132A (en) * | 2019-12-17 | 2020-03-31 | 华羿微电子股份有限公司 | Low-capacitance groove type VDMOS device and preparation method thereof |
| CN113363315A (en) * | 2021-04-25 | 2021-09-07 | 深圳深爱半导体股份有限公司 | Planar T-shaped gate transistor cell structure and manufacturing method |
| CN113690299A (en) * | 2020-05-18 | 2021-11-23 | 华润微电子（重庆）有限公司 | Trench gate VDMOS device and preparation method thereof |
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| CN102007584A (en) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | Semiconductor device structures and related processes |
| CN106158973A (en) * | 2016-07-06 | 2016-11-23 | 电子科技大学 | A kind of accumulation type DMOS |
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| CN110943132A (en) * | 2019-12-17 | 2020-03-31 | 华羿微电子股份有限公司 | Low-capacitance groove type VDMOS device and preparation method thereof |
| CN113690299A (en) * | 2020-05-18 | 2021-11-23 | 华润微电子（重庆）有限公司 | Trench gate VDMOS device and preparation method thereof |
| CN113690299B (en) * | 2020-05-18 | 2024-02-09 | 华润微电子（重庆）有限公司 | Trench gate VDMOS device and preparation method thereof |
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