CN107799585A - A kind of shield grid MOS structure with gradual change deep trouth - Google Patents
A kind of shield grid MOS structure with gradual change deep trouth Download PDFInfo
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 230000001413 cellular effect Effects 0.000 claims description 11
- 210000000746 body region Anatomy 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 210000005056 cell body Anatomy 0.000 description 20
- 238000005530 etching Methods 0.000 description 15
- 210000004027 cell Anatomy 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The present invention proposes a kind of shield grid MOS structure with gradual change deep trouth, it is characterized in that, the groove is shaped as inverted trapezoidal, and it is divided into two parts up and down, upper part includes inverted trapezoidal Gate Electrode Conductive polysilicon and the gate oxide positioned at inverted trapezoidal Gate Electrode Conductive polysilicon both sides, and lower part includes the inverted trapezoidal shield grid that thick oxide layer and thick oxide layer wrap up；Shield grid MOS structure proposed by the present invention, by setting graded slot so that the lower trench of inverted trapezoidal forms inverted trapezoidal shield grid and wraps up the thick oxide layer of inverted trapezoidal shield grid, it is pressure-resistant that such structure can improve device, conducting resistance is reduced, while chip area can be reduced, it is cost-effective.
Description
Technical field
The present invention relates to a kind of MOSFET element structure, especially a kind of shield grid MOS structure with gradual change deep trouth, category
In MOSFET technical fields.
Background technology
Metal-Oxide Semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect
Transistor, MOSFET) it is that a kind of can be widely used in analog circuit and the field-effect transistor of digital circuit.
As shown in figure 1, it is traditional Trench MOSFET elements structure, as shown in Fig. 2 being tied for traditional shield grid MOS
Structure, the voltage endurance capability of two kinds of structures are the key parameters for characterizing device performance, always also are emphasis of concern, and tradition
The shield grid of shield grid MOS structure and the oxide layer of shield grid both sides, be unanimous between the higher and lower levels, so that drift region exist two
Individual peak electric field, one is in PXing Ti areas 9 and the intersection of N-type epitaxy layer 2, and another is in the bottom of groove 4, two electric fields
The electric field of peak value center section can be relatively low, two such peak electric field be in device it is pressure-resistant when easily puncture, influence device
Voltage endurance capability.
The content of the invention
On the basis of overcoming existing shielding grid MOSFET component shortcoming, a kind of function admirable is proposed
Shielding grid MOSFET component structure and preparation method thereof, the structure is by setting graded slot（Inverted trapezoidal groove）So that fall
Trapezoidal groove bottom forms inverted trapezoidal shield grid and wraps up the thick oxide layer of inverted trapezoidal shield grid, can not only so improve device
Voltage endurance capability, and the conducting resistance of device can be reduced, while chip area can be reduced, it is cost-effective.
To realize above technical purpose, the technical scheme is that：A kind of shield grid MOS knots with gradual change deep trouth
Structure, including cellular region and terminal protection area, the cellular region are located at the center of device, and the terminal protection area is looped around described
Around cellular region, the cellular region is formed in parallel by several MOSFET element cell cubes, the MOSFET element cell cube
Including semiconductor substrate, the semiconductor substrate includes the first conduction type heavy doping substrate and heavily doped positioned at the first conduction type
The first conductive type epitaxial layer on miscellaneous substrate, the upper surface of first conductive type epitaxial layer are the first of semiconductor substrate
Interarea, the lower surface of the first conduction type heavy doping substrate is the second interarea of semiconductor substrate, in the first conduction type extension
The direction for pointing to the second interarea in layer along the first interarea is provided with groove, and the groove both sides are equipped with the second conduction type body
Area, second conductivity type body region is in the first conductive type epitaxial layer, and inside is provided with the first conduction type source area,
The first conduction type source area is located at left and right sides of groove and adjoining, on the groove and the first conduction type source area
Side is provided with insulating medium layer, and the insulating medium layer both sides are provided with source contact openings, metal is filled with the source contact openings,
Form source metal, the source metal contacts through source contact openings with the second conductivity type body region, and with the first conductive-type
Type source area Ohmic contact, it is characterised in that the groove is shaped as inverted trapezoidal, and is divided into two parts up and down, top subpackage
Inverted trapezoidal Gate Electrode Conductive polysilicon and the gate oxide positioned at inverted trapezoidal Gate Electrode Conductive polysilicon both sides are included, lower part includes thick oxygen
Change the inverted trapezoidal shield grid of layer and thick oxide layer parcel.
Further, the thickness of the thick oxide layer is more than the thickness of gate oxide, and the thickness of the thick oxide layer is
3000A ~ 10000A, the thickness of gate oxide is 800A ~ 1200A.
Further, in inverted trapezoidal groove, inverted trapezoidal Gate Electrode Conductive polysilicon and inverted trapezoidal shield grid inverted trapezoidal side wall
Angle with the second interarea of semiconductor substrate is 80 ° ~ 90 °.
Further, between the inverted trapezoidal Gate Electrode Conductive polysilicon and inverted trapezoidal shield grid oxide layer thickness for 2000A ~
4000A。
Further, separated between the source metal and inverted trapezoidal Gate Electrode Conductive polysilicon by insulating medium layer.
Further, the depth of inverted trapezoidal groove is 4 ~ 10um.
Further, for N-type MOS device, first conduction type is that N-type is conductive, and second conduction type is P
Type is conductive；For p-type MOS device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
In order to further realize above technical purpose, the present invention also proposes a kind of shield grid with stairstepping oxide layer
The preparation method of MOS structure, it is characterised in that comprise the following steps：
Step 1 provides the first conduction type heavy doping substrate, in the first conduction type heavy doping Grown first
Conductive type epitaxial layer, the upper surface of first conductive type epitaxial layer is the first interarea, and the first conduction type heavy doping serves as a contrast
The lower surface at bottom is the second interarea；
Step 2 is blocked by Patterned masking layer, and the first interarea is performed etching, in the first conductive type epitaxial layer
Groove is formed, and removes mask layer；
Step 3 uses thermal oxide or HDP techniques, grows oxide layer in the trench, the oxide layer fills up groove；
Step 4 is blocked by graphical photolithography plate, and the oxide layer in groove is performed etching, and is controlled horizontal and vertical
The ratio of etching, inverted trapezoidal groove is formed in groove, and remove photolithography plate；
Step 5 depositing polysilicons in the first interarea and inverted trapezoidal groove, and polysilicon carve, only retain inverted trapezoidal
The polysilicon of groove bottom, form shield grid；
Step 6 uses wet-etching technology, and groove internal oxidation layer is performed etching, and controls the depth of etching, removes shield grid
The oxide layer of top, stairstepping oxide layer is formed in shield grid both sides；
Step 7 uses thermal oxidation technology, with groove in grow layer of oxide layer, formed above the shield grid in groove
Cell body, the oxide layer of the cell body both sides is gate oxide；
Step 8 depositing polysilicons in cell body, the polysilicon fill up cell body, and the polysilicon in the cell body is led for grid
Electric polysilicon；
Step 9 is led under the blocking of graphical photolithography plate in groove both sides successively injection the second conductive type impurity and first
Electric type dopant, after pushing away trap, successively form the second conductivity type body region and the first conduction type source area；
Step 10 deposits insulating medium layer on the first interarea, and insulating medium layer is performed etching, in the second conduction type body
The source contact openings of break-through the first conduction type source area are formed above area；
Step 11 fills metal in source contact openings, and metal is performed etching, and forms source metal.
Further, in the step 3, a thickness oxide layer is grown in the first interarea and groove, then pass through wet method
Thick oxide layer on the interarea of erosion removal first, only retain the oxide layer in groove.
Further, in the step 7, the oxide layer of thermal oxidation method growth is also covered on the first interarea simultaneously；It is described
Polysilicon in step 8 is also deposited in the oxide layer above the first interarea simultaneously, then to the polysilicon on the first interarea and
Oxide layer performs etching, and exposes the first interarea and comes.
From the above, it can be seen that the beneficial effects of the present invention are：
1）Device of the present invention is by setting graded slot（Inverted trapezoidal groove）So that inverted trapezoidal lower trench forms inverted trapezoidal shielding
The thick oxide layer of grid and parcel inverted trapezoidal shield grid, it is pressure-resistant that such structure can improve device；
2）With tradition shield gate device compared with, it is identical it is pressure-resistant in the case of, epitaxial layer of the invention can possess more high-dopant concentration,
So that device has lower conducting resistance；
3）Compared with tradition shields gate device, device of the present invention can reduce chip area, cost-effective.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the Trench MOSFET cell cubes of prior art.
Fig. 2 is the cross-sectional view of the shield grid MOSFET cell cubes of prior art.
Fig. 3 is the cross-sectional view of the shield grid MOSFET cell cubes of the present invention.
Fig. 4 is the cross-sectional view that groove is formed in the embodiment of the present invention.
Fig. 5 is the cross-sectional view that the first cell body is formed in the embodiment of the present invention.
Fig. 6 is the cross-sectional view that inverted trapezoidal shield grid is formed in the embodiment of the present invention.
Fig. 7 is the cross-sectional view that thick oxide layer is formed in the embodiment of the present invention.
Fig. 8 is the cross-sectional view that the second cell body and gate oxide are formed in the embodiment of the present invention.
Fig. 9 is the cross-sectional view that inverted trapezoidal Gate Electrode Conductive polysilicon is formed in the embodiment of the present invention.
Brief description of the drawings：1- the first conduction type heavy doping substrate, the conductive type epitaxial layers of 2- first, 3- thick oxide layers, 4-
Groove, 5- inverted trapezoidals shield grid, 6- source contact openings, 7- inverted trapezoidal Gate Electrode Conductives polysilicon, 8- gate oxides, 9- second are conductive
Type body region, the first conduction types of 10- source area, 11- insulating medium layers, 12- source metals, the cell bodies of 13- first, 14- second
Cell body, the interareas of 001- first, the interareas of 002- second.
Embodiment
With reference to specific embodiments and the drawings, the invention will be further described.
With reference to the accompanying drawings described in 3, the shield grid MOS structure of the embodiment of the present invention is by taking N-type conduction as an example, first conductive-type
Type is that N-type is conductive, and second conduction type is P-type conduction, a kind of shield grid MOS structure with gradual change deep trouth, including member
Born of the same parents area and terminal protection area, the cellular region are located at the center of device, and the terminal protection area is looped around the cellular region
Around, the cellular region is formed in parallel by several MOSFET element cell cubes, and the MOSFET element cell cube includes partly leading
Structure base board, the semiconductor substrate include the first conduction type heavy doping substrate 1 and positioned at the first conduction type heavy doping substrates 1
On the first conductive type epitaxial layer 2, the upper surface of first conductive type epitaxial layer 2 is the first interarea of semiconductor substrate
001, the lower surface of the first conduction type heavy doping substrate 1 is the second interarea 002 of semiconductor substrate, outside the first conduction type
Prolong in layer 2 and be provided with groove 4 along the direction of the first interarea 001 the second interarea 002 of sensing, the both sides of groove 4 are equipped with second
Conductivity type body region 9, second conductivity type body region 9 is in the first conductive type epitaxial layer 2, and inside is led provided with first
Electric type source area 10, the first conduction type source area 10 is located at the left and right sides of groove 4 and adjoining, in the He of groove 4
The top of first conduction type source area 10 is provided with insulating medium layer 11, and the both sides of insulating medium layer 11 are provided with source contact openings 6,
Be filled with metal in the source contact openings 6, form source metal 12, the source metal 12 passes through source contact openings 6 and the
Two conductivity type body regions 9 contact, and with the Ohmic contact of the first conduction type source area 10, the source metal 12 and inverted trapezoidal grid
Separated between pole conductive polycrystalline silicon 7 by insulating medium layer 11；Characterized in that, the groove 4 is shaped as inverted trapezoidal, and divide
For upper and lower two parts, upper part includes inverted trapezoidal Gate Electrode Conductive polysilicon 7 and positioned at the both sides of inverted trapezoidal Gate Electrode Conductive polysilicon 7
Gate oxide 8, lower part include the inverted trapezoidal shield grid 5 that thick oxide layer 3 and thick oxide layer 3 wrap up, the thickness of the thick oxide layer 3
Thickness of the degree more than gate oxide 8；
The thickness of thick oxide layer in the embodiment of the present invention is 3000A ~ 10000A, and the thickness of gate oxide is 800A ~ 1200A,
And in groove 4, inverted trapezoidal Gate Electrode Conductive polysilicon 7 and inverted trapezoidal shield grid 5 side wall of inverted trapezoidal and semiconductor substrate second
The angle of interarea 002 is 80 ° ~ 90 °, the thickness of oxide layer between the inverted trapezoidal Gate Electrode Conductive polysilicon 7 and inverted trapezoidal shield grid 5
Spend for 2000A ~ 4000A, the depth of inverted trapezoidal groove 4 is 4 ~ 10um, and above concrete technology size is determined all in accordance with device parameters
It is fixed.
A kind of preparation method of shield grid MOS structure with gradual change deep trouth in above example, it is characterised in that bag
Include following steps：
Step 1 provides N-type heavy doping substrate 1, the growth N-type epitaxy layer 2 on the N-type heavy doping substrate 1, outside the N-type
The upper surface for prolonging layer 2 is the first interarea 001, and the lower surface of N-type heavy doping substrate 1 is the second interarea 002；
As shown in figure 4, step 2 blocking by Patterned masking layer, performs etching, and control transverse direction to the first interarea 001
With the etching ratio of longitudinal direction, the groove 4 of inverted trapezoidal is formed in N-type epitaxy layer 2, and removes mask layer；
As shown in figure 5, step 3 uses thermal oxide or HDP techniques, layer of oxide layer is grown in groove 4, the shape in groove 4
Into the first cell body 13；
In the step 3, layer of oxide layer is grown in the first interarea 001 and groove 4, then remove the by wet etching
Oxide layer on one interarea 001, only retain the oxide layer in groove 4, form the first cell body 13, and the oxygen of the side wall of the first cell body 13
It is identical with the thickness of thick oxide layer 3 to change thickness degree.
As shown in fig. 6, step 4 depositing polysilicons in the first interarea 001 and the first cell body 13, and polysilicon is entered
Go back quarter, only retain the polysilicon of the bottom of the first cell body 13, form inverted trapezoidal shield grid 5；
As shown in fig. 7, step 5 uses wet-etching technology, the oxide layer of the first cell body 13 is performed etching, control etching
Depth, remove the oxide layer of the top of inverted trapezoidal shield grid 5, thick oxide layer 3 formed in the both sides of inverted trapezoidal shield grid 5；
As shown in figure 8, step 6 uses thermal oxidation technology, and the growth layer of oxide layer in groove 4, the ladder in groove 4
The top of shape shield grid 5 forms the second cell body 14, and the oxide layer of the both sides of the second cell body 14 is gate oxide 8；
As shown in figure 9, step 7 depositing polysilicons in the second cell body 14, the polysilicon fills up the second cell body 14, described
Polysilicon in second cell body 14 is inverted trapezoidal Gate Electrode Conductive polysilicon 7；
In the step 6, the oxide layer of thermal oxidation method growth is also covered on the first interarea 001 simultaneously；In the step 7
Polysilicon is also deposited in the oxide layer of the top of the first interarea 001 simultaneously, then to the polysilicon on the first interarea 001 and oxidation
Layer performs etching, and exposes the first interarea 001 and comes, and retains the polysilicon and oxide layer in groove 4.
Step 8 is under the blocking of graphical photolithography plate, in the both sides priority implanting p-type impurity of groove 4 and N of inverted trapezoidal
Type impurity, after pushing away trap, successively form PXing Ti areas 9 and N-type source region 10；
Step 9 deposits insulating medium layer 11 on the first interarea 001, insulating medium layer 11 is performed etching, in PXing Ti areas 9
Top forms the source contact openings of break-through N-type source region 10；
Step 10 fills metal in source contact openings, and metal is performed etching, and forms source metal 12.
Compared with traditional shielded gate structures, device of the invention has higher breakdown voltage when bearing pressure-resistant：This hair
The bright groove 4 using inverted trapezoidal so that the thick oxide layer of inverted trapezoidal shield grid 5 and parcel inverted trapezoidal shield grid 5 is formed in groove 4
3, inverted trapezoidal structure can greatly optimize the Electric Field Distribution in region between PXing Ti areas 9 and the bottom of groove 4, and make two peak values
And between peak value the Electric Field Distribution of transition become it is more gentle will uniformly, when device is pressure-resistant be not easy at peak value it is breakdown, therefore can be with
Effectively improve the breakdown voltage of device；
After break-over of device of the present invention, compared with traditional shielded gate structures, it is identical it is pressure-resistant in the case of, device of the present invention can use more
Highly doped N-type epitaxy layer 2, the resistance of N-type epitaxy layer 2 is reduced, so as to reduce device on-resistance；More than being based on, the device
Part can have smaller chip area, improve the cost performance of device.
Claims (7)
1. a kind of shield grid MOS structure with gradual change deep trouth, including cellular region and terminal protection area, the cellular region are located at device
The center of part, the terminal protection area are looped around around the cellular region, and the cellular region is by several MOSFET elements
Cell cube is formed in parallel, and the MOSFET element cell cube includes semiconductor substrate, and it is conductive that the semiconductor substrate includes first
Type heavy doping substrate（1）And positioned at the first conduction type heavy doping substrate（1）On the first conductive type epitaxial layer（2）, institute
State the first conductive type epitaxial layer（2）Upper surface be semiconductor substrate the first interarea（001）, the first conduction type heavy doping
Substrate（1）Lower surface be semiconductor substrate the second interarea（002）, in the first conductive type epitaxial layer（2）It is interior along first
Interarea（001）Point to the second interarea（002）Direction be provided with groove（4）, the groove（4）Both sides are equipped with the second conduction type
Body area（9）, second conductivity type body region（9）Located at the first conductive type epitaxial layer（2）It is interior and internal conductive provided with first
Type source area（10）, the first conduction type source area（10）Positioned at groove（4）The left and right sides and adjoining, in the groove
（4）With the first conduction type source area（10）Top is provided with insulating medium layer（11）, the insulating medium layer（11）Both sides are provided with
Source contact openings（6）, the source contact openings（6）It is interior to be filled with metal, form source metal（12）, the source metal（12）
Through source contact openings（6）With the second conductivity type body region（9）Contact, and with the first conduction type source area（10）Ohm connects
Touch, it is characterised in that the groove（4）Be shaped as inverted trapezoidal, and be divided into two parts up and down, upper part includes inverted trapezoidal grid
Conductive polycrystalline silicon（7）With positioned at inverted trapezoidal Gate Electrode Conductive polysilicon（7）The gate oxide of both sides（8）, lower part includes thick aoxidize
Layer（3）And thick oxide layer（3）The inverted trapezoidal shield grid of parcel（5）.
A kind of 2. shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The thick oxygen
Change layer（3）Thickness be more than gate oxide（8）Thickness, the thickness of the thick oxide layer is 3000A ~ 10000A, gate oxide
Thickness be 800A ~ 1200A.
A kind of 3. shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The ladder
The groove of shape（4）, inverted trapezoidal Gate Electrode Conductive polysilicon（7）With inverted trapezoidal shield grid（5）The side wall of middle inverted trapezoidal with it is semiconductor-based
Second interarea of plate（002）Angle be 80 ° ~ 90 °.
A kind of 4. shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The ladder
Shape Gate Electrode Conductive polysilicon（7）With inverted trapezoidal shield grid（5）Between the thickness of oxide layer be 2000A ~ 4000A.
A kind of 5. shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The source electrode
Metal（12）With inverted trapezoidal Gate Electrode Conductive polysilicon（7）Between pass through insulating medium layer（11）Separate.
A kind of 6. shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The ladder
The groove of shape（4）Depth be 4 ~ 10um.
A kind of 7. shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：For N-type
MOS device, first conduction type are that N-type is conductive, and second conduction type is P-type conduction；For p-type MOS device, institute
It is P-type conduction to state the first conduction type, and second conduction type is that N-type is conductive.
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| CN201711251628.9A CN107799585A (en) | 2017-12-01 | 2017-12-01 | A kind of shield grid MOS structure with gradual change deep trouth |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108400094A (en) * | 2018-04-19 | 2018-08-14 | 张帅 | Shielded gate field effect transistor and its manufacturing method（Capitate） |
| CN108598165A (en) * | 2018-04-19 | 2018-09-28 | 张帅 | Shielded gate field effect transistor and its manufacturing method（Cylindricality） |
| CN109461769A (en) * | 2018-12-10 | 2019-03-12 | 无锡紫光微电子有限公司 | A kind of trench gate IGBT device structure and preparation method thereof |
Citations (4)
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| US20150108568A1 (en) * | 2013-10-21 | 2015-04-23 | Vishay-Siliconix | Semiconductor structure with high energy dopant implantation |
| US20170012111A1 (en) * | 2015-07-09 | 2017-01-12 | Great Wall Semiconductor Corporation | Trench mosfet with depleted gate shield and method of manufacture |
| CN106876278A (en) * | 2017-03-01 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | The manufacture method of the trench-gate device with shield grid |
| CN207925474U (en) * | 2017-12-01 | 2018-09-28 | 苏州凤凰芯电子科技有限公司 | A kind of shield grid MOS structure with gradual change deep trouth |
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| US20150108568A1 (en) * | 2013-10-21 | 2015-04-23 | Vishay-Siliconix | Semiconductor structure with high energy dopant implantation |
| US20170012111A1 (en) * | 2015-07-09 | 2017-01-12 | Great Wall Semiconductor Corporation | Trench mosfet with depleted gate shield and method of manufacture |
| CN106876278A (en) * | 2017-03-01 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | The manufacture method of the trench-gate device with shield grid |
| CN207925474U (en) * | 2017-12-01 | 2018-09-28 | 苏州凤凰芯电子科技有限公司 | A kind of shield grid MOS structure with gradual change deep trouth |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108400094A (en) * | 2018-04-19 | 2018-08-14 | 张帅 | Shielded gate field effect transistor and its manufacturing method（Capitate） |
| CN108598165A (en) * | 2018-04-19 | 2018-09-28 | 张帅 | Shielded gate field effect transistor and its manufacturing method（Cylindricality） |
| CN108598165B (en) * | 2018-04-19 | 2020-12-25 | 济南安海半导体有限公司 | Shielded gate field effect transistor and method of manufacturing the same (pillar shape) |
| CN109461769A (en) * | 2018-12-10 | 2019-03-12 | 无锡紫光微电子有限公司 | A kind of trench gate IGBT device structure and preparation method thereof |
| CN109461769B (en) * | 2018-12-10 | 2024-03-12 | 无锡紫光微电子有限公司 | Trench gate IGBT device structure and manufacturing method thereof |
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