CN107681006A - A kind of shield grid MOS structure with stairstepping oxide layer - Google Patents

A kind of shield grid MOS structure with stairstepping oxide layer Download PDF

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Publication number
CN107681006A
CN107681006A CN201711057348.4A CN201711057348A CN107681006A CN 107681006 A CN107681006 A CN 107681006A CN 201711057348 A CN201711057348 A CN 201711057348A CN 107681006 A CN107681006 A CN 107681006A
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oxide layer
type
stairstepping
shield grid
groove
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CN201711057348.4A
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钱振华
吴宗宪
王宇澄
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Opc Microelectronics Corp
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Suzhou Phoenix Core Electronic Technology Co Ltd
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Priority to CN201711057348.4A priority Critical patent/CN107681006A/en
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The present invention proposes a kind of shield grid MOS structure with stairstepping oxide layer, it is characterized in that, the groove is divided into two parts up and down, upper part includes Gate Electrode Conductive polysilicon and the gate oxide positioned at Gate Electrode Conductive polysilicon both sides, and lower part includes the shield grid that stairstepping oxide layer and stairstepping oxide layer are wrapped up；Shield grid MOS structure proposed by the present invention, the structure of the oxide layer of shield grid both sides use stairstepping oxide layer, it is pressure-resistant can to improve device, conducting resistance is reduced, while the parasitic capacitance of device can be reduced, the switching characteristic of optimised devices, chip area can be reduced simultaneously, it is cost-effective.

Description

A kind of shield grid MOS structure with stairstepping oxide layer
Technical field
The present invention relates to a kind of MOSFET element structure, especially a kind of shield grid MOS knots with stairstepping oxide layer Structure, belong to MOSFET technical fields.
Background technology
Metal-Oxide Semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) it is that a kind of can be widely used in analog circuit and the field-effect transistor of digital circuit.
As shown in figure 1, it is traditional Trench MOSFET elements structure, as shown in Fig. 2 being tied for traditional shield grid MOS Structure, the voltage endurance capability of two kinds of structures are the key parameters for characterizing device performance, always also are emphasis of concern, and tradition The shield grid both sides of shield grid MOS structure be thick oxide layer 15, and the oxidated layer thickness in thick oxide layer is consistent up and down, this Sample causes drift region two peak electric fields to be present, and one is in PXing Ti areas 9 and the intersection of N-type epitaxy layer 2, and another is in ditch The bottom of groove 4, the electric field of center section can be relatively low, two peak electric fields of two such be in device it is pressure-resistant when easily hit Wear, influence the voltage endurance capability of device.
The content of the invention
On the basis of overcoming existing shielding grid MOSFET component shortcoming, a kind of function admirable is proposed Shielding grid MOSFET component structure and preparation method thereof, the structual shield grid use ladder-type structure, and shield grid both sides are adopted With stairstepping oxide layer, the voltage endurance capability of device can not only be so improved, and the conducting resistance of device can be reduced, while reduces device The parasitic capacitance of part, the switching characteristic of optimised devices.
To realize above technical purpose, the technical scheme is that：A kind of shield grid MOS with stairstepping oxide layer Structure, including cellular region and terminal protection area, the cellular region are located at the center of device, and the terminal protection area is looped around institute State around cellular region, the cellular region is formed in parallel by several MOSFET element cell cubes, it is characterised in that：It is described MOSFET element cell cube includes semiconductor substrate, and the semiconductor substrate includes the first conduction type heavy doping substrate and is located at The first conductive type epitaxial layer on first conduction type heavy doping substrate, the upper surface of first conductive type epitaxial layer are First interarea of semiconductor substrate, the lower surface of the first conduction type heavy doping substrate are the second interarea of semiconductor substrate, The direction for pointing to the second interarea in first conductive type epitaxial layer along the first interarea is provided with groove, and the groove both sides are equipped with Second conductivity type body region, second conductivity type body region is in the first conductive type epitaxial layer, and inside is provided with first Conduction type source area, the first conduction type source area is located at left and right sides of groove and adjoining, in the groove and first Insulating medium layer is provided with above conduction type source area, the insulating medium layer both sides are provided with source contact openings, and the source electrode connects Metal is filled with contact hole, forms source metal, the source metal connects through source contact openings with the second conductivity type body region Touch, and with the first conduction type source area Ohmic contact, it is characterised in that the groove be divided into up and down two parts, top subpackage Gate Electrode Conductive polysilicon and the gate oxide positioned at Gate Electrode Conductive polysilicon both sides are included, lower part includes stairstepping oxide layer and rank The shield grid of trapezoidal oxide layer parcel.
Further, the shield grid is shaped as ladder-type structure.
Further, the step number in the stairstepping oxide layer is 3 ~ 5, and the height of each ladder is 1 ~ 3um, and is pushed up The oxidated layer thickness of layer ladder is 1000A ~ 5000A, and the oxidated layer thickness of bottom ladder is 6000A ~ 10000A.
Further, the thickness of oxide layer is 2000A ~ 4000A between the Gate Electrode Conductive polysilicon and shield grid.
Further, separated between source metal and the Gate Electrode Conductive polysilicon by insulating medium layer.
Further, the depth of the groove is 4 ~ 8um.
Further, for N-type MOS device, first conduction type is that N-type is conductive, and second conduction type is P Type is conductive；For p-type MOS device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
In order to further realize above technical purpose, the present invention also proposes a kind of shield grid with stairstepping oxide layer The preparation method of MOS structure, it is characterised in that comprise the following steps：
Step 1 provides the first conduction type heavy doping substrate, in the first conduction type heavy doping Grown first Conductive type epitaxial layer, the upper surface of first conductive type epitaxial layer is the first interarea, and the first conduction type heavy doping serves as a contrast The lower surface at bottom is the second interarea；
Step 2 is blocked by Patterned masking layer, and the first interarea is performed etching, in the first conductive type epitaxial layer Groove is formed, and removes mask layer；
Step 3 uses thermal oxide or HDP techniques, grows oxide layer in the trench, the oxide layer fills up groove；
Step 4 is blocked by graphical photolithography plate, and the oxide layer in groove is performed etching, and is controlled horizontal and vertical The ratio of etching, inverted trapezoidal groove is formed in groove, and remove photolithography plate；
Step 5 depositing polysilicons in the first interarea and inverted trapezoidal groove, and polysilicon carve, only retain inverted trapezoidal The polysilicon of groove bottom, form shield grid；
Step 6 uses wet-etching technology, and groove internal oxidation layer is performed etching, and controls the depth of etching, removes shield grid The oxide layer of top, stairstepping oxide layer is formed in shield grid both sides；
Step 7 uses thermal oxidation technology, with groove in grow layer of oxide layer, formed above the shield grid in groove Cell body, the oxide layer of the cell body both sides is gate oxide；
Step 8 depositing polysilicons in cell body, the polysilicon fill up cell body, and the polysilicon in the cell body is led for grid Electric polysilicon；
Step 9 is led under the blocking of graphical photolithography plate in groove both sides successively injection the second conductive type impurity and first Electric type dopant, after pushing away trap, successively form the second conductivity type body region and the first conduction type source area；
Step 10 deposits insulating medium layer on the first interarea, and insulating medium layer is performed etching, in the second conduction type body The source contact openings of break-through the first conduction type source area are formed above area；
Step 11 fills metal in source contact openings, and metal is performed etching, and forms source metal.
Further, in the step 3, a thickness oxide layer is grown in the first interarea and groove, then pass through wet method Thick oxide layer on the interarea of erosion removal first, only retain the oxide layer in groove.
Further, in the step 7, the oxide layer of thermal oxidation method growth is also covered on the first interarea simultaneously；It is described Polysilicon in step 8 is also deposited in the oxide layer above the first interarea simultaneously, then to the polysilicon on the first interarea and Oxide layer performs etching, and exposes the first interarea and comes.
From the above, it can be seen that the beneficial effects of the present invention are：
1）It is pressure-resistant can to improve device by setting stairstepping oxide layer in shield grid both sides for device of the present invention；
2）Compared with tradition shields gate device, device of the present invention has lower conducting resistance；
3）Compared with tradition shields gate device, invention device can reduce chip area, cost-effective.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the Trench MOSFET cell cubes of prior art.
Fig. 2 is the cross-sectional view of the shield grid MOSFET cell cubes of prior art.
Fig. 3 is the cross-sectional view of the shield grid MOSFET cell cubes of the present invention.
Fig. 4 is the cross-sectional view that groove is formed in the embodiment of the present invention.
Fig. 5 is the cross-sectional view of filling thick oxide layer in groove in the embodiment of the present invention.
Fig. 6 is the cross-sectional view that step slot is formed in the embodiment of the present invention.
Fig. 7 is the cross-sectional view that shield grid is formed in the embodiment of the present invention.
Fig. 8 is the cross-sectional view that stairstepping oxide layer is formed in the embodiment of the present invention.
Fig. 9 is the cross-sectional view that gate oxide is formed in the embodiment of the present invention.
Figure 10 is the cross-sectional view that Gate Electrode Conductive polysilicon is formed in the embodiment of the present invention.
Brief description of the drawings：1- the first conduction type heavy doping substrate, the conductive type epitaxial layers of 2- first, the oxidation of 3- stairsteppings Layer, 4- grooves, 5- shield grids, 6- source contact openings, 7- Gate Electrode Conductives polysilicon, 8- gate oxides, 9- the second conduction type bodies Area, the first conduction types of 10- source area, 11- insulating medium layers, 12- source metals, 13- step slots, 14- cell bodies, 15- are thick Oxide layer, the interareas of 001- first, the interareas of 002- second.
Embodiment
With reference to specific embodiments and the drawings, the invention will be further described.
With reference to the accompanying drawings described in 3, for the shield grid MOS structure of the embodiment of the present invention by taking N-type conduction as an example, one kind has stairstepping The shield grid MOS structure of oxide layer, including cellular region and terminal protection area, the cellular region is located at the center of device, described Terminal protection area is looped around around the cellular region, and the cellular region is formed in parallel by several MOSFET element cell cubes, It is characterized in that：The MOSFET element cell cube includes semiconductor substrate, and the semiconductor substrate includes N-type heavy doping substrate 1 and the N-type epitaxy layer 2 on N-type heavy doping substrate 1, the upper surface of the N-type epitaxy layer 2 is the first of semiconductor substrate Interarea 001, the lower surface of N-type heavy doping substrate 1 are the second interarea 002 of semiconductor substrate, along the in N-type epitaxy layer 2 The direction that one interarea 001 points to the second interarea 002 is provided with groove 4, and the both sides of groove 4 are equipped with PXing Ti areas 9, the p-type body Area 9 in the N-type epitaxy layer 2, and it is internal be provided with N-type source region 10, the N-type source region 10 be located at left and right sides of groove 4 and It is adjacent, insulating medium layer 11 is provided with above the groove 4 and N-type source region 10, the both sides of insulating medium layer 11 are provided with source Pole contact hole 6, the source contact openings 6 are interior to be filled with metal, forms source metal 12, the source metal 12 connects through source electrode Contact hole 6 contacts with PXing Ti areas 9, and with the Ohmic contact of N-type source region 10, the source metal 12 and Gate Electrode Conductive polysilicon 7 it Between separated by insulating medium layer 11, it is characterised in that the groove 4 divides includes Gate Electrode Conductive for upper and lower two parts, upper part Polysilicon 7 and the gate oxide 8 positioned at the both sides of Gate Electrode Conductive polysilicon 7, lower part include stairstepping oxide layer 3 and stairstepping oxygen Change the shield grid 5 that layer 3 wraps up, the shield grid 5 is shaped as inverted trapezoidal；
The depth of groove 4 described in the embodiment of the present invention is 4 ~ 8um, and the step number in the stairstepping oxide layer 3 is 3 ~ 5, The height of each ladder is 1 ~ 3um, and the oxidated layer thickness of top layer ladder is 1000A ~ 5000A, the oxidation thickness of bottom ladder Spend for 6000A ~ 10000A, and last place differs about 5000A, oxygen between the Gate Electrode Conductive polysilicon 7 and shield grid 5 with thinnest part The thickness for changing layer is 2000A ~ 4000A.
The preparation method of the shield grid MOS structure with stairstepping oxide layer in above example, it is characterised in that bag Include following steps：
Step 1 provides N-type heavy doping substrate 1, the growth N-type epitaxy layer 2 on the N-type heavy doping substrate 1, outside the N-type The upper surface for prolonging layer 2 is the first interarea 001, and the lower surface of N-type heavy doping substrate 1 is the second interarea 002；
As shown in figure 4, step 2 blocking by Patterned masking layer, performs etching to the first interarea 001, in N-type extension Groove 4 is formed in layer 2, and removes mask layer；
As shown in figure 5, step 3 uses thermal oxide or HDP techniques, oxide layer is grown in groove 4, the oxide layer is filled up Groove 4；
In the step 3, a thickness oxide layer is grown in the first interarea 001 and groove 4, then remove by wet etching Thick oxide layer on first interarea 001, only retain the oxide layer in groove 4.
As shown in fig. 6, step 4 blocking by graphical photolithography plate, performs etching, shape to the oxide layer in groove 4 Into oxide layer groove, twice etching is carried out continuously to the oxide layer of oxide layer groove both sides, step slot is formed in groove 4 13, and remove photolithography plate；
As shown in fig. 7, step 5 depositing polysilicons in the first interarea 001 and step slot 13, and polysilicon is returned Carve, only retain the polysilicon of the bottom of step slot 13, form shield grid 5；
As shown in figure 8, step 6 uses wet-etching technology, the internal oxidation layer of groove 4 is performed etching, controls the depth of etching Degree, the oxide layer of the top of shield grid 5 is removed, stairstepping oxide layer 3 is formed in the both sides of shield grid 5；
As shown in figure 9, step 7 uses thermal oxidation technology, with growth layer of oxide layer, the screen in groove 4 in groove 4 Cover the top of grid 5 and form cell body 14, the oxide layer of the both sides of cell body 14 is gate oxide 8；
As shown in Figure 10, step 8 depositing polysilicons in cell body 14, the polysilicon fill up cell body 14, in the cell body 14 Polysilicon be Gate Electrode Conductive polysilicon 7；
In the step 7, the oxide layer of thermal oxidation method growth is also covered on the first interarea 001 simultaneously；In the step 8 Polysilicon is also deposited in the oxide layer of the top of the first interarea 001 simultaneously, then to the polysilicon on the first interarea 001 and oxidation Layer performs etching, and exposes the first interarea 001 and comes.
Step 9, in the both sides priority implanting p-type impurity of groove 4 and N-type impurity, is pushed away under the blocking of graphical photolithography plate After trap, PXing Ti areas 9 and N-type source region 10 are successively formed；
Step 10 deposits insulating medium layer 11 on the first interarea 001, insulating medium layer 11 is performed etching, in PXing Ti areas 9 Top forms the source contact openings of break-through N-type source region 10；
Step 11 fills metal in source contact openings, and metal is performed etching, and forms source metal 12.
Compared with traditional shielded gate structures, device of the invention has higher breakdown voltage when bearing pressure-resistant：This hair It is bright greatly to optimize the Electric Field Distribution in region between PXing Ti areas 9 and the bottom of groove 4 using stairstepping oxide layer 3, meeting, make two Electric Field Distribution between peak value electric field becomes more gentle and uniformly, when device is pressure-resistant is not easy breakdown at peak value, therefore can have Effect improves the breakdown voltage of device；
After break-over of device of the present invention, compared with traditional shielded gate structures, it is identical it is pressure-resistant in the case of, device of the present invention can use more Highly doped N-type epitaxy layer 2, the resistance of N-type epitaxy layer 2 is reduced, so as to reduce device on-resistance；More than being based on, the device Part has smaller chip area, improves the cost performance of device.

Claims (7)

1. a kind of shield grid MOS structure with stairstepping oxide layer, including cellular region and terminal protection area, the cellular position In the center of device, the terminal protection area is looped around around the cellular region, and the cellular region is by several MOSFET Device cell body is formed in parallel, and the MOSFET element cell cube includes semiconductor substrate, and the semiconductor substrate includes first Conduction type heavy doping substrate（1）And positioned at the first conduction type heavy doping substrate（1）On the first conductive type epitaxial layer （2）, first conductive type epitaxial layer（2）Upper surface be semiconductor substrate the first interarea（001）, the first conduction type Heavy doping substrate（1）Lower surface be semiconductor substrate the second interarea（002）, in the first conductive type epitaxial layer（2）Interior edge The first interarea（001）Point to the second interarea（002）Direction be provided with groove（4）, the groove（4）Both sides are equipped with second and led Electric type body region（9）, second conductivity type body region（9）Located at the first conductive type epitaxial layer（2）It is interior, and internal it is provided with the One conduction type source area（10）, the first conduction type source area（10）Positioned at groove（4）The left and right sides and adjoining, in institute State groove（4）With the first conduction type source area（10）Top is provided with insulating medium layer（11）, the insulating medium layer（11）Two Side is provided with source contact openings（6）, the source contact openings（6）It is interior to be filled with metal, form source metal（12）, the source electrode gold Category（12）Through source contact openings（6）With the second conductivity type body region（9）Contact, and with the first conduction type source area（10）Europe Nurse contacts, it is characterised in that the groove（4）Being divided into two parts, upper part up and down includes Gate Electrode Conductive polysilicon（7）With positioned at Gate Electrode Conductive polysilicon（7）The gate oxide of both sides（8）, lower part includes stairstepping oxide layer（3）And stairstepping oxide layer（3） The shield grid of parcel（5）.
A kind of 2. shield grid MOS structure with stairstepping oxide layer according to claim 1, it is characterised in that：It is described Shield grid（5）Be shaped as ladder-type structure.
A kind of 3. shield grid MOS structure with stairstepping oxide layer according to claim 1, it is characterised in that：It is described Stairstepping oxide layer（3）In step number be 3 ~ 5, the height of each ladder is 1 ~ 3um, and the oxidated layer thickness of top layer ladder For 1000A ~ 5000A, the oxidated layer thickness of bottom ladder is 6000A ~ 10000A.
A kind of 4. shield grid MOS structure with stairstepping oxide layer according to claim 1, it is characterised in that：It is described Gate Electrode Conductive polysilicon（7）And shield grid（5）Between the thickness of oxide layer be 2000A ~ 4000A.
A kind of 5. shield grid MOS structure with stairstepping oxide layer according to claim 1, it is characterised in that：It is described Source metal（12）With Gate Electrode Conductive polysilicon（7）Between pass through insulating medium layer（11）Separate.
A kind of 6. shield grid MOS structure with stairstepping oxide layer according to claim 1, it is characterised in that：It is described Groove（4）Depth be 4 ~ 8um.
A kind of 7. shield grid MOS structure with stairstepping oxide layer according to claim 1, it is characterised in that：For N Type MOS device, first conduction type are that N-type is conductive, and second conduction type is P-type conduction；For p-type MOS device, First conduction type is P-type conduction, and second conduction type is that N-type is conductive.
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CN110400846A (en) * 2019-08-19 2019-11-01 无锡橙芯微电子科技有限公司 With ladder deep trouth shield grid MOS structure and production method
CN110444595A (en) * 2019-08-21 2019-11-12 江苏中科君芯科技有限公司 IGBT device with inverted T shaped shield grid
CN110534574A (en) * 2019-07-16 2019-12-03 娜美半导体有限公司 Groove type metal oxide semiconductor field-effect tube
CN110676312A (en) * 2019-11-07 2020-01-10 苏州凤凰芯电子科技有限公司 Shielding grid MOS device terminal structure with step-type oxide layer and manufacturing method
CN110690272A (en) * 2019-11-07 2020-01-14 苏州凤凰芯电子科技有限公司 SJ MOS device structure combined with shielding grid and manufacturing method thereof
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CN110739346A (en) * 2019-11-07 2020-01-31 苏州凤凰芯电子科技有限公司 SJ MOS device terminal structure with shielding grid and manufacturing method thereof
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CN110400831A (en) * 2018-04-25 2019-11-01 英飞凌科技股份有限公司 Transistor device
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CN110444595A (en) * 2019-08-21 2019-11-12 江苏中科君芯科技有限公司 IGBT device with inverted T shaped shield grid
CN110676312A (en) * 2019-11-07 2020-01-10 苏州凤凰芯电子科技有限公司 Shielding grid MOS device terminal structure with step-type oxide layer and manufacturing method
CN110690272A (en) * 2019-11-07 2020-01-14 苏州凤凰芯电子科技有限公司 SJ MOS device structure combined with shielding grid and manufacturing method thereof
CN110707155A (en) * 2019-11-07 2020-01-17 苏州凤凰芯电子科技有限公司 Shielding grid MOS structure capable of improving reverse recovery characteristic and manufacturing method thereof
CN110739346A (en) * 2019-11-07 2020-01-31 苏州凤凰芯电子科技有限公司 SJ MOS device terminal structure with shielding grid and manufacturing method thereof
CN111312814A (en) * 2020-02-26 2020-06-19 无锡新洁能股份有限公司 Shielding type insulated gate bipolar transistor structure
CN111863969A (en) * 2020-07-17 2020-10-30 上海陆芯电子科技有限公司 Shielded gate trench type MOSFET device and method of manufacturing the same
TWI798899B (en) * 2021-10-28 2023-04-11 力晶積成電子製造股份有限公司 Semiconductor device and method for forming the same
US12100743B2 (en) 2021-10-28 2024-09-24 Powerchip Semiconductor Manufacturing Corporation Semiconductor device and method for forming the same
CN116110957A (en) * 2023-04-17 2023-05-12 深圳平创半导体有限公司 SiC multistage stepped split gate trench MOSFET device and manufacturing method thereof
CN116666445A (en) * 2023-07-25 2023-08-29 张家港凯思半导体有限公司 Low-grid internal resistance shielded grid trench MOSFET
CN116666445B (en) * 2023-07-25 2023-12-19 张家港凯思半导体有限公司 Low-grid internal resistance shielded grid trench MOSFET

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