CN207925474U - A kind of shield grid MOS structure with gradual change deep trouth - Google Patents
A kind of shield grid MOS structure with gradual change deep trouth Download PDFInfo
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- CN207925474U CN207925474U CN201721655473.0U CN201721655473U CN207925474U CN 207925474 U CN207925474 U CN 207925474U CN 201721655473 U CN201721655473 U CN 201721655473U CN 207925474 U CN207925474 U CN 207925474U
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 17
- 230000001413 cellular effect Effects 0.000 claims description 12
- 210000000746 body region Anatomy 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
The utility model proposes a kind of shield grid MOS structures with gradual change deep trouth, it is characterized in that, the shape of the groove is inverted trapezoidal, and it is divide into upper part and lower part, upper part includes inverted trapezoidal Gate Electrode Conductive polysilicon and the gate oxide positioned at inverted trapezoidal Gate Electrode Conductive polysilicon both sides, and lower part includes the inverted trapezoidal shield grid of thick oxide layer and thick oxide layer package；The utility model proposes shield grid MOS structure, pass through and graded slot be set so that the lower trench of inverted trapezoidal forms inverted trapezoidal shield grid and wraps up the thick oxide layer of inverted trapezoidal shield grid, device pressure resistance can be improved in such structure, conducting resistance is reduced, while chip area can be reduced, it is cost-effective.
Description
Technical field
The utility model is related to a kind of MOSFET element structure, especially a kind of shield grid MOS knots with gradual change deep trouth
Structure belongs to MOSFET technical fields.
Background technology
Metal-Oxide Semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect
Transistor, MOSFET) it is a kind of field-effect transistor that can be widely used in analog circuit and digital circuit.
As shown in Figure 1, being tradition Trench MOSFET element structures, as shown in Fig. 2, for traditional shield grid MOS knots
The voltage endurance capability of structure, two kinds of structures is the key parameter for characterizing device performance, always also is emphasis of people's attention, and tradition
Shield grid MOS structure shield grid and shield grid both sides oxide layer, be unanimous between the higher and lower levels, so that there are two for drift region
A peak electric field, one be in 2 intersection of the areas PXing Ti 9 and N-type epitaxy layer, the other is in the bottom of groove 4, two electric fields
The electric field of peak value middle section can be relatively low, and two such peak electric field easily punctures when being in device pressure resistance, influences device
Voltage endurance capability.
Invention content
On the basis of existing shielding grid MOSFET component disadvantage, a kind of performance is proposed
Excellent shielding grid MOSFET component structure and preparation method thereof, the structure is by being arranged graded slot（Inverted trapezoidal groove）, make
It obtains inverted trapezoidal lower trench to form inverted trapezoidal shield grid and wrap up the thick oxide layer of inverted trapezoidal shield grid, device can not only be improved in this way
The voltage endurance capability of part, and the conducting resistance of device can be reduced, while chip area can be reduced, it is cost-effective.
For the above technical purpose of realization, the technical solution of the utility model is：A kind of shield grid MOS with gradual change deep trouth
Structure, including cellular region and terminal protection area, the cellular region are located at the center of device, and the terminal protection area is looped around institute
It states around cellular region, the cellular region is formed in parallel by several MOSFET element cell cubes, the MOSFET element unit
Body includes semiconductor substrate, and the semiconductor substrate is including the first conduction type heavy doping substrate and is located at the first conduction type weight
The first conductive type epitaxial layer in doped substrate, the upper surface of first conductive type epitaxial layer are the of semiconductor substrate
One interarea, the lower surface of the first conduction type heavy doping substrate is the second interarea of semiconductor substrate, outside the first conduction type
Prolong in layer and be equipped with groove along the direction of the first interarea the second interarea of direction, the groove both sides are equipped with the second conduction type body
Area, second conductivity type body region is set in the first conductive type epitaxial layer, and is internally provided with the first conductive type source area,
First conductive type source area is located at left and right sides of groove and adjoining, on the groove and the first conductive type source area
Side is equipped with insulating medium layer, and the insulating medium layer both sides are equipped with source contact openings, metal is filled in the source contact openings,
Form source metal, the source metal contacts across source contact openings with the second conductivity type body region, and with the first conductive-type
Type source area Ohmic contact, which is characterized in that the shape of the groove is inverted trapezoidal, and is divide into upper part and lower part, top subpackage
Inverted trapezoidal Gate Electrode Conductive polysilicon and the gate oxide positioned at inverted trapezoidal Gate Electrode Conductive polysilicon both sides are included, lower part includes thick oxygen
Change the inverted trapezoidal shield grid of layer and thick oxide layer package.
Further, the thickness of the thick oxide layer is more than the thickness of gate oxide, and the thickness of the thick oxide layer is
The thickness of 3000A ~ 10000A, gate oxide are 800A ~ 1200A.
Further, in inverted trapezoidal groove, inverted trapezoidal Gate Electrode Conductive polysilicon and inverted trapezoidal shield grid inverted trapezoidal side wall
Angle with the second interarea of semiconductor substrate is 80 ° ~ 90 °.
Further, between the inverted trapezoidal Gate Electrode Conductive polysilicon and inverted trapezoidal shield grid oxide layer thickness be 2000A ~
4000A。
Further, it is separated by insulating medium layer between the source metal and inverted trapezoidal Gate Electrode Conductive polysilicon.
Further, the depth of inverted trapezoidal groove is 4 ~ 10um.
Further, for N-type MOS device, first conduction type is that N-type is conductive, and second conduction type is P
Type is conductive；For p-type MOS device, first conduction type is P-type conduction, and second conduction type is that N-type is conductive.
In order to further realize the above technical purpose, the utility model also proposes a kind of shielding with stairstepping oxide layer
The production method of grid MOS structure, which is characterized in that include the following steps：
Step 1 provides the first conduction type heavy doping substrate, is grown in the first conduction type heavy doping substrate
The upper surface of first conductive type epitaxial layer, first conductive type epitaxial layer is the first interarea, and the first conduction type is heavily doped
The lower surface of miscellaneous substrate is the second interarea；
Step 2 is blocked by Patterned masking layer, is performed etching to the first interarea, in the first conduction type extension
Groove is formed in layer, and removes mask layer；
Step 3 uses thermal oxide or HDP techniques, grows oxide layer in the trench, the oxide layer fills up groove；
Step 4 is blocked by graphical photolithography plate, is performed etching to the oxide layer in groove, and control laterally and
The ratio longitudinally etched forms inverted trapezoidal slot, and removes photolithography plate in the trench；
Step 5 depositing polysilicons in the first interarea and inverted trapezoidal slot, and polysilicon carve, only retain to fall
The polysilicon of dovetail groove lower part forms shield grid；
Step 6 uses wet-etching technology, is performed etching to groove internal oxidation layer, controls the depth of etching, removal screen
The oxide layer above grid is covered, stairstepping oxide layer is formed in shield grid both sides；
Step 7 uses thermal oxidation technology, with groove in grow layer of oxide layer, above shield grid in the trench
Groove body is formed, the oxide layer of the groove body both sides is gate oxide；
Step 8 depositing polysilicons in groove body, the polysilicon fill up groove body, and the polysilicon in the groove body is grid
Pole conductive polycrystalline silicon；
Step 9 is under the blocking of graphical photolithography plate, in groove both sides successively the second conductive type impurity of injection and the
One conductive type impurity after pushing away trap, successively forms the second conductivity type body region and the first conductive type source area；
Step 10 deposits insulating medium layer on the first interarea, is performed etching to insulating medium layer, in the second conductive-type
The source contact openings of the first conductive type source area of break-through are formed above the areas Xing Ti；
Step 11 fills metal in source contact openings, and is performed etching to metal, forms source metal.
Further, in the step 3, a thickness oxide layer is grown in the first interarea and groove, then pass through wet method
Thick oxide layer on the first interarea of erosion removal only retains the oxide layer in groove.
Further, in the step 7, the oxide layer of thermal oxidation method growth is also covered on the first interarea simultaneously；It is described
Polysilicon in step 8 is also deposited in the oxide layer above the first interarea simultaneously, then on the first interarea polysilicon and
Oxide layer performs etching, and the first interarea is made to expose.
From the above, it can be seen that the beneficial effects of the present invention are：
1）The utility model device is by being arranged graded slot（Inverted trapezoidal groove）So that inverted trapezoidal lower trench, which is formed, to fall
Device pressure resistance can be improved in the thick oxide layer of trapezoidal shield grid and package inverted trapezoidal shield grid, such structure；
2）Compared with tradition shields gate device, in the case of identical pressure resistance, the epitaxial layer of the utility model can possess higher
Doping concentration, to make device that there is lower conducting resistance；
3）Compared with tradition shields gate device, the utility model device can reduce chip area, cost-effective.
Description of the drawings
Fig. 1 is the cross-sectional view of the Trench MOSFET cell cubes of the prior art.
Fig. 2 is the cross-sectional view of the shield grid MOSFET cell cubes of the prior art.
Fig. 3 is the cross-sectional view of the shield grid MOSFET cell cubes of the present invention.
Fig. 4 is the cross-sectional view that groove is formed in the embodiment of the present invention.
Fig. 5 is the cross-sectional view that the first groove body is formed in the embodiment of the present invention.
Fig. 6 is the cross-sectional view that inverted trapezoidal shield grid is formed in the embodiment of the present invention.
Fig. 7 is the cross-sectional view that thick oxide layer is formed in the embodiment of the present invention.
Fig. 8 is the cross-sectional view that the second groove body and gate oxide are formed in the embodiment of the present invention.
Fig. 9 is the cross-sectional view that inverted trapezoidal Gate Electrode Conductive polysilicon is formed in the embodiment of the present invention.
Description of the drawings：The first conduction types of 1- heavy doping substrate, the first conductive type epitaxial layers of 2-, 3- thick oxide layers, 4-
Groove, 5- inverted trapezoidals shield grid, 6- source contact openings, 7- inverted trapezoidal Gate Electrode Conductives polysilicon, 8- gate oxides, 9- second are conductive
Type body region, the first conductive type source areas of 10-, 11- insulating medium layers, 12- source metals, the first groove bodies of 13-, 14- second
Groove body, the first interareas of 001-, the second interareas of 002-.
Specific implementation mode
With reference to specific embodiments and the drawings, the utility model is described in further detail.
With reference to the accompanying drawings described in 3, by taking N-type conduction as an example, described first leads the shield grid MOS structure of the utility model embodiment
Electric type is that N-type is conductive, and second conduction type is P-type conduction, a kind of shield grid MOS structure with gradual change deep trouth, packet
Cellular region and terminal protection area are included, the cellular region is located at the center of device, and the terminal protection area is looped around the cellular
Around area, the cellular region is formed in parallel by several MOSFET element cell cubes, and the MOSFET element cell cube includes
Semiconductor substrate, the semiconductor substrate is including the first conduction type heavy doping substrate 1 and is located at the first conduction type heavy doping
The first conductive type epitaxial layer 2 on substrate 1, the upper surface of first conductive type epitaxial layer 2 are the of semiconductor substrate
One interarea 001, the lower surface of the first conduction type heavy doping substrate 1 are the second interarea 002 of semiconductor substrate, in the first conduction
The direction for being directed toward the second interarea 002 in type epitaxial layer 2 along the first interarea 001 is equipped with groove 4, and 4 both sides of the groove are all provided with
There is the second conductivity type body region 9, second conductivity type body region 9 is set in the first conductive type epitaxial layer 2, and is internally provided with
First conductive type source area 10, first conductive type source area 10 is located at 4 left and right sides of groove and adjoining, in the ditch
Slot 4 and 10 top of the first conductive type source area are equipped with insulating medium layer 11, and 11 both sides of the insulating medium layer connect equipped with source electrode
Contact hole 6, the source contact openings 6 are interior to be filled with metal, forms source metal 12, and the source metal 12 passes through source contact openings
6 contact with the second conductivity type body region 9, and with 10 Ohmic contact of the first conductive type source area, the source metal 12 and fall
It is separated by insulating medium layer 11 between trapezoidal Gate Electrode Conductive polysilicon 7；It is characterized in that, the shape of the groove 4 is terraced
Shape, and being divide into upper part and lower part, upper part include inverted trapezoidal Gate Electrode Conductive polysilicon 7 and are located at inverted trapezoidal Gate Electrode Conductive polysilicon
The gate oxide 8 of 7 both sides, lower part include the inverted trapezoidal shield grid 5 that thick oxide layer 3 and thick oxide layer 3 wrap up, the thick oxidation
The thickness of layer 3 is more than the thickness of gate oxide 8；
The thickness of thick oxide layer in the utility model embodiment is 3000A ~ 10000A, and the thickness of gate oxide is 800A
~ 1200A, and in groove 4, inverted trapezoidal Gate Electrode Conductive polysilicon 7 and inverted trapezoidal shield grid 5 inverted trapezoidal side wall and semiconductor substrate
The angle of the second interarea 002 be 80 ° ~ 90 °, aoxidized between the inverted trapezoidal Gate Electrode Conductive polysilicon 7 and inverted trapezoidal shield grid 5
The thickness of layer is 2000A ~ 4000A, and the depth of inverted trapezoidal groove 4 is 4 ~ 10um, and the above concrete technology size is joined all in accordance with device
Number determines.
A kind of production method of shield grid MOS structure with gradual change deep trouth in above example, which is characterized in that packet
Include following steps：
Step 1 provides N-type heavy doping substrate 1, and N-type epitaxy layer 2, the N are grown in the N-type heavy doping substrate 1
The upper surface of type epitaxial layer 2 is the first interarea 001, and the lower surface of N-type heavy doping substrate 1 is the second interarea 002；
As shown in figure 4, step 2 blocking by Patterned masking layer, performs etching the first interarea 001, and control
Etching ratio laterally and longitudinally, forms the groove 4 of inverted trapezoidal in N-type epitaxy layer 2, and removes mask layer；
As shown in figure 5, step 3 uses thermal oxide or HDP techniques, layer of oxide layer is grown in groove 4, in groove 4
The first groove body 13 of middle formation；
In the step 3, layer of oxide layer is grown in the first interarea 001 and groove 4, then go by wet etching
Except the oxide layer on the first interarea 001, only retain the oxide layer in groove 4, forms the first groove body 13, and 13 side wall of the first groove body
Oxidated layer thickness it is identical as the thickness of thick oxide layer 3.
As shown in fig. 6, step 4 depositing polysilicons in the first interarea 001 and the first groove body 13, and to polysilicon into
It goes back quarter, only retains the polysilicon of 13 lower part of the first groove body, form inverted trapezoidal shield grid 5；
As shown in fig. 7, step 5 uses wet-etching technology, the oxide layer of the first groove body 13 is performed etching, is controlled
The depth of etching, the oxide layer of 5 top of removal inverted trapezoidal shield grid form thick oxide layer 3 in 5 both sides of inverted trapezoidal shield grid；
As shown in figure 8, step 6 uses thermal oxidation technology, layer of oxide layer is grown in groove 4, in groove 4
5 top of inverted trapezoidal shield grid forms the second groove body 14, and the oxide layer of 14 both sides of the second groove body is gate oxide 8；
As shown in figure 9, step 7 depositing polysilicons in the second groove body 14, the polysilicon fill up the second groove body 14,
Polysilicon in second groove body 14 is inverted trapezoidal Gate Electrode Conductive polysilicon 7；
In the step 6, the oxide layer of thermal oxidation method growth is also covered on the first interarea 001 simultaneously；The step 7
In polysilicon be also deposited on simultaneously in the oxide layer of the top of the first interarea 001, then on the first interarea 001 polysilicon and
Oxide layer performs etching, and the first interarea 001 is made to expose, and retains polysilicon and oxide layer in groove 4.
Step 8 is under the blocking of graphical photolithography plate, in the 4 both sides priority implanting p-type impurity of groove and N of inverted trapezoidal
Type impurity after pushing away trap, successively forms the areas PXing Ti 9 and N-type source region 10；
Step 9 deposits insulating medium layer 11 on the first interarea 001, is performed etching to insulating medium layer 11, in p-type
9 top of body area forms the source contact openings of break-through N-type source region 10；
Step 10 fills metal in source contact openings, and is performed etching to metal, forms source metal 12.
Compared with traditional shielded gate structures, the device of the utility model has higher breakdown voltage when bearing pressure resistance：
The utility model uses the groove 4 of inverted trapezoidal so that forms inverted trapezoidal shield grid 5 in groove 4 and wraps up inverted trapezoidal shield grid 5
Thick oxide layer 3, inverted trapezoidal structure can greatly optimize the field distribution in region between 4 bottom of the areas PXing Ti 9 and groove, and make
The field distribution of two transition between peak value and peak value become it is more gentle will uniformly, when device pressure resistance be not easy at peak value it is breakdown,
Therefore it can effectively improve the breakdown voltage of device；
After the utility model break-over of device, compared with traditional shielded gate structures, in the case of identical pressure resistance, the utility model
More highly doped N-type epitaxy layer 2 can be used in device, reduces the resistance of N-type epitaxy layer 2, to reduce device on-resistance；Base
In above, which can have smaller chip area, improve the cost performance of device.
Claims (7)
1. a kind of shield grid MOS structure with gradual change deep trouth, including cellular region and terminal protection area, the cellular region are located at device
The center of part, the terminal protection area are looped around around the cellular region, and the cellular region is by several MOSFET elements
Cell cube is formed in parallel, and the MOSFET element cell cube includes semiconductor substrate, and the semiconductor substrate includes first conductive
Type heavy doping substrate（1）And it is located at the first conduction type heavy doping substrate（1）On the first conductive type epitaxial layer（2）, institute
State the first conductive type epitaxial layer（2）Upper surface be semiconductor substrate the first interarea（001）, the first conduction type heavy doping
Substrate（1）Lower surface be semiconductor substrate the second interarea（002）, in the first conductive type epitaxial layer（2）It is interior along first
Interarea（001）It is directed toward the second interarea（002）Direction be equipped with groove（4）, the groove（4）Both sides are equipped with the second conduction type
Body area（9）, second conductivity type body region（9）Set on the first conductive type epitaxial layer（2）It is interior, and it is internally provided with the first conduction
Type source area（10）, first conductive type source area（10）Positioned at groove（4）The left and right sides and adjoining, in the groove
（4）With the first conductive type source area（10）Top is equipped with insulating medium layer（11）, the insulating medium layer（11）Both sides are equipped with
Source contact openings（6）, the source contact openings（6）It is interior to be filled with metal, form source metal（12）, the source metal（12）
Across source contact openings（6）With the second conductivity type body region（9）Contact, and with the first conductive type source area（10）Ohm connects
It touches, which is characterized in that the groove（4）Shape be inverted trapezoidal, and be divide into upper part and lower part, upper part includes inverted trapezoidal grid
Conductive polycrystalline silicon（7）With positioned at inverted trapezoidal Gate Electrode Conductive polysilicon（7）The gate oxide of both sides（8）, lower part includes thick aoxidizes
Layer（3）And thick oxide layer（3）The inverted trapezoidal shield grid of package（5）.
2. a kind of shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The thickness oxygen
Change layer（3）Thickness be more than gate oxide（8）Thickness, the thickness of the thick oxide layer is 3000A ~ 10000A, gate oxide
Thickness be 800A ~ 1200A.
3. a kind of shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The ladder
The groove of shape（4）, inverted trapezoidal Gate Electrode Conductive polysilicon（7）With inverted trapezoidal shield grid（5）The side wall of middle inverted trapezoidal with it is semiconductor-based
Second interarea of plate（002）Angle be 80 ° ~ 90 °.
4. a kind of shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The ladder
Shape Gate Electrode Conductive polysilicon（7）With inverted trapezoidal shield grid（5）Between oxide layer thickness be 2000A ~ 4000A.
5. a kind of shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The source electrode
Metal（12）With inverted trapezoidal Gate Electrode Conductive polysilicon（7）Between pass through insulating medium layer（11）It separates.
6. a kind of shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：The ladder
The groove of shape（4）Depth be 4 ~ 10um.
7. a kind of shield grid MOS structure with gradual change deep trouth according to claim 1, it is characterised in that：For N-type
MOS device, first conduction type are that N-type is conductive, and second conduction type is P-type conduction；For p-type MOS device, institute
It is P-type conduction to state the first conduction type, and second conduction type is that N-type is conductive.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107799585A (en) * | 2017-12-01 | 2018-03-13 | 苏州凤凰芯电子科技有限公司 | A kind of shield grid MOS structure with gradual change deep trouth |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107799585A (en) * | 2017-12-01 | 2018-03-13 | 苏州凤凰芯电子科技有限公司 | A kind of shield grid MOS structure with gradual change deep trouth |
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Effective date of registration: 20231222 Address after: Unit 802E, No. 155 Taidong Road, Siming District, Xiamen City, Fujian Province, 361000 Patentee after: Xiamen Xinheda Investment Co.,Ltd. Address before: 215612 2nd floor, building e, Fenghuang science and Technology Pioneer Park, Fenghuang Town, Zhangjiagang City, Suzhou City, Jiangsu Province Patentee before: SUZHOU FENGHUANGXIN ELECTRONIC TECHNOLOGY CO.,LTD. |
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