CN207398150U - Power semiconductor - Google Patents

Abstract

This application discloses power semiconductors.The power semiconductor includes：Multiple grooves in Semiconductor substrate, Semiconductor substrate are the first doping type, and multiple grooves are included respectively positioned at first to the 3rd groove in first area to the 3rd region of Semiconductor substrate；Splitting bar structure in first groove and second groove；It is located at the 3rd lower trench and the shield wiring and separation layer on top respectively；And source electrode, gate electrode and the bucking electrode being electrically connected with source region, grid conductor and shield wiring, wherein, bucking electrode reaches shield wiring via the contact hole through separation layer, and shield wiring is electrically connected with shielded conductor.The power semiconductor improves charge balance effect using the shield wiring of independent extraction electrode, and using separation layer the splitting bar structure of different zones and shield wiring is formed in public step, so as to reduce manufacture cost.

Description

Power semiconductor

Technical field

The utility model is related to technical field of electronic devices, more particularly, to power semiconductor.

Background technology

Power semiconductor is also known as power electronic devices, including power diode, thyristor, VDMOS (vertical double expansions Dispersed metallic oxide semiconductor) field-effect transistor, LDMOS (lateral diffusion metal oxide semiconductor) field-effect transistors with And IGBT (insulated gate bipolar transistor) etc..VDMOS field-effect transistors are included in the upper shape of apparent surface of Semiconductor substrate Into source region and drain region, in the on-state, electric current is mainly along the longitudinal flow of Semiconductor substrate.

In the high frequency of power semiconductor uses, lower conduction loss and switching loss are evaluation device performances Important indicator.On the basis of VDMOS field-effect transistors, further develop groove type MOS field-effect transistor, wherein, Grid conductor is formed in the trench, and gate-dielectric is formed on trenched side-wall to separate grid conductor and semiconductor layer, so as to The direction of side wall forms raceway groove in the semiconductor layer along groove.Groove (Trench) technique from level by raceway groove due to becoming vertical Directly, the influence of planar structure parasitism JFET resistance is eliminated, is substantially reduced cellular size.It is close to increase primitive unit cell on this basis Degree improves the overall width of unit area chip interior raceway groove, it is possible to so that channel width-over-length ratio increase of the device on unit silicon chip So that electric current increase, conducting resistance decline and relevant parameter is optimized, realize smaller size of tube core and possess bigger Power and high performance target, therefore trench process is more and more applies in novel power semiconductor.

However, with the raising of cell density, electrode resistance can increase, and switching loss accordingly increases, and gate leakage capacitance Cgd is straight Connect the switching characteristic for being related to device.In order to reduce gate leakage capacitance Cgd, division gate groove (Split Gate are further developed Trench is abbreviated as SGT) type power semiconductor, wherein, grid conductor extends to drift region, while grid conductor and leakage It is separated between pole using thick-oxide, so as to reduce gate leakage capacitance Cgd, improves switching speed, reduce switching loss.With This shielded conductor below grid conductor and is connected simultaneously with source electrode, common to be grounded, and is put down so as to introduce charge Weigh effect, has reduction surface field (Reduced Surface Field, abbreviation in the vertical direction of power semiconductor For RESURF) effect, conducting resistance Rdson is further reduced, so as to reduce conduction loss.

Cutting for the manufacturing method key step of SGT power semiconductors according to prior art is shown respectively in Fig. 1 a and 1b Face figure.As shown in Figure 1a, groove 102 is formed in Semiconductor substrate 101.The first insulating layer is formed in the lower part of groove 102 103, shielded conductor 104 fills groove 102.On the top of groove 102, two openings separated by shielded conductor 104 are formed.Into One step, as shown in Figure 1 b, gate-dielectric is formed in the upper portion side wall of groove 102 and the expose portion of shielded conductor 104 105, conductive material is filled to form two grid conductors 106 in two openings then separated in shielded conductor 104.

In the SGT power semiconductors, shielded conductor 104 is connected with the source electrode of power semiconductor, For generating RESURF effects.Two grid conductors 106 are located at the both sides of shielded conductor 104.Shielded conductor 104 is partly led with power It is separated by the first insulating layer 103 between the drain region of body device, is separated between gate electrode 106 by gate-dielectric 105.Grid It is separated between well region in conductor 106 and Semiconductor substrate 101 by gate-dielectric 105, so as to form raceway groove in well region.Such as Shown in figure, the thickness of the first insulating layer 103 is less than the thickness of gate-dielectric 105.

It is theoretical according to SGT, no matter which kind of SGT structure, the material of shielded conductor 104 is required for and the isolation of the second conductive material And the material for isolation needs to meet certain capacitance parameter, is otherwise susceptible to the short circuit of grid source, gate leakage capacitance Cgd exceptions etc. Failure.How optimised devices structure and to meet the parameter and reliability requirement of product, while wiring method accomplished most efficient, low Cost is the content to be studied of those skilled in the art.

Utility model content

In view of the above problems, the purpose of this utility model is to provide a kind of power semiconductor, wherein using independent The shield wiring of extraction electrode improves charge balance effect, and the wiring area of shielded conductor using separation layer to reduce technique Step.

It is according to the present utility model in a first aspect, provide a kind of manufacturing method of power semiconductor, including：First Form multiple grooves in the Semiconductor substrate of doping type, the multiple groove is included respectively positioned at the of the Semiconductor substrate First to the 3rd groove in one region to the 3rd region；Splitting bar knot is formed in the first groove and the second groove Structure, the splitting bar structure include shielded conductor, grid conductor and are clipped in second insulating layer therebetween；In the 3rd ditch Shield wiring is formed in slot；The body area of the second doping type is formed in the region of the Semiconductor substrate adjacent trench, it is described Second doping type is opposite with first doping type；The source region of first doping type is formed in the body area；With And source electrode, gate electrode and the bucking electrode being electrically connected respectively with the source region, source conductor and shield wiring are formed, In, separation layer is formed on the 3rd groove top, the shield wiring is located at the 3rd lower trench, the bucking electrode The shield wiring is reached via the contact hole through the separation layer, the shield wiring is electrically connected with the shielded conductor.

Preferably, the step of splitting bar structure is formed in the first groove and the second groove includes：Described Form insulating laminate on the side wall and bottom of first groove and the second groove, the insulating laminate include the first insulating layer and Second insulating layer, first insulating layer surround the second insulating layer；In the upper of the first groove and the second groove Portion and lower part are respectively formed the separation layer and the shielded conductor；Institute is removed in the first groove and the second groove Separation layer is stated, is open so as to be formed on the top of the first groove and the second groove；On the first groove top Gate-dielectric is formed on side wall；And the grid conductor is formed to fill the opening, wherein, the grid conductor and institute It states and is isolated from each other by the gate-dielectric between shielded conductor, by grid electricity between the grid conductor and the body area Medium is isolated from each other, and is isolated from each other between the shielded conductor and the Semiconductor substrate by the insulating laminate.

Preferably, the step of shield wiring is formed in the 3rd groove includes：The 3rd groove side wall and Insulating laminate is formed on bottom, the insulating laminate includes the first insulating layer and second insulating layer, and first insulating layer surrounds The second insulating layer；The separation layer and the shield wiring are respectively formed in the upper and lower part of the 3rd groove, In, it is isolated from each other between the shield wiring and the Semiconductor substrate by the insulating laminate.

Preferably, the shielding is formed simultaneously in the first groove, the second groove and the 3rd groove to lead Body and the shield wiring.

Preferably, the step of forming the grid conductor includes：Form conductor layer, first portion's filling of the conductor layer The opening, second portion extend laterally above the semiconductor substrate surface and the separation layer, in the 3rd groove In, the conductor layer and the shield wiring are separated from each other by the separation layer；And using the Semiconductor substrate as stopping Layer, the second portion of the conductor layer is removed using planarization, and the conductor layer stays in the first groove and second ditch First portion in slot forms the grid conductor.

Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area, The bucking electrode is located in the 3rd region, the first area, the second area and the 3rd region each other every It opens.

Preferably, first insulating layer is made of silica, and the second insulating layer is by being selected from silicon nitride, nitrogen oxides Or at least one of polysilicon composition, the separation layer are made of silica.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple The bottom width of groove.

Preferably, the step of forming the shielded conductor forms the step of shield wiring and forms the grid and lead The step of body, includes depositing at least once respectively.

Second aspect according to the present utility model provides a kind of power semiconductor, including：In Semiconductor substrate Multiple grooves, the Semiconductor substrate be the first doping type, the multiple groove include respectively be located at the semiconductor serve as a contrast First to the 3rd groove in the first area at bottom to the 3rd region；Division in the first groove and the second groove Grid structure, the splitting bar structure include shielded conductor, grid conductor and are clipped in second insulating layer therebetween；It is located at respectively 3rd lower trench and the shield wiring and separation layer on top；Positioned at the Semiconductor substrate Zhong Ti areas, the body area The neighbouring first groove top, and be the second doping type, second doping type is opposite with first doping type； Source region in the body area, the source region are first doping type；And with the source region, the grid conductor and Source electrode, gate electrode and the bucking electrode that the shield wiring is electrically connected, wherein, the bucking electrode via through The contact hole of the separation layer reaches the shield wiring, and the shield wiring is electrically connected with the shielded conductor.

Preferably, the splitting bar structure in the first groove and the second groove includes：Positioned at described first Groove and the second groove lower sides and the insulating laminate of bottom, the insulating laminate include the first insulating layer and second absolutely Edge layer, first insulating layer surround the second insulating layer；Screen positioned at the first groove and the second groove lower part Cover conductor；And the grid conductor positioned at the first groove and the first groove top, wherein, the grid conductor and institute It states and is isolated from each other by the gate-dielectric between shielded conductor, by grid electricity between the grid conductor and the body area Medium is isolated from each other, and is isolated from each other between the shielded conductor and the Semiconductor substrate by the insulating laminate.

Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area, The bucking electrode is located in the 3rd region, the first area, the second area and the 3rd region each other every It opens.

Preferably, first insulating layer is made of silica, and the second insulating layer is by being selected from silicon nitride, nitrogen oxides Or at least one of polysilicon composition, the separation layer are made of silica.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple The bottom width of groove.

Preferably, the power semiconductor is selected from cmos device, BCD devices, mosfet transistor, IGBT and Xiao One kind in special based diode.

In the method according to the utility model embodiment, SGT structures are formed in power semiconductor, wherein, Insulating laminate is formed between shielded conductor and Semiconductor substrate, so as to reduce gate leakage capacitance Cgd.The SGT structures include with it is described Source electrode, gate electrode and the bucking electrode that source region, the grid conductor and the shield wiring are electrically connected, the screen Wiring is covered to be electrically connected with the shielded conductor.The shield wiring of independent extraction electrode on shielded conductor for example for individually applying Bias voltage, so as to improve charge balance effect.Using separation layer so that the splitting bar structure and shielded conductor of different zones can To be formed in public step, so as to reduce manufacture cost..

This method realizes SGT structures by better simply processing step, solves complex process in common process, is susceptible to While the problems such as grid source is short-circuit, gate leakage capacitance Cgd is abnormal is so as to meet the parameter of product and reliability requirement, with reference to specific work Wiring method is accomplished most efficient, low cost by skill step.Compared with prior art, based on 0.18~0.25um techniques, this method The photoresist mask used in currently manufactured technique can be reduced by 3~4 photoresist masks.

The utility model embodiment use a kind of reduction source drain capacitance separate gate power semiconductor device structure and its Forming method can also apply in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.

Description of the drawings

By the description referring to the drawings to the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from, in the accompanying drawings：

The section of the manufacturing method key step of power semiconductor according to prior art is shown respectively in Fig. 1 a and 1b Figure.

Fig. 2 shows the flow chart of the manufacturing method of the power semiconductor according to this implementation new embodiment.

Fig. 3 a to 3i show the sectional view of the method, semi-conductor device manufacturing method different phase according to this implementation new embodiment.

Specific embodiment

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Reference numeral represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown Some well known parts.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.

It should be appreciated that in the structure of outlines device, it is known as when by a floor, a region positioned at another floor, another area When domain " above " or " top ", can refer to above another layer, another region or its with another layer, it is another Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

It if, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and And A and B is abutted rather than A is located in the doped region formed in B.

In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices The general designation of conductor structure, including all layers formed or region.

Many specific details of the utility model, such as the structure of device, material, size, place is described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art Material is formed.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC and IV race semiconductor, such as Si、Ge。

Fig. 2 shows the flow chart of the manufacturing method of the SGT power semiconductors according to the utility model embodiment, Fig. 3 a The sectional view in different step is shown respectively to 3i.It is described below in conjunction with Fig. 2 and 3a to 3i according to the utility model embodiment Manufacturing method the step of.

This method starts from Semiconductor substrate 101.Semiconductor substrate is, for example, to be doping to the silicon substrate of N-type, the silicon substrate Longitudinal uniform doping, resistivity is for example between the scope of 1~15 Ω cm.Semiconductor substrate has opposite first surface And second surface.Preferably, in the first surface of Semiconductor substrate, the works such as photoetching, etching, ion implanting, impurity activation are passed through Skill forms the partial pressure ring structure of power semiconductor, and the partial pressure ring structure belongs to the well known knot of one kind of this field device architecture Structure part, this will not be detailed here.Preferably, the Semiconductor substrate 101 used in the present embodiment could be formed with MOS field-effects crystalline substance The semiconductor devices such as body pipe, IGBT isolated-gate field effect transistor (IGFET)s, Schottky diode.

In step S101, in the first area of Semiconductor substrate 101 201,202 and the 3rd region 203 of second area Groove 102 is respectively formed, as shown in Figure 3a.

Include forming Etching mask by photoetching and etching for forming the technique of groove 102, via Etching mask Opening etching removal Semiconductor substrate 101 expose portion.

In this embodiment, first area 201 refers to that the wiring area of source region in SGT structures, second area 202 refer to It is the wiring area of grid conductor in SGT structures, second area 203 refers to the wiring area of shielded conductor in SGT structures.

Groove 102 is extended downwardly from the surface of Semiconductor substrate 101, and is reached in the Semiconductor substrate 101 and made a reservation for Depth.In this embodiment, the width of groove 102 is, for example, 0.2 to 10 micron, and depth is, for example, 0.1 to 50 micron.SGT The width of the groove of structure is wider much than the groove of the convention trench power semiconductor of identical conducting level of efficiency, and its The depth of groove is also deeply more many than the groove of convention trench power semiconductor.

Preferably, the sidewall slope of groove 102, for example, compared with vertical trench 102 top into 85 to 89 degree angle, So that the bottom width of groove 102 is less than top width.The angle of groove is more oblique, beneficial to follow-up each dielectric layer, conductive material Filling reduces the defects of blind leads to problems such as.

In step s 102, insulating laminate is sequentially formed on the surface of Semiconductor substrate 101, which is included altogether The first insulating layer 122 and second insulating layer 123 of shape, as shown in Figure 3b.

In groove 102, the first insulating layer 122 surrounds second insulating layer 123.First insulating layer 122 and second insulating layer 123 are made of different insulating materials.In this embodiment, the first insulating layer 122 is for example made of silica.Second insulating layer 123 are for example formed by being selected from least one of silicon nitride, nitrogen oxides or polysilicon.Preferably, second insulating layer 123 is by nitrogen SiClx forms.The thickness of first insulating layer 122 is, for example, 500 to 50000 angstroms, the thickness of second insulating layer 123 be, for example, 50 to 5000 angstroms.The thickness of first insulating layer 122 is bigger, then gate leakage capacitance Cgd is smaller.

Include for forming the technique of the first insulating layer 122 through thermal oxide, chemical vapor deposition (CVD) or high density etc. Ion body chemical vapor phase growing forms oxide layer in the inner wall of groove 102.The side of the oxide layer conformally covering groove 102 Wall and bottom, so as to still retain a part of inner space of groove 102.

Include for forming the technique of second insulating layer 123 through chemical vapor deposition (CVD) or high-density plasma Chemical vapor deposition forms nitride layer on 122 surface of the first insulating layer.The nitride layer conformally covers the first insulating layer 122 surface, so as to still retain a part of inner space of groove 102.

In step s 103, shielded conductor is formed in first area 201 and 102 lower part of groove of second area 202, the 102 lower part of groove in three regions 203 forms shield wiring 131 and forms separation layer 132 on groove top, as shown in Figure 3c.

In this embodiment, shielded conductor 104 and shield wiring 131 are formed using same conductor layer, for example, respectively by Non-crystalline silicon or the polysilicon composition of doping.Separation layer 132 is for example made of silica.Technique for forming conductor layer is for example wrapped It includes using process deposits polysilicons such as sputterings so that polysilicon fills the remainder of groove 102.Then, etched conductors layer and Second insulating layer 123 is open with removing the part positioned at the outside of groove 102 and top so as to be formed on the top of groove 102. Separation layer 132 is filled in the opening of groove 102.Preferably, after the step of filling separation layer 132, further useization It learns mechanical planarization (CMP) and removes 132 and first insulating layer 122 of separation layer being located at outside groove 102.

Preferably, it is made of for forming the conductor layer of shielded conductor 104 and shield wiring 131 polysilicon.The polysilicon Deposition velocity be, for example, 1 to 100 angstrom per minute, depositing temperature is, for example, 510 to 650 degrees Celsius, thickness be, for example, 1000 to 100000 angstroms.By controlling the doping concentration of conductor layer, its resistance can be adjusted.In this embodiment, the square electricity of conductor layer It is, for example, less than 20 ohm to hinder Rs.Further, the square resistance Rs of conductor layer is smaller, is formed during subsequent oxidation layer Oxidated layer thickness is bigger compared with silicon.Further, the material selection amorphous of conductor layer, it is easier to form lower square resistance Rs。

In above-mentioned deposition step, one or many depositions may be employed and form conductor layer material.In Multiple depositions, The rate of subsequent deposition process is less than previous deposition step, so as to which sedimentation rate is gradually reduced.In trench fill process, deposition The slower filling effect of rate is better, the difficult filling of channel bottom packing ratio the top of the groove, therefore in multiple filling, it is previously deposited Rate needs to be less than the rate of any primary depositing below.

In above-mentioned etching step, wet etching may be employed.Due to the selectivity of etchant, compared with the first insulation Layer 122 removes the expose portion of conductor layer.The etching not only removes conductor layer and second insulating layer 123 is located at outside groove 102 Part, but also etch-back conductor layer and second insulating layer 123 are located at the part inside groove 102.After the etching, this is led The part that body layer retains in the groove 102 of first area 201 and second area 202 forms shielded conductor 104, in the 3rd region The part retained in 203 groove 102 forms shield wiring 131.Preferably, which includes etching twice, using not In first time etches, the expose portion of conductor layer is removed compared with second insulating layer 123 for same etchant, in second of erosion In quarter, compared with the expose portion of the first insulating layer 122 removal second insulating layer 123.After the etch back, in groove 102 The opening of predetermined depth is formed, for example, the depth is to extend downwardly 0.2 to 4 micron from the surface of Semiconductor substrate 101.

In above-mentioned chemical-mechanical planarization step, using Semiconductor substrate 101 as stop-layer, so as to not only remove Conductor layer is located at the part outside groove 102, and further also removal 132 and first insulating layer 122 of separation layer is located at outside groove 102 The part in portion.Therefore, the top of 132 and first insulating layer 122 of separation layer is flushed with the surface of the first insulating layer 122.

It should be noted that in figure 3 c, for clarity, in not separately shown first insulating layer 122 in the top of groove 102 Part, but by 132 and first insulating layer 122 of separation layer this is shown partially for whole separation layer 132.In the embodiment In, 132 and first insulating layer 122 of separation layer is made of and adjacent to each other silica, therefore in the device structure without clear Clear border.

In step S104, etching removal 132 and first insulating layer of separation layer in the groove of first area and second area 122, so as to form opening 124 on the top of groove 102, as shown in Figure 3d.The opening 124 exposes the top of groove 102 again Side wall.

In the etching step, Etching mask is formed by photoetching and etching, with the first of exposing semiconductor substrate 101 Region 201 and second area 202 and the 3rd region 203 for blocking Semiconductor substrate 101.The etch process is, for example, wet method Etching.Due to the selectivity of etchant, the exposure of 132 and first insulating layer 122 of separation layer is removed compared with Semiconductor substrate 101 Part.The depth that opening 124 is extended downwardly from the surface of Semiconductor substrate 101 is, for example, 0.5 to 5 micron.The etch depth pair 102 top of groove should be located in the thickness of separation layer 132 so as to remove 132 and first insulating layer 122 of separation layer completely Part.After the etching, the first insulating layer 122 is located at the lower sides of groove 102 and the part reservation of bottom so that screen It covers and is still isolated from each other between the lower part of conductor 104 and shield wiring 131 and Semiconductor substrate 101 by insulating laminate.

In step S105, gate-dielectric 105 is formed in the upper portion side wall of groove 102 and the top of shielded conductor 104, As shown in Figure 3 e.

Thermal oxide may be employed in technique for forming gate-dielectric 105.The temperature of the thermal oxide be, for example, 950 to 1200 degrees Celsius.The exposure silicon materials of Semiconductor substrate 101 and shielded conductor 104 form silica in thermal oxidation process. In step of thermal oxidation, the surface of Semiconductor substrate 101 is also exposed in atmosphere.Gate-dielectric 105 is not placed only in groove 102 Upper portion side wall on, and be covered on the surface of Semiconductor substrate 101.

Compared with fine and close Semiconductor substrate 101, shielded conductor 104 is the amorphous or polycrystalline material of heavy doping, structure More loose, doping concentration is higher.As a result, gate-dielectric 105 is located at the thickness ratio of the second portion on 104 surface of shielded conductor The thickness of first portion on 101 surface of Semiconductor substrate and in groove 102 is big.The first portion of gate-dielectric 105 Thickness be, for example, 50 to 5000 angstroms, the thickness of second portion is, for example, 60 to 10000 angstroms.

In step s 106, grid conductor 106 and adjacent with groove 102 in Semiconductor substrate 101 is formed in the trench Region in form body area 107 and source region 108, as illustrated in figure 3f.

The grid conductor 106 is for example made of the non-crystalline silicon or polysilicon that adulterate.For forming the technique of grid conductor 106 Such as including using process deposits polysilicons such as sputterings so that the opening at 104 top of polysilicon filling shielded conductor.

The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius, Thickness is, for example, 1000 to 100000 angstroms.By the doping concentration of control gate conductor 106, its resistance can be adjusted.In the reality It applies in example, the square resistance Rs of grid conductor 106 is, for example, less than 20 ohm.Further, the square resistance Rs of grid conductor 106 Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, grid conductor 106 Material selection amorphous, it is easier to form lower square resistance Rs.

In above-mentioned deposition step, one or many materials for depositing and forming grid conductor 106 may be employed.Multiple During deposition, the rate of subsequent deposition process is less than previous deposition step, so as to which sedimentation rate is gradually reduced.In trench fill process In, the slower filling effect of sedimentation rate is better, the difficult filling of channel bottom packing ratio the top of the groove, therefore in multiple filling, it is preceding The rate of face deposition needs to be less than the rate of any primary depositing below.

The polysilicon includes the first portion in the groove of first area 201 and second area 202 and is partly leading The second portion extended laterally on the surface of body substrate 101.In the groove of second area 203, separation layer 132 fills groove Polysilicon and shielded conductor 106 are separated from each other by the opening on 102 tops.

Then, etching removal polysilicon is located at the second portion that 101 surface of Semiconductor substrate extends laterally so that more Crystal silicon fills the opening 124 on 102 top of groove only in the first area of Semiconductor substrate 101 and second area, so as to be formed Grid conductor 106.

Then, PXing Ti areas 107 are formed in Semiconductor substrate 101 and the source region of N-type is formed in body area 107. Technique for forming body area 107 and source region 108 is, for example, multiple ion implanting.By the way that suitable dopant is selected to form difference Then the doped region of type carries out thermal annealing with activator impurity.In ion implanting, using grid conductor 106 and separation layer 132 As hard mask, body area 107 and the lateral position of source region 108 can be limited, so as to save photoresist mask.It should be from The angle of son injection is, for example, zero degree, i.e., compared with the surface vertical injection of Semiconductor substrate 101.By controlling ion implanting Energy, the injection depth of body area 107 and source region 108 can be limited, so as to limit upright position.

When forming body area 107, for B11 or BF2 or first note B11 notes BF2 again for the dopant that uses, injects energy It measures as 20~100Kev, implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.Forming source region 108 When, the dopant used for P+ or AS+, Implantation Energy be 60~150Kev, implantation dosage be 1E14~1E16, thermal annealing temperatures For 800 to 1100 degrees Celsius.

In this step, SGT structures are formed in the groove 102 of first area 201 and second area 202, including being located at Shielded conductor 104 and grid conductor 106 in groove.Grid conductor 106 include be located at groove 102 in first portion and The second portion extended above Semiconductor substrate 101.The first portion of grid conductor 106 is formed in 104 both sides of shielded conductor Opening 124 in, be clipped in the middle so as to shielded conductor 104.By second insulating layer between shielded conductor 104 and grid conductor 106 123 are isolated from each other.The lower part of shielded conductor 104 extends to the lower part of groove 102, folded by insulating between Semiconductor substrate 101 Layer is being isolated each other, which includes the first insulating layer 122 and second insulating layer 123.Grid conductor 106 and body area 107 It is adjacent with source region 108, and be isolated from each other by gate-dielectric 105.

In step s 107, the dielectric layer 109 between the surface deposits of semiconductor structure, as shown in figure 3g.

Interlayer dielectric layer 109 covers the first area of Semiconductor substrate 101 and second area interlayer dielectric layer 109 can be by Selected from least one of silica, silicon nitride, silicon oxynitride composition, and can be individual layer or laminated construction.In the reality It applies in example, interlayer dielectric layer 109 for example can be the boron-phosphorosilicate glass (BPSG) that thickness is 2000 to 15000 angstroms.

In step S108, formed in interlayer dielectric layer 109 and reach source region 108, grid conductor 106 and shield wiring 131 multiple contact holes 125 and contact zone 110 is respectively formed in the bottom of multiple contact holes 125 by ion implanting, such as Shown in Fig. 3 h.

Technique for forming contact hole 125 is, for example, dry etching.The sidewall slope of contact hole 125, such as compared with The angle that the top of vertical trench 102 is spent into 85 to 89.9 so that the bottom width of contact hole 125 is less than top width.Contact The angle in hole 125 is more oblique, beneficial to the filling of subsequent conductive material, reduces the defects of blind leads to problems such as.

In the first area of Semiconductor substrate 101 201, first group of contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109 and gate-dielectric 105, extend to the predetermined depth in shield wiring 131, and second group of contact hole is worn successively Cross the predetermined depth in interlayer dielectric layer 109, gate-dielectric 105, the arrival body of source region 108 area 107.The predetermined depth is, for example, 0.1 to 1 micron.

In the second area 202 of Semiconductor substrate 101, second group of contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109 extends to the predetermined depth in grid conductor 106.

In the 3rd region 203 of Semiconductor substrate 101, the 3rd group of contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109, separation layer 132, extend to the predetermined depth in shield wiring 131.

In ion implanting, using interlayer dielectric layer as hard mask, the lateral position of contact zone 110 is limited, so as to To save photoresist mask.For B11 or BF2 or first note B11 notes BF2 to the dopant that the ion implanting uses again, Implantation Energy is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.In ion After injection, thermal annealing can be carried out to activate dopant.

In step S109, source electrode 111, gate electrode 112 and bucking electrode 113 are formed, as shown in figure 3i.

The step is for example including deposited metal layer and patterning.The metal layer for example by be selected from Ti, TiN, TiSi, W, One kind or its alloy composition in AL, AlSi, AlSiCu, Cu, Ni.By etching by metal layer pattern be melted into source electrode 111, Gate electrode 112 and bucking electrode 113.As shown in the figure, source electrode 111, gate electrode 112 and bucking electrode 113 each other every From.

In the first area of Semiconductor substrate 101 201, source electrode 111 is via in the multiple contact hole 125 One group of contact hole reaches source region 108.

In the second area 202 of Semiconductor substrate 101, gate electrode 112 is via in the multiple contact hole 125 Two groups of contact holes reach grid conductor 106.

In the 3rd region 203 of Semiconductor substrate 101, bucking electrode 113 is via in the multiple contact hole 125 Three groups of contact holes reach shield wiring 131.

After step S109, the metallization of power semiconductor is had been carried out.Further, according to the needs of product, Passivation layer protection can be increased, complete the processing of power semiconductor Facad structure.By being thinned, carrying on the back a systems such as gold, scribing Row postchannel process completes the final realization of device.

It should be noted that although in above-mentioned sectional view, shielded conductor 104 and shield wiring 131 in different grooves that This isolation, grid conductor 106 are isolated from each other, however, in actual power semiconductor, it is above-mentioned from planar structure Shielded conductor 104 and shield wiring 131 in different grooves can be connected to each other, and grid conductor 106 can also be connected to each other. In a kind of embodiment, which is, for example, that the grid conductor 106 in different grooves 102 is integrally formed by single conductive layer, And shielded conductor 104 in different grooves 102 and shield wiring 131 are integrally formed by single conductive layer.In the implementation of replacement In example, which is, for example, to utilize public bucking electrode 113 by the shielded conductor 104 in different grooves 102 and shielding Wiring 131 is connected to each other and is connected the grid conductor 106 in different grooves 102 each other using public gate electrode 112 It connects.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those Element, but also including other elements that are not explicitly listed or further include as this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that Also there are other identical elements in process, method, article or equipment including element.

Embodiment according to the utility model is for example above, these embodiments are there is no all details of detailed descriptionthe, also not Limit the specific embodiment that the utility model is only.Obviously, as described above, can make many modifications and variations.This explanation Book is chosen and specifically describes these embodiments, is the principle and practical application in order to preferably explain the utility model, so that Skilled artisan can be used using the utility model and the modification on the basis of the utility model well.This Utility model is limited only by the claims and their full scope and equivalents.

Claims (7)

1. a kind of power semiconductor, which is characterized in that including：

Multiple grooves in Semiconductor substrate, the Semiconductor substrate are the first doping type, and the multiple groove includes Respectively positioned at first to the 3rd groove in first area to the 3rd region of the Semiconductor substrate；

Splitting bar structure in the first groove and the second groove, the splitting bar structure include shielded conductor, Grid conductor and it is clipped in second insulating layer therebetween；

It is located at the 3rd lower trench and the shield wiring and separation layer on top respectively；

Positioned at the Semiconductor substrate Zhong Ti areas, the body area is the second doping type adjacent to the first groove top, Second doping type is opposite with first doping type；

Source region in the body area, the source region are first doping type；And

Source electrode, gate electrode and the shielding being electrically connected with the source region, the grid conductor and the shield wiring Electrode,

Wherein, the bucking electrode reaches the shield wiring, the shield wiring via the contact hole through the separation layer It is electrically connected with the shielded conductor.

2. power semiconductor according to claim 1, which is characterized in that the first groove and the second groove In the splitting bar structure include：

Positioned at the first groove and the second groove lower sides and the insulating laminate of bottom, the insulating laminate includes the One insulating layer and second insulating layer, first insulating layer surround the second insulating layer；

Shielded conductor positioned at the first groove and the second groove lower part；And

Grid conductor positioned at the first groove and the first groove top,

Wherein, it is isolated from each other between the grid conductor and the shielded conductor by the gate-dielectric, the grid conductor It is isolated from each other between the body area by the gate-dielectric, by described between the shielded conductor and the Semiconductor substrate Insulating laminate is isolated from each other.

3. power semiconductor according to claim 2, which is characterized in that the source electrode is located at firstth area In domain, the gate electrode is located in the second area, and the bucking electrode is located in the 3rd region, firstth area Domain, the second area and the 3rd region are separated from each other.

4. power semiconductor according to claim 2, which is characterized in that first insulating layer is by silica group Into the second insulating layer is formed by being selected from least one of silicon nitride, nitrogen oxides or polysilicon, and the separation layer is by oxygen SiClx forms.

5. power semiconductor according to claim 2, which is characterized in that first doping type is N-type and p-type In one kind, second doping type be N-type and p-type in another kind.

6. power semiconductor according to claim 2, which is characterized in that the sidewall slope of the multiple groove makes The top width for obtaining the multiple groove is more than the bottom width of the multiple groove.

7. power semiconductor according to claim 2, which is characterized in that the power semiconductor be selected from One kind in cmos device, BCD devices, mosfet transistor, IGBT and Schottky diode.