CN107910270A - Power semiconductor and its manufacture method - Google Patents
Power semiconductor and its manufacture method Download PDFInfo
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- CN107910270A CN107910270A CN201711148753.7A CN201711148753A CN107910270A CN 107910270 A CN107910270 A CN 107910270A CN 201711148753 A CN201711148753 A CN 201711148753A CN 107910270 A CN107910270 A CN 107910270A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
This application discloses power semiconductor and its manufacture method.This method includes：Multiple grooves are formed in the semiconductor substrate；Splitting bar structure is formed in first groove and second groove；Shield wiring is formed in the 3rd groove；In the Semiconductor substrate Zhong Ti areas；Source region is formed in the body area；And form source electrode, gate electrode and the bucking electrode being electrically connected respectively with the source region, source conductor and shield wiring, wherein, the shield wiring is electrically connected with the shielded conductor, and the shield wiring includes the Part II filled the Part I of the 3rd groove and extended laterally in the semiconductor substrate surface, the Part II is used to reroute.This method improves charge balance effect using the shield wiring of independent extraction electrode, and shield wiring is used to reroute to improve yield of devices and reliability.
Description
Technical field
The present invention relates to technical field of electronic devices, more particularly, to power semiconductor and its manufacture method.
Background technology
Power semiconductor is also known as power electronic devices, including power diode, thyristor, VDMOS (vertical double expansions
Dispersed metallic oxide semiconductor) field-effect transistor, LDMOS (lateral diffusion metal oxide semiconductor) field-effect transistors with
And IGBT (insulated gate bipolar transistor) etc..VDMOS field-effect transistors are included in the upper shape of apparent surface of Semiconductor substrate
Into source region and drain region, in the on-state, longitudinal flow of the electric current mainly along Semiconductor substrate.
In the high frequency of power semiconductor uses, lower conduction loss and switching loss are evaluation device performances
Important indicator.On the basis of VDMOS field-effect transistors, further develop groove type MOS field-effect transistor, wherein,
Grid conductor is formed in the trench, and gate-dielectric is formed on trenched side-wall to separate grid conductor and semiconductor layer, so that
Raceway groove is formed in the semiconductor layer along the direction of trenched side-wall.Groove (Trench) technique from level by raceway groove due to becoming vertical
Directly, the influence of planar structure parasitism JFET resistance is eliminated, is substantially reduced cellular size.It is close to increase primitive unit cell on this basis
Degree, improves the overall width of unit area chip interior raceway groove, it is possible to so that channel width-over-length ratio increase of the device on unit silicon chip
So that electric current increase, conducting resistance decline and relevant parameter is optimized, realize smaller size of tube core and possess bigger
Power and high performance target, therefore trench process is more and more applies in novel power semiconductor.
However, with the raising of cell density, electrode resistance can increase, and switching loss accordingly increases, and gate leakage capacitance Cgd is straight
Connect the switching characteristic for being related to device.In order to reduce gate leakage capacitance Cgd, division gate groove (Split Gate are further developed
Trench, is abbreviated as SGT) type power semiconductor, wherein, grid conductor extends to drift region, while grid conductor and leakage
Separated between pole using thick-oxide, so as to reduce gate leakage capacitance Cgd, improve switching speed, reduce switching loss.With
This shielded conductor below grid conductor and is connected with source electrode at the same time, and common ground connection, puts down so as to introduce electric charge
Weigh effect, has reduction surface field (Reduced Surface Field, abbreviation in the vertical direction of power semiconductor
For RESURF) effect, further reduces conducting resistance Rdson, so as to reduce conduction loss.
Cutting for the manufacture method key step of SGT power semiconductors according to prior art is shown respectively in Fig. 1 a and 1b
Face figure.As shown in Figure 1a, groove 102 is formed in Semiconductor substrate 101.The first insulating layer is formed in the lower part of groove 102
103, shielded conductor 104 fills groove 102.On the top of groove 102, two openings separated by shielded conductor 104 are formed.Into
One step, as shown in Figure 1 b, gate-dielectric is formed in the upper portion side wall of groove 102 and the expose portion of shielded conductor 104
105, then conductive material is filled in two openings that shielded conductor 104 separates to form two grid conductors 106.
In the SGT power semiconductors, shielded conductor 104 is connected with the source electrode of power semiconductor,
For producing RESURF effects.Two grid conductors 106 are located at the both sides of shielded conductor 104.Shielded conductor 104 is partly led with power
Separated by the first insulating layer 103 between the drain region of body device, separated between gate electrode 106 by gate-dielectric 105.Grid
Separated between well region in conductor 106 and Semiconductor substrate 101 by gate-dielectric 105, so as to form raceway groove in well region.Such as
Shown in figure, the thickness of the first insulating layer 103 is less than the thickness of gate-dielectric 105.
It is theoretical according to SGT, no matter which kind of SGT structure, the material of shielded conductor 104 is required for and the isolation of the second conductive material
And the material for isolating needs to meet certain capacitance parameter, otherwise easily there is the short circuit of grid source, gate leakage capacitance Cgd exceptions etc.
Failure.How optimised devices structure and to meet the parameter and reliability requirement of product, while wiring method accomplished most efficient, low
Cost is the content to be studied of those skilled in the art.
The content of the invention
In view of the above problems, it is an object of the invention to provide a kind of power semiconductor and its manufacture method, wherein
Using independent extraction electrode shield wiring improve charge balance effect, and the wiring area of shielded conductor using separation layer with
Reduce processing step.
According to the first aspect of the invention, there is provided a kind of manufacture method of power semiconductor, including：In the first doping
Multiple grooves are formed in the Semiconductor substrate of type, the multiple groove includes being located at the firstth area of the Semiconductor substrate respectively
First to the 3rd groove in domain to the 3rd region；Splitting bar structure, institute are formed in the first groove and the second groove
Stating splitting bar structure includes shielded conductor, grid conductor and is clipped in the second insulating layer therebetween；In the 3rd groove
Form at least a portion of shield wiring；The body of the second doping type is formed in the region of the Semiconductor substrate adjacent trench
Area, second doping type are opposite with first doping type；First doping type is formed in the body area
Source region；And form source electrode, gate electrode and the shielding being electrically connected respectively with the source region, source conductor and shield wiring
Electrode, wherein, the shield wiring is electrically connected with the shielded conductor, and the shield wiring includes filling the 3rd ditch
The Part I of groove and the Part II extended laterally in the semiconductor substrate surface, the Part II are used for weight cloth
Line.
Preferably, the step of splitting bar structure is formed in the first groove and the second groove includes：Described
Form insulating laminate on the side wall and bottom of first groove and the second groove, the insulating laminate include the first insulating layer and
Second insulating layer, first insulating layer surround second insulating layer；In the upper of the first groove and the second groove
Opening and the shielded conductor are formed respectively at portion and lower part；Described in being removed on the top of the first groove and the second groove
A part for first separation layer；Gate-dielectric is formed on the side wall on the first groove top；And form the grid
Conductor to fill the opening, wherein, between the grid conductor and the shielded conductor by the gate-dielectric each other every
From being isolated from each other between the grid conductor and the body area by the gate-dielectric, the shielded conductor is partly led with described
It is isolated from each other between body substrate by the insulating laminate.
Preferably, the step of shield wiring is formed in the 3rd groove includes：The 3rd groove side wall and
Insulating laminate is formed on bottom, the insulating laminate includes the first insulating layer and the second insulating layer, and first insulating layer surrounds
Second insulating layer；The shield wiring is formed to fill the 3rd groove, wherein, the shield wiring is partly led with described
It is isolated from each other between body substrate by the insulating laminate.
Preferably, the shielding is formed at the same time in the first groove, the second groove and the 3rd groove to lead
Body and the shield wiring.
Preferably, the step of forming the grid conductor includes：Form conductor layer, the Part I filling of the conductor layer
The opening, Part II extend laterally above the semiconductor substrate surface；And the etching conductor layer is to remove
The Part II of conductor layer is stated, the Part I that the conductor layer is stayed in the first groove and the second groove forms institute
State grid conductor.
Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area,
The bucking electrode is located in the 3rd region, the first area, the second area and the 3rd region each other every
Open.
Preferably, first insulating layer is made of silica, and second insulating layer is by selected from silicon nitride, nitrogen oxides
Or at least one of polysilicon composition, the separation layer are made of silica.
Preferably, the thickness of first insulating layer is in the range of 500 to 50000 angstroms, the thickness of second insulating layer
Degree is in the range of 50 to 5000 angstroms, and the thickness of the separation layer is in the range of 0.5 to 5 micron.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple
The bottom width of groove.
Preferably, the step of forming the shielded conductor, form the step of shield wiring and form the grid and lead
The step of body, includes depositing at least once respectively.
According to the second aspect of the invention, there is provided a kind of power semiconductor, including：It is more in Semiconductor substrate
A groove, the Semiconductor substrate are the first doping type, and the multiple groove is included respectively positioned at the Semiconductor substrate
First to the 3rd groove in first area to the 3rd region；Splitting bar knot in the first groove and the second groove
Structure, the splitting bar structure include shielded conductor, grid conductor and are clipped in the second insulating layer therebetween；At least a portion position
Shield wiring in the 3rd groove；Positioned at the Semiconductor substrate Zhong Ti areas, the body area is adjacent to first ditch
Groove top, and be the second doping type, second doping type is opposite with first doping type；In the body area
Source region, the source region is first doping type；And divide with the source region, the grid conductor and the shield wiring
Source electrode, gate electrode and the bucking electrode not being electrically connected, wherein, the shield wiring is electrically connected with the shielded conductor,
And the shield wiring includes filling the Part I of the 3rd groove and laterally prolongs in the semiconductor substrate surface
The Part II stretched, the Part II are used to reroute.
Preferably, the splitting bar structure in the first groove and the second groove includes：Positioned at described first
Groove and the second groove lower sides and the insulating laminate of bottom, the insulating laminate are exhausted including the first insulating layer and second
Edge layer, first insulating layer surround second insulating layer；Screen positioned at the first groove and the second groove lower part
Cover conductor；And the grid conductor positioned at the first groove and the first groove top, wherein, the grid conductor and institute
State and be isolated from each other by the gate-dielectric between shielded conductor, by grid electricity between the grid conductor and the body area
Medium is isolated from each other, and is isolated from each other between the shielded conductor and the Semiconductor substrate by the insulating laminate.
Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area,
The bucking electrode is located in the 3rd region, the first area, the second area and the 3rd region each other every
Open.
Preferably, first insulating layer is made of silica, and second insulating layer is by selected from silicon nitride, nitrogen oxides
Or at least one of polysilicon composition.
Preferably, the thickness of first insulating layer is in the range of 500 to 50000 angstroms, the thickness of second insulating layer
Degree is in the range of 50 to 5000 angstroms.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple
The bottom width of groove.
Preferably, the power semiconductor is selected from cmos device, BCD devices, mosfet transistor, IGBT and Xiao
One kind in special based diode.
According to the method for the embodiment of the present invention, SGT structures are formed in power semiconductor, wherein, shielding
Insulating laminate is formed between conductor and Semiconductor substrate, so as to reduce gate leakage capacitance Cgd.The SGT structures include with the source region,
Source electrode, gate electrode and the bucking electrode that the grid conductor and the shield wiring are electrically connected, the shielding cloth
Line is electrically connected with the shielded conductor.The shield wiring of independent extraction electrode on shielded conductor for example for individually applying biasing
Voltage, so as to improve charge balance effect.Using separation layer the splitting bar structure of different zones and shielded conductor are existed
Formed in public step, so as to reduce manufacture cost.This method realizes SGT structures by better simply processing step, solves
Complex process in common process, easily occur the short circuit of grid source, the problems such as gate leakage capacitance Cgd is abnormal so as to meet the parameter of product and
While reliability requirement, wiring method is accomplished into most efficient, low cost with reference to concrete technology step.Compared with prior art,
Based on 0.25~0.35um techniques, the photoresist mask used in currently manufactured technique can be reduced 3~4 by this method
Photoresist mask.
A kind of separate gate power semiconductor device structure for reduction source drain capacitance that the embodiment of the present invention uses and its formation
Method, can also apply in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
The section of the manufacture method key step of power semiconductor according to prior art is shown respectively in Fig. 1 a and 1b
Figure.
Fig. 2 shows the flow chart of the manufacture method of power semiconductor according to embodiments of the present invention.
Fig. 3 a to 3i show method, semi-conductor device manufacturing method different phase according to embodiments of the present invention.
Embodiment
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown some
Known part.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.
It should be appreciated that in the structure of outlines device, it is known as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.
Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art
Material is formed.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC, and IV races semiconductor, such as
Si、Ge。
Fig. 2 shows the flow chart of the manufacture method of SGT power semiconductors according to embodiments of the present invention, Fig. 3 a to 3i
The sectional view in different step is shown respectively.Manufacturer according to embodiments of the present invention is described below in conjunction with Fig. 2 and 3a to 3i
The step of method.
This method starts from Semiconductor substrate 101.Semiconductor substrate is, for example, to be doping to the silicon substrate of N-type, the silicon substrate
Longitudinal uniform doping, resistivity is for example between the scope of 1~15 Ω cm.Semiconductor substrate has opposite first surface
And second surface.Preferably, in the first surface of Semiconductor substrate, the works such as photoetching, etching, ion implanting, impurity activation are passed through
Skill forms the partial pressure ring structure of power semiconductor, and the partial pressure ring structure belongs to the known knot of one kind of this area device architecture
Structure part, this will not be detailed here.Preferably, the Semiconductor substrate 101 used in the present embodiment could be formed with MOS field-effects crystalline substance
The semiconductor devices such as body pipe, IGBT isolated-gate field effect transistor (IGFET)s, Schottky diode.
In step S101, in the first area 201 of Semiconductor substrate 101,202 and the 3rd region 203 of second area
Groove 102 is formed respectively, as shown in Figure 3a.
Technique for forming groove 102 includes forming Etching mask by photoetching and etching, via Etching mask
Opening etching remove Semiconductor substrate 101 expose portion.
In this embodiment, first area 201 refers to that the wiring area of source region in SGT structures, second area 202 refer to
It is the wiring area of grid conductor in SGT structures, second area 203 refers to the wiring area of shielded conductor in SGT structures.
Groove 102 is extended downwardly from the surface of Semiconductor substrate 101, and is reached in the Semiconductor substrate 101 and made a reservation for
Depth.In this embodiment, the width of groove 102 is, for example, 0.2 to 10 micron, and depth is, for example, 0.1 to 50 micron.SGT
The width of the groove of structure is wider much than the groove of the convention trench power semiconductor of identical conducting level of efficiency, and its
The depth of groove is also deeply more many than the groove of convention trench power semiconductor.
Preferably, the sidewall slope of groove 102, for example, relative to vertical trench 102 top into 85 to 89 degree angles,
So that the bottom width of groove 102 is less than top width.The angle of groove is more oblique, beneficial to follow-up each dielectric layer, conductive material
The problems such as the defects of filling, reduction blind causes.
In step s 102, insulating laminate is sequentially formed on the surface of Semiconductor substrate 101, which is included altogether
The first insulating layer 122 and the second insulating layer 123 of shape, as shown in Figure 3b.
In groove 102, the first insulating layer 122 surrounds the second insulating layer 123.First insulating layer 122 and the second insulating layer
123 are made of different insulating materials.In this embodiment, the first insulating layer 122 is for example made of silica.Second insulating layer
123 selected from least one of silicon nitride, nitrogen oxides or polysilicon for example by forming.Preferably, the second insulating layer 123 is by nitrogen
SiClx forms.The thickness of first insulating layer 122 is, for example, 500 to 50000 angstroms, the thickness of the second insulating layer 123 be, for example, 50 to
5000 angstroms.The thickness of first insulating layer 122 is bigger, then gate leakage capacitance Cgd is smaller.
Technique for forming the first insulating layer 122 is included by thermal oxide, chemical vapor deposition (CVD) or high density etc.
Ion body chemical vapor phase growing, oxide layer is formed in the inner wall of groove 102.The side of the oxide layer conformally covering groove 102
Wall and bottom, so as to still retain a part of inner space of groove 102.
Technique for forming the second insulating layer 123 includes passing through chemical vapor deposition (CVD) or high-density plasma
Chemical vapor deposition, nitride layer is formed on 122 surface of the first insulating layer.The nitride layer conformally covers the first insulating layer
122 surface, so as to still retain a part of inner space of groove 102.
In step s 103, formed out respectively in 102 upper and lower part of groove of first area 201 and second area 202
Mouth 124 and shielded conductor 104, form shield wiring 131, as shown in Figure 3c in the groove 102 in the 3rd region 203.
In this embodiment, shielded conductor 104 and shield wiring 131 are formed using same conductor layer, for example, respectively by
Non-crystalline silicon or the polysilicon composition of doping.For forming technique process deposits polycrystalline such as including using sputtering of conductor layer
Silicon so that polysilicon fills the remainder of groove 102.Then, in first area 201 and second area 202, etched conductors
Layer and the second insulating layer 123 are to remove the part positioned at the outside of groove 102 and top, so as to be formed on the top of groove 102
Opening.
Preferably, it is made of for forming the conductor layer of shielded conductor 104 and shield wiring 131 polysilicon.The polysilicon
Deposition velocity be, for example, 1 to 100 angstrom per minute, depositing temperature is, for example, 510 to 650 degrees Celsius, thickness be, for example, 1000 to
100000 angstroms.By controlling the doping concentration of conductor layer, its resistance can be adjusted.In this embodiment, the square electricity of conductor layer
It is, for example, less than 20 ohm to hinder Rs.Further, the square resistance Rs of conductor layer is smaller, is formed during subsequent oxidation layer
Oxidated layer thickness is bigger compared with silicon.Further, the material selection amorphous of conductor layer, it is easier to form lower square resistance
Rs。
In above-mentioned deposition step, one or many depositions can be used to form conductor layer material.In Multiple depositions,
The speed of subsequent deposition process is less than previous deposition step, so that sedimentation rate is gradually reduced.In trench fill process, deposition
The slower filling effect of speed is better, the difficult filling of channel bottom packing ratio the top of the groove, therefore in multiple filling, it is previously deposited
Speed needs the speed of small primary depositing any later.
In the etching step, Etching mask is formed by photoetching and etching, with the first of exposing semiconductor substrate 101
Region 201 and second area 202, and block the 3rd region 203 of Semiconductor substrate 101., can in above-mentioned etching step
With using wet etching.Due to the selectivity of etchant, conductor layer and the second insulating layer are removed relative to the first insulating layer 122
123 expose portion.The etching not only removes conductor layer and the second insulating layer 123 is located at part outside groove 102, but also
Etch-back conductor layer and the second insulating layer 123 are located at the part inside groove 102.After the etching, the conductor layer is in the firstth area
The part retained in the groove 102 of domain 201 and second area 202 forms shielded conductor 104.In the 3rd region 203, shielding cloth
Line 131 is included in the Part I in the groove 102 in the 3rd region 203 and is extended laterally on the surface of Semiconductor substrate 101
Part II.Preferably, which includes etching twice, using different etchants, in first time etches, relatively
The expose portion of conductor layer is removed in the second insulating layer 123, in second etches, the is removed relative to the first insulating layer 122
The expose portion of two insulating layers 123.After the etch back, the opening 124 of desired depth is formed in groove 102, for example, the depth
Spend to extend downwardly 0.2 to 4 micron from the surface of Semiconductor substrate 101.The opening 124 exposes the upper side of groove 102 again
Wall.
In step S104, the first insulating layer 122 of etching removal in the groove of first area 201 and second area 202
A part, as shown in Figure 3d.
In the etching step, Etching mask is formed by photoetching and etching, with the first of exposing semiconductor substrate 101
Region 201 and second area 202, and block the 3rd region 203 of Semiconductor substrate 101.The etch process is, for example, wet method
Etching.Due to the selectivity of etchant, relative to the expose portion of the first insulating layer 122 of removal of Semiconductor substrate 101.Opening
124 depth extended downwardly from the surface of Semiconductor substrate 101 are, for example, 0.5 to 5 micron.The etching removes the first insulating layer
122 are located at the part on 102 top of groove.After the etching, the first insulating layer 122 is located at lower sides and the bottom of groove 102
A part reservation so that still by insulating between the lower part and Semiconductor substrate 101 of shielded conductor 104 and shield wiring 131
Lamination is isolated from each other.
In step S105, gate-dielectric 105 is formed in the upper portion side wall of groove 102 and the top of shielded conductor 104,
As shown in Figure 3 e.
Technique for forming gate-dielectric 105 can use thermal oxide.The temperature of the thermal oxide be, for example, 950 to
1200 degrees Celsius.The exposure silicon materials of Semiconductor substrate 101 and shielded conductor 104 form silica in thermal oxidation process.
In step of thermal oxidation, the surface of Semiconductor substrate 101 is also exposed in atmosphere.Gate-dielectric 105 is not placed only in groove 102
Upper portion side wall on, and be covered on the surface of Semiconductor substrate 101.
Compared with fine and close Semiconductor substrate 101, shielded conductor 104 is the amorphous or polycrystalline material of heavy doping, its structure
More loose, doping concentration is higher.As a result, gate-dielectric 105 is located at the thickness ratio of the Part II on 104 surface of shielded conductor
The thickness of Part I on 101 surface of Semiconductor substrate and in groove 102 is big.The Part I of gate-dielectric 105
Thickness be, for example, 50 to 5000 angstroms, the thickness of Part II is, for example, 60 to 10000 angstroms.
In step s 106, grid conductor 106, Yi Ji is formed in the groove of first area 201 and second area 202
Body area 107 and source region 108 are formed in the region adjacent with groove 102 of Semiconductor substrate 101, as illustrated in figure 3f.
The grid conductor 106 is for example made of the non-crystalline silicon or polysilicon that adulterate.For the technique for forming grid conductor 106
Such as including using process deposits polysilicons such as sputterings so that the opening at 104 top of polysilicon filling shielded conductor.
The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius,
Thickness is, for example, 1000 to 100000 angstroms.By the doping concentration of control gate conductor 106, its resistance can be adjusted.In the reality
Apply in example, the square resistance Rs of grid conductor 106 is, for example, less than 20 ohm.Further, the square resistance Rs of grid conductor 106
Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, grid conductor 106
Material selection amorphous, it is easier to form lower square resistance Rs.
In above-mentioned deposition step, one or many materials for depositing and forming grid conductor 106 can be used.Multiple
During deposition, the speed of subsequent deposition process is less than previous deposition step, so that sedimentation rate is gradually reduced.In trench fill process
In, the slower filling effect of sedimentation rate is better, the difficult filling of channel bottom packing ratio the top of the groove, therefore in multiple filling, it is preceding
The speed of face deposition needs the speed of small primary depositing any later.
The polysilicon includes the Part I in the groove of first area 201 and second area 202, and is partly leading
The Part II extended laterally on the surface of body substrate 101.
Then, in first area 201 and second area 202, etching removes polysilicon and is located at 101 surface of Semiconductor substrate
The Part II that top extends laterally so that polysilicon is only filled in the first area of Semiconductor substrate 101 and second area
The opening 124 on 102 top of groove, so as to form grid conductor 106.In the 3rd region 203, positioned at 131 surface of shield wiring
On polysilicon can remove completely.Further, the Part II of shield wiring 131 may also be etched partly and thickness
Reduce.However, the Part II of shield wiring 131 will be used to reroute, therefore, can be by controlling etching period to retain shielding
The Part II of wiring 131.
Then, PXing Ti areas 107 are formed in Semiconductor substrate 101, and the source region of N-type is formed in body area 107.
Technique for forming body area 107 and source region 108 is, for example, multiple ion implanting.By selecting suitable dopant to form difference
The doped region of type, then carries out thermal annealing with activator impurity.In ion implanting, using grid conductor 106 and shield wiring
131 are used as hard mask, body area 107 and the lateral position of source region 108 can be limited, so as to save photoresist mask.
The angle of the ion implanting is, for example, zero degree, i.e., relative to the surface vertical injection of Semiconductor substrate 101.By controlling ion
The energy of injection, can limit the injection depth of body area 107 and source region 108, so as to limit upright position.
When forming body area 107, for B11 or BF2 or first note B11 notes BF2 again for the dopant that uses, injects energy
It is 1E14~1E16 to measure as 20~100Kev, implantation dosage, and thermal annealing temperatures are 500 to 1000 degrees Celsius.Forming source region 108
When, for the dopant used for P+ or AS+, Implantation Energy is 60~150Kev, and implantation dosage is 1E14~1E16, thermal annealing temperatures
For 800 to 1100 degrees Celsius.
In this step, the formation SGT structures in the groove 102 of first area 201 and second area 202, including positioned at
Shielded conductor 104 and grid conductor 106 in groove.Grid conductor 106 includes the Part I being located in groove 102, and
The Part II extended above Semiconductor substrate 101.The Part I of grid conductor 106 is formed in 104 both sides of shielded conductor
Opening 124 in so that shielded conductor 104 is clipped in the middle.By the second insulating layer between shielded conductor 104 and grid conductor 106
123 are isolated from each other.The lower part of shielded conductor 104 extends to the lower part of groove 102, folded by insulating between Semiconductor substrate 101
Layer is being isolated each other, which includes the first insulating layer 122 and the second insulating layer 123.Grid conductor 106 and body area 107
It is adjacent with source region 108, and be isolated from each other by gate-dielectric 105.
In step s 107, the dielectric layer 109 between the surface deposits of semiconductor structure, as shown in figure 3g.
Interlayer dielectric layer 109 covers the first area of Semiconductor substrate 101 and second area interlayer dielectric layer 109 can be by
Formed selected from least one of silica, silicon nitride, silicon oxynitride, and can be individual layer or laminated construction.In the reality
Apply in example, interlayer dielectric layer 109 for example can be the boron-phosphorosilicate glass (BPSG) that thickness is 2000 to 15000 angstroms.
In step S108, formed in interlayer dielectric layer 109 and reach source region 108, grid conductor 106 and shield wiring
131 multiple contact holes 125, and contact zone 110 is formed by ion implanting respectively in the bottom of multiple contact holes 125, such as
Shown in Fig. 3 h.
Technique for forming contact hole 125 is, for example, dry etching.The sidewall slope of contact hole 125, such as relative to
Angle of the top of vertical trench 102 into 85 to 89.9 degree so that the bottom width of contact hole 125 is less than top width.Contact
The angle in hole 125 is more oblique, beneficial to the filling of subsequent conductive material, the problems such as reducing the defects of blind causes.
In the first area 201 of Semiconductor substrate 101, first group of contact hole in multiple contact holes 125 sequentially passes through
Interlayer dielectric layer 109 and gate-dielectric 105, extend to the desired depth in shield wiring 131, and second group of contact hole is worn successively
Cross the desired depth in interlayer dielectric layer 109, gate-dielectric 105, the arrival body of source region 108 area 107.The desired depth is, for example,
0.1 to 1 micron.
In the second area 202 of Semiconductor substrate 101, second group of contact hole in multiple contact holes 125 sequentially passes through
Interlayer dielectric layer 109, extends to the desired depth in grid conductor 106.
In the 3rd region 203 of Semiconductor substrate 101, the 3rd group of contact hole in multiple contact holes 125 passes through interlayer
Dielectric layer 109, extends to the desired depth in shield wiring 131.
In ion implanting, using interlayer dielectric layer as hard mask, the lateral position of contact zone 110 is limited, so as to
To save photoresist mask.For B11 or BF2 or first note B11 notes BF2 to the dopant that the ion implanting uses again,
Implantation Energy is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.In ion
After injection, thermal annealing can be carried out to activate dopant.
In step S109, source electrode 111, gate electrode 112 and bucking electrode 113 are formed, as shown in figure 3i.
The step is for example including deposited metal layer and patterning.The metal layer for example by selected from Ti, TiN, TiSi, W,
One kind or its alloy composition in AL, AlSi, AlSiCu, Cu, Ni.By etching by metal layer pattern be melted into source electrode 111,
Gate electrode 112 and bucking electrode 113.As shown in the figure, source electrode 111, gate electrode 112 and bucking electrode 113 each other every
From.
In the first area 201 of Semiconductor substrate 101, source electrode 111 is via in the multiple contact hole 125
One group of contact hole reaches source region 108.
In the second area 202 of Semiconductor substrate 101, gate electrode 112 is via in the multiple contact hole 125
Two groups of contact holes reach grid conductor 106.
In the 3rd region 203 of Semiconductor substrate 101, bucking electrode 113 is via in the multiple contact hole 125
Three groups of contact holes reach shield wiring 131.
After step S109, the metallization of power semiconductor is had been carried out.Further, according to the needs of product,
Passivation layer protection can be increased, complete the processing of power semiconductor Facad structure.By being thinned, carrying on the back a systems such as gold, scribing
Row postchannel process completes the final realization of device.
It should be noted that although in above-mentioned sectional view, shielded conductor 104 and shield wiring 131 in different grooves that
This isolation, grid conductor 106 are isolated from each other, however, in actual power semiconductor, it is above-mentioned from planar structure
Shielded conductor 104 and shield wiring 131 in different grooves can be connected to each other, and grid conductor 106 can also be connected to each other.
In a kind of embodiment, which is, for example, that the grid conductor 106 in different grooves 102 is integrally formed by single conductive layer,
And shielded conductor 104 in different grooves 102 and shield wiring 131 are integrally formed by single conductive layer.In the implementation of replacement
In example, which is, for example, to utilize public bucking electrode 113 by the shielded conductor 104 in different grooves 102 and shielding
Wiring 131 is connected to each other, and is connected the grid conductor 106 in different grooves 102 each other using public gate electrode 112
Connect.
In this embodiment, shield wiring 131 not only includes the Part I of filling groove 102, but also including from groove
102 Part II extended laterally on 101 surface of Semiconductor substrate.The Part II is as wiring layer.This mainly considers work(
The groove width of rate semiconductor devices is limited.Shielded conductor 104 in the trench is formed after contact hole, Semiconductor substrate 101
First area 201 and second area 102 in contact hole it is intensive.Led to improve source region 108, shielded conductor 104 and grid
Electric isolution between body 106, using the Part II of shield wiring 131 as wiring layer so that the multiple contact hole 125
In, for source region 108, shield wiring 104 and grid conductor 106 contact hole can away from each other, so as to reduce technology difficulty,
The reliability of power semiconductor is provided.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed, or further include as this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Also there are other identical element in process, method, article or equipment including key element.
For example above according to the embodiment of the present invention, these embodiments do not have all details of detailed descriptionthe, do not limit yet
The specific embodiment that the invention is only.Obviously, as described above, can make many modifications and variations.This specification is chosen simultaneously
These embodiments are specifically described, are in order to preferably explain the principle of the present invention and practical application, so that technical field
Technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention only by claims and
The limitation of its four corner and equivalent.
Claims (19)
1. a kind of manufacture method of power semiconductor, including：
Multiple grooves are formed in the Semiconductor substrate of the first doping type, the multiple groove includes partly leading positioned at described respectively
First to the 3rd groove in the first area of body substrate to the 3rd region；
In the first groove and the second groove formed splitting bar structure, the splitting bar structure include shielded conductor,
Grid conductor and it is clipped in the second insulating layer therebetween；
At least a portion of shield wiring is formed in the 3rd groove；
Form the body area of the second doping type in the region of the Semiconductor substrate adjacent trench, second doping type with
First doping type is opposite；
The source region of first doping type is formed in the body area；And
Source electrode, gate electrode and the bucking electrode being electrically connected respectively with the source region, source conductor and shield wiring are formed,
Wherein, the shield wiring is electrically connected with the shielded conductor, and the shield wiring includes filling the 3rd ditch
The Part I of groove and the Part II extended laterally in the semiconductor substrate surface, the Part II are used for weight cloth
Line.
2. according to the method described in claim 1, wherein, splitting bar knot is formed in the first groove and the second groove
The step of structure, includes：
Form insulating laminate on the side wall and bottom of the first groove and the second groove, the insulating laminate includes the
One insulating layer and the second insulating layer, first insulating layer surround second insulating layer；
Opening and the shielded conductor are formed respectively in the upper and lower part of the first groove and the second groove；
A part for first separation layer is removed on the top of the first groove and the second groove；
Gate-dielectric is formed on the side wall on the first groove top；And
The grid conductor is formed to fill the opening,
Wherein, it is isolated from each other between the grid conductor and the shielded conductor by the gate-dielectric, the grid conductor
It is isolated from each other between the body area by the gate-dielectric, by described between the shielded conductor and the Semiconductor substrate
Insulating laminate is isolated from each other.
3. according to the method described in claim 2, wherein, include in the 3rd groove the step of formation shield wiring：
Insulating laminate is formed on the side wall of the 3rd groove and bottom, the insulating laminate includes the first insulating layer and second
Insulating layer, first insulating layer surround second insulating layer；
The shield wiring is formed to fill the 3rd groove,
Wherein, it is isolated from each other between the shield wiring and the Semiconductor substrate by the insulating laminate.
4. according to the method described in claim 3, wherein, in the first groove, the second groove and the 3rd groove
In at the same time form the shielded conductor and the shield wiring.
5. according to the method described in claim 4, wherein, the step of forming the grid conductor, includes：
Conductor layer is formed, the Part I of the conductor layer fills the opening, and Part II is in the semiconductor substrate surface
Top extends laterally；And
The conductor layer is etched to remove the Part II of the conductor layer, the conductor layer stays in the first groove and described
Part I in second groove forms the grid conductor.
6. according to the method described in claim 5, wherein, the source electrode is located in the first area, the grid is electric
Pole is located in the second area, and the bucking electrode is located in the 3rd region, the first area, the second area
It is spaced apart with the 3rd region.
7. according to the method described in claim 1, wherein, first insulating layer is made of silica, second insulating layer
By being formed selected from least one of silicon nitride, nitrogen oxides or polysilicon, the separation layer is made of silica.
8. according to the method described in claim 1, wherein, the scope of the thickness of first insulating layer at 500 to 50000 angstroms
Interior, the thickness of second insulating layer is in the range of 50 to 5000 angstroms, the model of the thickness of the separation layer at 0.5 to 5 micron
In enclosing.
9. according to the method described in claim 1, wherein, first doping type is one kind in N-type and p-type, described the
Two doping types are the another kind in N-type and p-type.
10. according to the method described in claim 1, wherein, the sidewall slope of the multiple groove so that the multiple groove
Top width is more than the bottom width of the multiple groove.
11. according to the method described in claim 1, wherein, the step of forming the shielded conductor, form the shield wiring
The step of step and the formation grid conductor, includes depositing at least once respectively.
12. a kind of power semiconductor, including：
Multiple grooves in Semiconductor substrate, the Semiconductor substrate are the first doping type, and the multiple groove includes
Respectively positioned at first to the 3rd groove in first area to the 3rd region of the Semiconductor substrate；
Splitting bar structure in the first groove and the second groove, the splitting bar structure include shielded conductor,
Grid conductor and it is clipped in the second insulating layer therebetween；
At least a portion is located at the shield wiring in the 3rd groove；
Positioned at the Semiconductor substrate Zhong Ti areas, the body area is the second doping type adjacent to the first groove top,
Second doping type is opposite with first doping type；
Source region in the body area, the source region are first doping type；And
Source electrode, gate electrode and the shielding being electrically connected with the source region, the grid conductor and the shield wiring
Electrode,
Wherein, the shield wiring is electrically connected with the shielded conductor, and the shield wiring includes filling the 3rd ditch
The Part I of groove and the Part II extended laterally in the semiconductor substrate surface, the Part II are used for weight cloth
Line.
13. power semiconductor according to claim 12, wherein, in the first groove and the second groove
The splitting bar structure includes：
Positioned at the first groove and the second groove lower sides and the insulating laminate of bottom, the insulating laminate includes the
One insulating layer and the second insulating layer, first insulating layer surround second insulating layer；
Shielded conductor positioned at the first groove and the second groove lower part；And
Grid conductor positioned at the first groove and the first groove top,
Wherein, it is isolated from each other between the grid conductor and the shielded conductor by the gate-dielectric, the grid conductor
It is isolated from each other between the body area by the gate-dielectric, by described between the shielded conductor and the Semiconductor substrate
Insulating laminate is isolated from each other.
14. power semiconductor according to claim 13, wherein, the source electrode is located at the first area
In, the gate electrode is located in the second area, and the bucking electrode is located in the 3rd region, firstth area
Domain, the second area and the 3rd region are spaced apart.
15. power semiconductor according to claim 13, wherein, first insulating layer is made of silica, institute
The second insulating layer is stated by being formed selected from least one of silicon nitride, nitrogen oxides or polysilicon.
16. power semiconductor according to claim 13, wherein, the thickness of first insulating layer 500 to
In the range of 50000 angstroms, the thickness of second insulating layer is in the range of 50 to 5000 angstroms.
17. power semiconductor according to claim 13, wherein, first doping type is in N-type and p-type
One kind, second doping type are the another kind in N-type and p-type.
18. power semiconductor according to claim 13, wherein, the sidewall slope of the multiple groove so that institute
The top width for stating multiple grooves is more than the bottom width of the multiple groove.
19. power semiconductor according to claim 13, wherein, the power semiconductor is selected from CMOS devices
One kind in part, BCD devices, mosfet transistor, IGBT and Schottky diode.
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