TW201941428A - Integrated chip and method of forming the same - Google Patents

Abstract

The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.

Description

Integrated wafer and forming method thereof

Modern integrated circuit chips include millions or billions of semiconductor elements formed on a semiconductor substrate (eg, silicon). Integrated chips (ICs) use many different types of transistor components depending on the application of the IC. In recent years, the market for cellular and radio frequency (RF) components has gradually expanded and the use of high-voltage transistor components has increased significantly. For example, high-voltage transistor components are commonly used in power amplifiers in RF transmit / receive chains due to their ability to handle high breakdown voltage (BV) (eg, greater than about 50 volts) and high frequencies.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are examples only and are not intended to be limiting. For example, in the following description, the formation of the first feature above or on the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. An embodiment is formed between the second features so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat the graphical element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not itself define the relationship between the various embodiments and / or configurations discussed.

In addition, for ease of description, spatially relative terms such as "below", "below", "below", "above", "above" And the like to describe the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientation depicted in the drawings, spatially relative terms are intended to cover different orientations of the elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

High-voltage piezoelectric crystal elements are usually constructed with a field plate. The field plate is a conductive element that is placed above the channel region to enhance the performance of the high-voltage transistor element by manipulating the electric field generated by the gate electrode (eg, reducing the peak electric field). By manipulating the electric field generated by the gate electrode, the high voltage transistor element can achieve a higher breakdown voltage. For example, a laterally diffused metal oxide semiconductor (LDMOS) transistor element typically includes a field plate that extends from a channel region to an adjacent drift region, where the adjacent The drift region is disposed between the channel region and the drain region.

Field plates can be formed in a number of different ways. For example, a field plate may be formed by extending a conductive gate material (for example, polycrystalline silicon) from a gate electrode toward a drift region. However, in such a configuration, the field plate is synchronized with the gate bias, which increases the burden on the gate-to-drain capacitance (Cgd) and increases the switching of the components loss. Alternatively, the conductive gate material may be patterned to form separate field plates. This type of configuration reduces the gate-drain capacitance (Cgd), but the position of the field plate is usually limited by design rules. In yet another alternative, non-gate materials may be used to form the field plates. However, such solutions use additional processing steps that will increase the manufacturing cost of the resulting integrated wafer.

Accordingly, the present disclosure relates to a high-voltage transistor element having a field plate made of a non-gate material, the field plate and a metal layer of a back-end-of-the-line (BEOL) For simultaneous formation to achieve low-cost manufacturing methods. In some embodiments, the high-voltage transistor element has a gate electrode disposed above the substrate between the source region and the drain region, and the source region and the drain region are located within the substrate. . The dielectric layer extends laterally from above the gate electrode to a drift region disposed between the gate electrode and the drain region. The field plate is located in a first inter-level dielectric (ILD) layer, and the first inter-level dielectric layer is overlying the substrate. The field plate extends laterally from above the gate electrode to above the drift region, and extends vertically from the dielectric layer to the top surface of the first ILD layer. A plurality of metal contacts having the same material as the field plate extend vertically from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

FIG. 1 illustrates a cross-sectional view of some embodiments of a disclosed high-voltage transistor element 100 having a field plate 122.

The high-voltage piezoelectric crystal element 100 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 have a second doping type having a higher doping concentration than the semiconductor substrate 102. In some embodiments, the first doping type may be an n-type doping, and the second doping type may be a p-type doping.

The gate structure 116 is disposed above the semiconductor substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 108 that is separated from the semiconductor substrate 102 by a gate dielectric layer 110. After receiving the bias voltage, the gate electrode 108 is used to generate an electric field, which controls the movement of the charge carriers in the channel region 112, which is disposed laterally between the source region 104 and the drain region 106. between. For example, during operation, a gate-source voltage (VGS) may be selectively applied to the gate electrode 108 relative to the source region 104 to form a conductive channel in the channel region 112. When a gate-source voltage is applied to form a conductive channel, a drain-source voltage (VDS) is applied to move the charge carriers between the source region 104 and the drain region 106 (for example, as shown by arrow 105) ).

The channel region 112 extends laterally from the source region 104 to an adjacent drift region 114 (ie, a drain extension region). The drift region 114 includes a second doping type with a relatively low doping concentration, which provides higher impedance at high operating voltages. The gate structure 116 is disposed above the channel region 112. In some embodiments, the gate structure 116 may extend from above the channel region 112 to a position overlying a portion of the drift region 114.

A first interlayer dielectric (ILD) layer 118 is disposed over the semiconductor substrate 102. One or more conductive metal structures are disposed within the first ILD layer 118. In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 for providing the source region 104, the drain region 106 or the gate electrode 108 and disposed within the second ILD layer 126. The first ILD layer 126 is vertically connected between the metal line layers 128 of the first back-end process (BEOL), and the second ILD layer 126 is overlaid on the first ILD layer 118.

The one or more conductive metal structures may further include a field plate 122 which is disposed in the first ILD layer 118 at a position overlying a portion of the gate electrode 108 and the drift region 114. The field plate 122 includes the same conductive material as the plurality of contacts 120. The field plate 122 may be disposed above a dielectric layer 124 configured to separate the field plate 122 from the drift region 114 and the gate electrode 108. In some embodiments, the dielectric layer 124 extends laterally beyond the field plate 122 in one or more directions.

During operation, the field plate 122 is configured to act on an electric field generated by the gate electrode 108. The field plate 122 can be used to change the distribution of the electric field generated by the gate electrode 108 in the drift region 114, which enhances the internal electric field of the drift region 114 and increases the drift doping concentration of the drift region 114, thereby enhancing the high-voltage transistor element. 100 breakdown voltage capability.

FIG. 2 illustrates a cross-sectional view of some other embodiments of a disclosed high-voltage transistor device including a high-voltage lateral diffusion MOSFET (LDMOS) device 200 having a field plate 214.

The LDMOS device 200 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 include a highly doped region having a second doping type different from the first doping type. In some embodiments, the first doping type may be p-type, and the second doping type may be n-type. In some embodiments, the source region 104 and the drain region 106 may have a doping concentration in a range between about 1019 cm ^-3 and about 1020 cm ^-3 .

The contact region 208 (eg, “p-tap” or “n-tap”) having a first doping type (eg, p + doping) is laterally abutted于 源 极 区 104。 In the source region 104. The contact region 208 provides an ohmic connection with the semiconductor substrate 102. In some embodiments, the contact region 208 may have a p-type doping concentration in a range between about 1018 cm ^-3 and about 1020 cm ^-3 . The contact region 208 and the source region 104 are disposed in a body region 202. The body region 202 has a first doping type having a doping concentration higher than that of the semiconductor substrate 102. For example, the semiconductor substrate 102 may have a doping concentration of between about 1014 cm ^-3 and in a range between about 1016 ^cm-3, and the body region 202 may have between about 1016 cm ^-3 and about 1018 cm ^- Doping concentration in the range between ³ .

The drain region 106 is disposed in a drift region 204 that is disposed in the semiconductor substrate 102 at a position laterally adjacent to the body region 202. The drift region 204 includes a second doping type with a relatively low doping concentration, which provides a higher impedance when the LDMOS element 200 is operated at a high voltage. In some embodiments, the drift region 204 may have a doping concentration in a range between about 1015 cm ^-3 and about 1017 cm ^-3 .

The gate structure 210 is disposed above the semiconductor substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. In some embodiments, the gate structure 210 may extend laterally from above the body region 202 to a position overlying a portion of the drift region 204. The gate structure 210 includes a gate electrode 108 that is separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may include silicon dioxide (SiO ₂ ) or a high dielectric constant (high-k) gate dielectric material, and the gate electrode 108 may include polycrystalline silicon ( polysilicon) or metal gate material (for example, aluminum). In some embodiments, the gate structure 210 may also include a sidewall spacer 212 disposed on an opposite side of the gate electrode 108. In various embodiments, the sidewall spacer 212 may include a nitride-based sidewall spacer (eg, including SiN) or an oxide-based sidewall spacer (eg, SiO ₂ , SiOC, etc.).

One or more dielectric layers 124 are disposed above the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 continuously extend from above a portion of the gate electrode 108 to above a portion of the drift region 204. In some embodiments, one or more dielectric layers 124 may be conformally disposed on the drift region 204, the gate electrode 108, and the sidewall spacer 212.

The field plate 214 is disposed above the one or more dielectric layers 124 and is laterally surrounded by the first ILD layer 118. The field plate 214 extends from above the gate electrode 108 to above the drift region 204. The size of the field plate 214 may vary according to the size and characteristics of the LDMOS device 200. In some embodiments, the field plate 214 may have a size between about 50 nanometers and about 1 micron. In other embodiments, the field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may include a dielectric material having a relatively low dielectric constant (eg, less than or equal to about 3.9), which provides electrical isolation between the plurality of contacts 120 and / or the field plate 122. . In some embodiments, the first ILD layer 118 may include an ultra-low-k dielectric material or a low-k dielectric material (eg, SiCO).

The field plate 214 extends vertically from the dielectric layer 124 to the top surface of the first ILD layer 118. In some embodiments, the field plate 214 may extend vertically to a height greater than or equal to the height of the top surface of the contact 120 and the first ILD layer 118. The field plate 122 has a non-planar surface adjacent one or more dielectric layers 124. The non-planar surface causes the field plate 122 to have a first thickness t ₁ in a region above the gate electrode 108 and a second thickness t ₂ greater than the first thickness t ₁ in a region overlying the drift region 204.

The plurality of contacts 120 are also surrounded by the first ILD layer 118. The plurality of contacts 120 may include a first contact 120 a coupled to the contact region 208, a second contact 120 b coupled to the drain region 106, and a third contact 120 c coupled to the gate electrode 108. In some embodiments, the first contact 120 a may include a butted contact (not shown), which contacts both the contact region 208 and the source region 104. In some embodiments, the plurality of contacts 120 and the field plate 122 may include the same metal material. For example, the plurality of contacts 120 and the field plate 122 may include tungsten (Tungsten; W), tantalum-nitride (TaN), titanium (Ti), titanium-nitride (TiN) , Aluminum copper (AlCu), copper (Cu) and / or other similar conductive materials.

FIG. 3 illustrates a cross-sectional view of some other embodiments of the disclosed high-voltage LDMOS device 300 having a field plate 214.

The LDMOS device 300 includes an isolation region 302 that is disposed in the drift region 204 at a position laterally disposed between the gate structure 210 and the drain region 106. The isolation region 302 improves the isolation between the gate structure 210 and the drain region 106 so as to prevent dielectric breakdown between the gate structure 210 and the drift region 204 when the LDMOS device 300 is operated at a large operating voltage. . For example, the isolation region 302 can be introduced into the drift region 204 of the LDMOS device (designed to operate at the first breakdown voltage) to increase the breakdown voltage of the LDMOS device 300 without greatly changing the manufacturing process of the LDMOS device. . In some embodiments, the isolation region 302 may include shallow trench isolation (STI). In other embodiments, the isolation region 302 may include a field oxide.

FIG. 4 illustrates a cross-sectional view of some other embodiments of the disclosed high-voltage LDMOS device 400 having a field plate 408.

The LDMOS device 400 includes a plurality of dielectric layers 402 to 404 disposed between the field plate 408 and the gate structure 210 and / or the drift region 204. The plurality of dielectric layers 402 to 404 are configured to electrically isolate the field plate 408 from the gate structure 210 and / or the drift region 204. In an embodiment, the plurality of dielectric layers 402 to 404 may include two or more than two different dielectric materials. In some embodiments, the plurality of dielectric layers 402 to 404 may include one or more dielectric layers used during a typical CMOS manufacturing process, thereby limiting the use of the field plate 408 and the gate structure 210 and / Or an additional manufacturing step for electrically isolating the drift region 204.

For example, the plurality of dielectric layers 402 to 404 may include a silicide blocking layer 402. In some embodiments, the silicide blocking layer 402 may include a resist-protection oxide (RPO) layer to prevent silicide formation. The silicide blocking layer 402 may be disposed above portions of the gate electrode 108 and the drift region 204. In some embodiments, the silicide blocking layer 402 may continuously extend from above the gate electrode 108 to above the drift region 204.

In some embodiments, the plurality of dielectric layers 402 to 404 may further include a field plate etch stop layer (ESL) 404. The field plate ESL 404 can be disposed above the silicide blocking layer 402 and used to control the etching of the openings of the field plate 408. The field plate ESL 404 may account for the difference in etch depth and / or the difference in etch rate between the contact 120 and the field plate 408 (eg, due to an etch loading effect). In some embodiments, for example, the field plate ESL 404 may include a silicon nitride (SiN) layer.

In some alternative embodiments (not shown), the plurality of dielectric layers 402 to 404 may additionally or alternatively include a gate dielectric layer. In such embodiments, the gate dielectric layer may be configured laterally adjacent to the gate structure 210 at a location overlying the drift region 204. In some embodiments, the dielectric layer oxide may include silicon dioxide (eg, SiO ₂ ) or a high dielectric constant gate dielectric material. In yet other embodiments, the plurality of dielectric layers 402 to 404 may additionally or alternatively include an ILD layer (eg, the first ILD layer 118).

A contact etch stop layer (CESL) 406 is disposed over the semiconductor substrate 102 and the field plate ESL 404. In some embodiments, the CESL 406 extends above the semiconductor substrate 102 at a location between the plurality of contacts 120 and the field plate 408 such that the CESL 406 is adjacent to the plurality of contacts 120 and the plurality of sidewalls of the field plate 408. The CESL 406 overlies the gate structure 210. In some embodiments, CESL 406 may also be overlying multiple dielectric layers 402 to 404. In other embodiments, one or more of the plurality of dielectric layers 402 to 404 (eg, field plate ESL 404) may be overlaid on CESL 406. In some embodiments, CESL 406 may include a nitride layer. For example, CESL 406 may include silicon nitride (SiN).

The field plate 408 is disposed in the first ILD layer 118 and is adjacent to the CESL 406 and one or more of the plurality of dielectric layers 402 to 404. In some embodiments, the field plate 408 extends through the CESL 406 to abut one or more of the plurality of dielectric layers 402 to 404. In such embodiments, one or more of the plurality of dielectric layers 402 to 404 separate the field plate 408 from the gate structure 210 and the drift region 204.

In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The first metal material 410 may include a glue layer disposed along an outer edge of the field plate 408, and the second metal material 412 is embedded in the first metal material 410 (ie, the second The metal material 412 is separated from the CESL 406 by the first metal material 410). In some embodiments, the inner liner layer 414 may be disposed between the first ILD layer 118 and the first metal material 410.

In some embodiments, the first metal material 410 disposed along the outer edge of the field plate 408 has a top surface configured along a substantially flat surface 420 (ie, a flat surface formed by a planarization process). The flat surface 420 may be aligned with a top surface of the plurality of contacts 120. In some embodiments, the first metal material 410 includes the same material as the plurality of contacts 120, and the second metal material 412 includes the same material as the first metal wire layer 418 overlying the plurality of contacts 120. For example, in some embodiments, the first metal material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).

It should be understood that, because the disclosed field plate is integrated with a BEOL metallization layer, the disclosed field plate allows various field plate biasing configurations to easily implement different design considerations. For example, the field plate bias can be changed by changing the metal wiring layer instead of changing the design of the disclosed high voltage components. In addition, it should be understood that biasing high-voltage transistor components with the help of BEOL metal interconnect wiring allows multiple field plate bias configurations to be integrated on the same wafer using a single manufacturing process flow.

5 to 6 illustrate cross-sectional views of some embodiments of field plate bias configurations for high-voltage transistor elements achieved by BEOL metal interconnection wiring. Although FIGS. 5 to 6 illustrate the connection between the field plate 214 and the contact region 208 or the gate electrode 108 by means of a first metal line layer (for example, the first metal line layer 504 or the first metal line layer 604), The BEOL metal interconnection wiring is not limited to this. Specifically, it should be understood that the field plate 214 may be connected to the source region by any combination of BEOL metal interconnection layers (for example, a first metal line layer, a first metal via layer, a second metal line layer, etc.) , Gate electrode, drain region or bulk contact.

FIG. 5 illustrates a cross-sectional view of the high-voltage LDMOS device 500, in which the field plate 214 is electrically coupled to the contact region 208 along the conductive path 506. The field plate 214 is connected to the first metal line layer 504 disposed in the second ILD layer 502. The first metal line layer 504 is coupled to a contact 120 a adjacent to the contact region 208. By electrically coupling the field plate 214 to the contact region 208, the field plate 214 is biased by the source voltage. The field plate 214 is biased by the source voltage to provide low on-state resistance (Rds (on)) and low dynamic power dissipation (eg, low Rds (relative to BV ( on) * Qgd) high voltage LDMOS element 500. Low dynamic power dissipation provides good performance during high frequency switching applications.

FIG. 6 illustrates a cross-sectional view of the high-voltage LDMOS device 600, in which the field plate 214 is electrically coupled to the gate electrode 108 along a conductive path 606. The field plate 214 is connected to the first metal line layer 604 disposed in the second ILD layer 602. The first metal line layer 604 is connected to a contact 120 b adjacent to the gate electrode 108. By electrically coupling the field plate 214 to the gate electrode 108, the field plate 214 is biased by the gate voltage. Biasing the field plate 214 by the gate voltage can provide a high-voltage LDMOS element 600 having a low Rds (on) relative to the breakdown voltage.

A variety of field plate bias configurations can allow the disclosed field plates to form multifunctional high-voltage transistor elements that can be used in different applications. For example, the on-state resistance Rds (on) of a high-voltage transistor element with a gate bias field plate is lower than that of a high-voltage transistor with a source bias field plate. Rds (on) of the crystal element. However, the Rds (on) * Qgd of a high-voltage transistor element having a source bias field plate is lower than the Rds (on) * Qgd of a high-voltage transistor element having a gate source field plate. Therefore, high-voltage transistor components with gate-biased field plates (eg, high-voltage LDMOS element 500) can be used for low-frequency switching applications (eg, below 10 MHz), while source-biased field plates (eg, high-voltage LDMOS) Element 600) can be used for high-frequency switching applications (eg, above 10 MHz).

7A-7C illustrate cross-sectional views of some embodiments of the high-voltage LDMOS device 700a to the high-voltage LDMOS device 700c in different switching isolation configurations.

As shown in FIG. 7A, the high-voltage LDMOS element 700 a is configured as a low-side switch (for example, a switch connected to a ground in an inverter). In such a configuration, the high-voltage LDMOS element 700a has a floating source region 104 so that the voltage on the source region 104 can be changed during a switching cycle.

As shown in FIG. 7B, the high-voltage LDMOS element 700 b is configured as a high-side switch (for example, a switch connected to VDD in an inverter). In such a configuration, the high-voltage LDMOS element 700b has a source region 104 connected to a source voltage. The high-voltage LDMOS element 700b has a drift region 702 that extends below the body region 202 and can prevent the charge carriers from traveling from the contact region 208 to the semiconductor substrate 102 (for example, by means of punch through) To prevent the source voltage from rising above the substrate voltage.

As shown in FIG. 7C, the high-voltage LDMOS element 700c is completely isolated from the substrate to allow independent biasing. The high-voltage piezoelectric crystal element 700c includes a deep well 704 and an oppositely doped underlying buried layer 706 configured to provide vertical isolation. In some embodiments, the deep well 704 may have a first doping type (eg, the same doping type as the body region 202), and the buried layer 706 may have a second doping type.

The high-voltage LDMOS device 700c further includes one or more additional STI regions 206 that laterally separate the drain region from the bulk region 708 and the buried layer 710 having a second doping type. The base region 708 is overlying the deep well 704 and the buried layer 710 is overlying the well region 712, which has a second doping type and is adjacent to the buried layer 706. The plurality of contacts 120 are used to provide a bias voltage for the base region 708 and the buried layer 710, thereby forming a deep well 704 and a junction isolation between the buried layer 706 and the well region 712. Junction isolation allows fully isolated high-voltage LDMOS elements 700c to operate in a range above the bias.

FIG. 8 illustrates a cross-sectional view of a source downward high-voltage transistor element 800 having a field plate 214.

The high-voltage piezoelectric crystal element 800 includes a substrate 802 having a first doping type (eg, a p + doping type) with a high doping concentration. The source region 804 is disposed along the back side 802b of the substrate 802. In various embodiments, the source region 804 may include a highly doped region or a metal layer. An epitaxial layer 806 having a first conductivity type is disposed over the front side surface 802f of the substrate 802. The dopant concentration of the epitaxial layer 806 is less than the dopant concentration of the substrate 802. The source contact region 810, the drain region 106, the body region 808, and the drift region 204 are disposed in the top surface of the epitaxial layer 806.

The conductive material 812 extends from the top surface of the epitaxial layer 806 to the substrate 802. The conductive material 812 may include a highly doped deep well region. The conductive material 812 allows source connection to the back side of the substrate 802, thereby reducing the complexity of metal wiring and achieving various package compatibility. In some embodiments, the field plate 214 can be biased by a source voltage by means of an electrical path 818 that extends through the contact 814 adjacent to the conductive material 812 and is coupled to the field plate 214 Covered metal wire layer 816.

9A-9B illustrate some embodiments of the disclosed high-voltage LDMOS device having a field plate 902 in a metal line layer. Although FIG. 9A to FIG. 9B illustrate the field plate as being located on the first metal line layer, it should be understood that the disclosed field plate is not limited to the first metal line layer, but may be implemented on an alternative layer of the BEOL metallization stack.

As shown in the cross-sectional view 900 of FIG. 9A, the field plate 902 is disposed in a first metal line layer overlying a second ILD layer 904 over a first ILD layer 118. In some embodiments, the field plate 902 has substantially flat top and bottom surfaces to provide a flat topology for the field plate 902. The field plate 902 is vertically separated from the gate structure 210 and the drift region 204 by the first ILD layer 118. A portion of the field plate 902 that covers the gate electrode 108 and the drift region 204 is laterally separated from the source region 104 and the drain region 106. For example, the field plate 902 may be laterally separated from the drain region 106 by a distance d . In some embodiments, the field plate 902 may extend laterally from above the gate electrode 108 to above the drift region 204.

As shown in a top view 906 of FIG. 9B, the field plate 902 includes a metal structure overlying a portion of the gate electrode 108 and the drift region 204. The metal structure is not connected to the underlying element or to another metal structure on the first metal line layer by means of the contact 120. Specifically, the metal structure will be connected to an overlying via (not shown) configured to connect the field plate to an overlying metal line layer that biases the field plate 902.

FIG. 10 illustrates some embodiments of the disclosed high-voltage LDMOS device 1000 having a self-aligned drift region 1002.

The self-aligned drift region 1002 has a sidewall 1002s that is substantially aligned with the sidewalls of the gate electrode 108 and the gate dielectric layer 110. In certain alternative embodiments, the self-aligned drift region 1002 may be formed to have a sidewall 1002s substantially aligned with an edge of the sidewall spacer 212. By aligning the self-aligned drift region 1002 with the sidewalls of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 is laterally separated from the body region 202 by a distance s , thereby enabling the gate-drain Minimize pole overlap and achieve low gate-drain charge (Qgd) and good high frequency performance. The field plate 214 overlying the self-aligned drift region 1002 can further reduce the gate-drain charge (Qgd).

FIG. 11 illustrates a flowchart of some embodiments of a method 1100 of forming a high-voltage transistor element having a field plate. The method can use a process step that has been used during a standard CMOS manufacturing process to form a field plate, and thus can provide a low cost, versatile field plate.

Although the disclosed methods (eg, method 1100 and method 3300) are illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events illustrated and / or described herein, some actions may occur in a different order and / or concurrently with other actions or events. In addition, not all illustrated actions may be required to implement one or more aspects or embodiments described herein. Furthermore, one or more of the actions described herein may be performed in one or more separate actions and / or stages.

At 1102, the substrate is provided with a source region and a drain region separated by a channel region. In some embodiments, the substrate may further include a drift region between the source region and the drain region at a position adjacent to the channel region.

At 1104, a gate structure is formed over the substrate at a location between the source and drain regions. The gate structure may include a gate dielectric layer and an overlying gate electrode.

At 1106, a drift region may be formed using a self-aligned process. In some embodiments, the self-aligned process selectively routes the semiconductor substrate according to the gate structure to form the drift region.

At 1108, one or more dielectric layers are selectively formed over the gate electrode and a portion of the drift region.

At 1110, a contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer are formed over the substrate.

At 1112, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings.

At 1114, a plurality of contact openings and field plate openings are filled with the first metal material.

At 1116, a planarization process may be performed to remove the excess first metal material overlying the first ILD layer.

At 1118, a second metal material corresponding to the first metal wire layer is deposited. In some embodiments, the second metal material may further fill the field plate opening. In such embodiments, the second metal material is embedded in the first metal material within the field plate opening.

At 1120, a second interlayer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line layer structure.

12 to 19 illustrate cross-sectional views of some embodiments of a method of forming a MOSFET element having a field plate. Although FIGS. 12 to 19 are described with reference to method 1100, it should be understood that the structures disclosed in FIGS. 12 to 19 are not limited to such methods, but may be used independently as structures independent of the methods.

FIG. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to action 1102.

As shown in the cross-sectional view 1200, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be intrinsically doped to have a first doping type. In various embodiments, the semiconductor substrate 102 may include any type of semiconductor body (eg, silicon, SOI) including, but not limited to, a semiconductor wafer or wafer or one or more dies on a wafer, and any other type And / or an epitaxial layer formed thereon and / or otherwise associated therewith.

Various implantation steps can be used to selectively pattern the semiconductor substrate 102 to form multiple implanted regions (eg, well regions, contact regions, etc.). For example, the semiconductor substrate 102 may be selectively laid out to form a body region 202, a drift region 204, a source region 104, a drain region 106, and a contact region 208. This can be achieved by selectively masking the semiconductor substrate 102 (eg, using a photoresist mask) and then applying a high energy dopant 1204 (eg, a p-type dopant species such as boron; or an n-type dopant such as phosphorus ) Is introduced into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions. For example, as shown in cross-sectional view 1200, the mask layer 1202 is selectively patterned to expose portions of the semiconductor substrate 102, and high energy dopants 1204 are then implanted into the portions to form source regions 104 and drain region 106.

It should be understood that the implanted area shown in cross-sectional view 1200 is one example of a possible implanted area, and the semiconductor substrate 102 may include other configurations of the implanted area, such as those illustrated in FIGS. 1-10 Either in the zone.

FIG. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to action 1104.

As shown in the cross-sectional view 1300, the gate structure 210 is formed over the semiconductor substrate 102 at a position between the source region 104 and the drain region 106. The gate structure 210 may be formed by forming a gate dielectric layer 110 over the semiconductor substrate 102 and by forming a gate electrode material 108 over the gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 and the gate electrode material 108 may be deposited by a vapor deposition technique. The gate dielectric layer 110 and the gate electrode material 108 may be subsequently patterned and etched (eg, according to a photoresist mask) to define the gate structure 210. In some embodiments, the gate electrode 108 may be formed by depositing a nitride or oxide-based material on the semiconductor substrate 102 and selectively etching the nitride or oxide-based material to form a sidewall spacer 212. A sidewall spacer 212 is formed on the opposite side.

FIG. 14 illustrates some embodiments of a cross-sectional view 1400 corresponding to action 1108.

As shown in the cross-sectional view 1400, one or more dielectric layers 124 are selectively formed over the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 may be deposited by a vapor deposition technique and then patterned and etched (eg, according to a photoresist mask). In some embodiments, one or more of the dielectric layers 124 may be etched to expose a portion of the gate electrode 108 and spaced laterally from the drain region 106.

In some embodiments, the one or more dielectric layers 124 may include a silicide blocking layer, such as a photoresist protective oxide (RPO) layer. In other embodiments, the one or more dielectric layers 124 may further and / or alternatively include a field plate etch stop layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by a vapor deposition technique. In yet other embodiments, the one or more dielectric layers 124 may further and / or alternatively include a gate dielectric layer or an interlayer dielectric (ILD) layer.

FIG. 15 illustrates some embodiments of a cross-sectional view 1500 corresponding to action 1110.

As shown in the cross-sectional view 1500, a contact etch stop layer (CESL) 1502 is formed over the semiconductor substrate 102. In some embodiments, CESL 1502 may be formed by a vapor deposition process. A first interlayer dielectric (ILD) layer 1504 is then formed over CESL 1502. In some embodiments, the first ILD layer 1504 may include an ultra-low dielectric constant dielectric material or a low dielectric constant dielectric material (eg, SiCO). In some embodiments, the first ILD layer 1504 can also be formed by a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin coating process. It should be understood that the term interlayer dielectric (ILD) layer as used herein may also refer to an inter-metal dielectric (IMD) layer.

FIG. 16 illustrates some embodiments of a cross-sectional view 1600 corresponding to action 1112.

As shown in cross-sectional view 1600, the first ILD layer 1504 is selectively exposed to a first etchant 1602, which is used to form a contact opening 1606 and a field plate opening 1608. In some embodiments, the contact opening 1606 may be smaller than the field plate opening 1608. In some embodiments, the first ILD layer 1504 is selectively exposed to the first etchant 1602 according to the mask layer 1604 (eg, a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have a large etch selectivity between the first ILD layer 1504 and the field plate ESL within the one or more dielectric layers 124. In some embodiments, the first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may have an etching chemistry including oxygen (O ₂ ), nitrogen (N ₂ ), hydrogen (Hydrogen; H ₂ ), argon (Argon; Ar) ) And / or one or more of the fluorine species (eg, CF ₄ , CHF ₃ , C ₄ F _8, etc.). In other embodiments, the first etchant 1602 may include a wet etchant including buffered hydroflouric acid (BHF).

FIG. 17 illustrates some embodiments of the cross-sectional view 1700 corresponding to actions 1114 to 1116.

As shown in the cross-sectional view 1700, the contact opening 1606 and the field plate opening 1608 are filled with a first metal material 1702. In some embodiments, the first metal material 1702 may be deposited by means of a vapor deposition technique (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the first metal material 1702 may be formed by depositing a seed layer by means of physical vapor deposition before a plating process (eg, an electroplating or electrodeless plating process). A planarization process (eg, chemical mechanical planarization) may be subsequently performed to remove excess first metal material 1702 and to form a flat surface along line 1704.

In some embodiments, the first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the diffusion barrier layer and / or the lining layer may be deposited into the contact openings 1606 and the field plate openings 1608 before the first metal material 1702 is deposited.

FIG. 18 illustrates some embodiments of a cross-sectional view 1800 corresponding to the action 1118.

As shown in cross-sectional view 1800, a second metal material 1802 is deposited. A second metal material 1802 is formed in the remaining openings in the field plate opening and above the first ILD layer 118. In some embodiments, the second metal material 1802 may be deposited by means of a vapor deposition technique (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the second metal material 1802 may be formed by depositing a seed layer by means of physical vapor deposition before the plating process. In some embodiments, the second metal material 1802 may include copper (Cu) or aluminum copper (AlCu) alloy.

After being formed, the second metal material 1802 may be selectively patterned to define one or more metal structures overlying the first metal line layer 418 of the first ILD layer 118. In some embodiments, a patterned mask layer (eg, a photoresist layer or a hard mask layer) (not shown) may be formed over the second metal material 1802 and then the patterned mask layer may be formed. The second metal material 1802 in the exposed area is etched to selectively pattern the second metal material 1802.

FIG. 19 illustrates some embodiments of a cross-sectional view 1900 corresponding to action 1120.

As shown in cross-sectional view 1900, a second ILD layer 416 is formed over one or more metal structures of the first ILD layer 118 and the first metal line layer 418. In various embodiments, the second ILD layer 416 may be formed by depositing a second ILD material over one or more metal structures of the first ILD layer 118 and the first metal line layer 418. After the second ILD layer 416 is formed, a planarization process (eg, CMP) is performed to remove the excess second ILD layer 416 and to expose the top surface of the one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may include an ultra-low-k dielectric material or a low-k dielectric material (eg, SiCO) formed by a vapor deposition processor or a spin coating process. .

It should be understood that height differences between multiple contacts (eg, contact 120) and field plates (eg, field plate 122) may cause difficulties during the fabrication of the disclosed transistor element. For example, since a field plate (for example, field plate 122) is formed over a dielectric layer 124 (for example, photoresist protective oxide), a field plate (for example, field plate 122) has more contacts (for example, Contact 120) smaller height. However, the same etching process is used to form a field plate (eg, the field plate 122) and a plurality of contacts (eg, the contacts 120). The difference in height may cause over-etching of the field plate opening (eg, the field plate opening 1608 of FIG. 16) or under-etching of the contact opening (eg, the contact opening 1606 of FIG. 16), so The over-etching results in a short circuit between the field plate (eg, field plate 122) and the conductive channel of the transistor element, and the etching does not completely cause multiple contacts (eg, contact 120) and the source region (eg, Poor connection between the source region 104), the drain region (eg, the drain region 106), and / or the gate region (eg, the gate region 116).

To prevent over-etching of the field plate opening or incomplete etching of the contact opening, in some embodiments, a composite etch stop layer may be used to control the etching depth of the field plate opening. By controlling the etch depth of the field plate opening, the composite etch stop layer allows multiple contacts (eg, contact 120) and field plates (eg, field plate 122) to both be accurately formed to have different heights.

FIG. 20 illustrates a cross-sectional view of some embodiments of a disclosed high voltage transistor element 2000 having a composite etch stop layer defining a field plate.

The high-voltage piezoelectric crystal element 2000 includes a gate structure 116 disposed above the semiconductor substrate 102. The gate structure 116 includes a gate dielectric layer 110 and an overlying gate electrode 108. In some embodiments, the gate structure 116 may have a first thickness th _{1 in} a range between about 1000 Angstroms and about 2000 Angstroms. The source region 104 and the drain region 106 are disposed in the semiconductor substrate 102 on opposite sides of the gate structure 116.

A photoresist protective oxide (RPO) 2002 is disposed above the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 to laterally beyond the outermost sidewall of the gate structure 116. In some embodiments, the RPO 2002 may extend vertically from the upper surface of the gate structure 116 to the upper surface of the semiconductor substrate 102, and may extend laterally from directly above the gate structure 116 to the gate structure 116 and the drain region 106. between. In some embodiments, RPO 2002 may include silicon dioxide, silicon nitride, or the like. In some embodiments, the RPO 2002 may have a second thickness th _{2 in} a range between about 100 angstroms and about 1000 angstroms.

A composite etch stop layer 2004 is disposed above the RPO 2002. In some embodiments, the composite etch stop layer 2004 directly contacts one or more upper surfaces of the RPO 2002. The first interlayer dielectric (ILD) layer 118 and the field plate 122 are disposed above the composite etch stop layer 2004. The first ILD layer 118 surrounds the field plate 122 and a plurality of contacts 120, which are coupled to the source region 104, the drain region 106, and the gate structure 116. In some embodiments, the field plate 122 and the plurality of contacts 120 may include a diffusion barrier (not shown) surrounding a conductive core, the conductive core including one or more metals.

The composite etch stop layer 2004 includes a plurality of different dielectric materials 2006 to 2008 stacked on top of the RPO 2002. In some embodiments, a plurality of different dielectric materials 2006 to 2008 may have an outermost sidewall that is aligned substantially along a line perpendicular to an upper surface of the semiconductor substrate 102. In some embodiments, a plurality of different dielectric materials 2006 to 2008 may have an outermost sidewall substantially aligned with an outermost sidewall of the RPO 2002. In such embodiments, the RPO 2002 has a first width that is substantially equal to a second width of the composite etch stop layer 2004. The plurality of different dielectric materials 2006 to 2008 have different etching characteristics, and the etching characteristics provide different etch selectivities to the etchant for corresponding ones of the plurality of different dielectric materials 2006 to 2008. Different etch selectivities may allow the composite etch stop layer 2004 to slow the etching of the field plate opening (ie, define the opening of the field plate 122), and thus tightly control the height of the field plate and allow multiple contacts 120 and the field plate 122 (For example, allowing multiple contacts 120 to have a higher height than the field plate 122).

For example, in some embodiments, the bottom of the field plate 122 is in contact with the composite etch stop layer 2004 along an interface that is vertically higher than the plurality of contacts 120 (eg, coupled to the source region 104 and the drain region). 106 contacts) of the bottom surface of one or more of them. In such embodiments, during the manufacture of the high-voltage transistor element 2000, the composite etch stop layer 2004 reduces the etch rate of the etchant used to form the field plate openings (ie, the openings defining the field plate 122). The reduction in the etch rate causes the field plate 122 to have a bottom surface that is higher than the bottom surface of one or more of the plurality of contacts 120.

In some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 in direct contact with the upper surface of the RPO 2002 and a second dielectric material 2008 in direct contact with the upper surface of the first dielectric material 2006. In some embodiments, the first dielectric material 2006 may have a third thickness th ₃ , and the second dielectric material 2008 may have a fourth thickness th ₄ . In some embodiments, the RPO 2002 and the composite etch stop layer 2004 may each have a substantially continuous thickness between the outermost sidewalls. If the third thickness th ₃ and the fourth thickness th _{4 are} too small (for example, less than the minimum value described below), the composite etch stop layer 2004 cannot effectively stop the etching that forms the field plate opening. If the third thickness th ₃ and the fourth thickness th _{4 are} too large (for example, larger than the maximum value described below), the effect of the field plate 122 on the high-voltage transistor element 2000 is reduced, which adversely affects the element performance.

In some embodiments, the first dielectric material 2006 may include or may be silicon nitride (Si _x N _y ), and the second dielectric material 2008 may include or may be silicon dioxide (SiO ₂ ). In such embodiments, the first thickness th ₁ may be within a first range between about 50 angstroms and about 400 angstroms, and the second thickness th ₂ may be between a first thickness between about 150 angstroms and about 700 angstroms. Within two. In other embodiments, the first dielectric material 2006 may include or may be silicon dioxide (SiO ₂ ), and the second dielectric material 2008 may include or may be silicon nitride (SiN _x ) or silicon oxynitride (SiO _x N _y ). In such embodiments, the first thickness th ₁ may be within a first range between about 600 angstroms and about 900 angstroms. In some embodiments, the second thickness th ₂ may be within a second range between about 100 angstroms and about 500 angstroms.

21A-21B illustrate some other embodiments of the disclosed high-voltage transistor device with a composite etch stop layer defining a field plate.

As shown in cross-sectional view 2100 of FIG. 21A, the high-voltage transistor element includes a semiconductor substrate 102 having a body region 2106 disposed within a drift region 2104 above the substrate 2102. The source region 104 is disposed in the body region 2106, and the drain region 106 is disposed in the drift region 2104. In some embodiments, the source region 104, the drain region 106, and the drift region 2104 may have a first doping type (for example, n-type), and the body region 2106 and the substrate 2102 have a first doping type opposite to the first doping type. Two-doped type (for example, p-type). In some embodiments, the source region 104 and the drain region 106 may include a highly doped region (ie, an n + region) with a higher doping concentration than the drift region 2104.

The gate structure 116 is disposed above the semiconductor substrate 102 between the source region 104 and the drain region 106. The RPO 2002 is disposed above the gate structure 116 and extends laterally beyond the outermost sidewall of the gate structure 116. The composite etch stop layer 2004 is disposed between the RPO 2002 and the field plate 122. In some embodiments, the RPO 2002 may surround the field plate 122 (ie, extend beyond the outermost sidewall of the field plate 122) at one or more lateral distances 2108, which are between about 0 microns and about 2 microns Within range.

In some embodiments, the field plate 122 may extend a non-zero depth 2110 into the composite etch stop layer 2004. In such embodiments, the field plate 122 contacts the sidewalls of the composite etch stop layer 2004. In various embodiments, the field plate 122 may also contact the horizontally extending surface of the composite etch stop layer 2004 or the horizontally extending surface of the RPO 2002. In some embodiments, the non-zero depth 2110 may be in a range between about 400 angstroms and about 700 angstroms. Since the field plate 122 extends into the composite etch stop layer 2004, the composite etch stop layer 2004 has a first thickness 2112 directly below the field plate 122 and a second thickness larger than the first thickness 2112 outside the field plate 122. In some embodiments, the first thickness 2112 is in a range between about 0 angstroms and about 10,000 angstroms. In some other embodiments, the first thickness 2112 is in a range between about 600 angstroms and about 300 angstroms.

As shown in the top view 2120 of FIG. 21B (along the cross-sectional line A-A 'of FIG. 21A), the field plate 122 has a width 2114 extending a certain distance in the first direction, and the distance ranges from about 150 nanometers Between rice and about 2000 nanometers. The field plate 122 also has a length 2122 extending in a second direction (perpendicular to the first direction) with a distance of less than about 1000 microns.

Referring again to the cross-sectional view 2100 of FIG. 21A, in some embodiments, the field plate 122 may be laterally separated from the gate structure 116 by a distance 2116. For example, the field plate 122 may be laterally separated from the gate structure 116 by a distance 2116 in a range between about 0 nm and about 500 nm. In other embodiments (not shown), the field plate 122 may laterally overlap the gate structure 116 (ie, extend directly above). For example, the field plate 122 may laterally overlap the gate structure 116 with a distance in a range between about 0 nm and about 200 nm.

In some embodiments, the silicide layer 2118 is disposed above the source region 104, the drain region 106, and the portion of the gate structure 116 that is not covered by the RPO 2002. In various embodiments, the silicide layer 2118 may include a compound having silicon and a metal, such as nickel, platinum, titanium, tungsten, magnesium, or the like. In some embodiments, the silicide layer 2118 has a thickness in a range between about 150 angstroms and about 400 angstroms.

22 illustrates a cross-sectional view of some other embodiments of the disclosed high-voltage transistor element 2200 with a composite etch stop layer defining a field plate.

The high-voltage piezoelectric crystal element 2200 includes a gate electrode 108 disposed above the semiconductor substrate 102. The RPO 2002 and the composite etch stop layer 2004 are located above the gate electrode 108 and the semiconductor substrate 102. A contact etch stop layer (CESL) 406 is disposed above the composite etch stop layer 2004. In some embodiments, the bottom surface of the composite etch stop layer 2004 may directly contact the RPO 2002, and the top surface of the composite etch stop layer 2004 may directly contact the CESL 406. The CESL 406 extends laterally beyond the outermost sidewall of the composite etch stop layer 2004 and contacts the semiconductor substrate 102. In some embodiments, the CESL 406 may have a thickness th _{5 in} a range between about 100 Angstroms and about 1000 Angstroms. In some embodiments, CESL 406 may include silicon nitride, silicon carbide, or the like.

The field plate 408 is disposed in the first ILD layer 118 above the CESL 406. In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The composite etch stop layer 2004 is horizontally disposed between the field plate 408 and the gate structure 116, and is vertically disposed between the field plate 122 and the semiconductor substrate 102. RPO 2002 and composite etch stop layer 2004 have sidewalls that are in contact with CESL 406. The composite etch stop layer 2004 further has a horizontally extending surface (eg, an upper surface) in contact with the CESL 406.

In some embodiments, the field plate 122 may extend into one or more of a plurality of different dielectric materials 2006 to 2008 within the composite etch stop layer 2004. For example, in some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2008 that is in contact with an upper surface of the first dielectric material 2006. The field plate 122 may extend through the second dielectric material 2008 (eg, silicon oxide) and have a bottom surface in contact with the first dielectric material 2006 (eg, silicon nitride). In such embodiments, the second dielectric material 2008 may vertically separate the bottommost point of the field plate 122 from the RPO 2002. In other embodiments, the field plate 122 may further extend through the first dielectric material 2006 and have a bottom surface and / or sidewalls in contact with the RPO 2002. In some embodiments, the field plate 122 may extend vertically through the second dielectric material 2008 and also be laterally separated from the gate structure 116 by the second dielectric material 2008.

Although the disclosed composite etch stop layer 2004 is shown in FIGS. 20 to 22 as having two different dielectric materials 2006 to 2008 stacked on top of the RPO 2002, it should be understood that the disclosed composite etch stop layer 2004 is not limited to such configurations. Specifically, in various embodiments, the composite etch stop layer 2004 may include other layers of a dielectric material. FIGS. 23-24 illustrate some non-limiting examples of alternative embodiments of the composite etch stop layer 2004 disclosed.

FIG. 23 illustrates a cross-sectional view of some other embodiments of the disclosed high voltage transistor element 2300 having a composite etch stop layer defining a field plate.

The high-voltage piezoelectric crystal element 2300 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2302, a second dielectric material 2304 that is in contact with the upper surface of the first dielectric material 2302, and a third dielectric material 2306 that is in contact with the upper surface of the second dielectric material 2304. . In some embodiments, the first dielectric material 2302 may include or may be silicon dioxide (SiO ₂ ), and the second dielectric material 2304 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride ( SiO _x N _y ), and the third dielectric material 2306 may include or may be silicon dioxide (SiO ₂ ).

In some embodiments, the first dielectric material 2302 may have a first thickness, the second dielectric material 2304 may have a second thickness, and the third dielectric material 2306 may have a third thickness. In some embodiments, the first thickness may be in a first range between about 300 Angstroms and about 900 Angstroms, the second thickness may be in a second range between about 50 Angstroms and about 200 Angstroms, and the first The three thicknesses may be in a third range between about 200 angstroms and about 600 angstroms.

FIG. 24 illustrates a cross-sectional view of some other embodiments of the disclosed high voltage transistor element 2400 with a composite etch stop layer defining a field plate.

The high-voltage piezoelectric crystal element 2400 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2402, a second dielectric material 2404 in contact with an upper surface of the first dielectric material 2402, and a third dielectric material 2406 in contact with an upper surface of the second dielectric material 2404. And a fourth dielectric material 2408 in contact with an upper surface of the third dielectric material 2406. In some embodiments, the first dielectric material 2402 may include or may be silicon dioxide (SiO ₂ ), and the second dielectric material 2404 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride ( SiO _x N _y ), the third dielectric material 2406 may include or may be silicon dioxide (SiO ₂ ), and the fourth dielectric material 2408 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride (SiO _x N _y ).

In some embodiments, the first dielectric material 2402 may have a first thickness, the second dielectric material 2404 may have a second thickness, the third dielectric material 2406 may have a third thickness, and the fourth dielectric material 2408 may Has a fourth thickness. In some embodiments, the first thickness may be in a first range between about 300 Angstroms and about 900 Angstroms, the second thickness may be in a second range between about 50 Angstroms and about 200 Angstroms, and the third The thickness may be in a third range between about 200 angstroms and about 600 angstroms, and the fourth thickness may be in a fourth range between about 50 angstroms and about 200 angstroms.

25 to 32 illustrate cross-sectional views of some embodiments of a method of forming a high-voltage transistor element having a composite etch stop layer defining a field plate. Although the cross-sectional views 2500 to 3200 shown in FIGS. 25 to 32 are described with reference to one method, it should be understood that the structure shown in FIGS. 25 to 32 is not limited to the method but may be independent于 所述 方法 In the method.

As shown in the cross-sectional view 2500 of FIG. 25, the semiconductor substrate 102 is selectively patterned to form a plurality of implanted regions (eg, well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively patterned to form a body region 2106, a drift region 2104, a source region 104, and a drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively patterned to form different implanted regions (eg, any of those implanted regions illustrated in FIGS. 1-10). In some embodiments, the semiconductor substrate 102 may be selectively shielded (eg, using a photoresist mask) and then a high energy dopant (eg, a p-type dopant species such as boron; or n-type dopants A dopant such as phosphorus is introduced into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions.

The gate structure 116 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by depositing a gate dielectric layer 110 over the semiconductor substrate 102 and by depositing a gate electrode material 108 over the gate dielectric layer 110. The gate dielectric layer 110 and the gate electrode material 108 may then be patterned (eg, etched according to a photoresist mask and / or a hard mask) to define the gate structure 116.

As shown in the cross-sectional view 2600 of FIG. 26, a photoresist protective oxide (RPO) 2002 is formed over the gate structure 116. The RPO 2002 extends laterally from directly above the gate structure 116 to beyond the outermost sidewall of the gate structure 116. RPO 2002 is configured to block silicide formation on the underlying layer. In some embodiments, RPO 2002 may be deposited by a vapor deposition technique (eg, CVD). In some embodiments, the RPO 2002 may include silicon dioxide (SiO ₂ ), silicon nitride, or the like.

As shown in cross-sectional view 2700 of FIG. 27, a composite etch stop layer 2004 including a plurality of different dielectric materials 2006 to 2008 is selectively formed over the RPO 2002. In some embodiments, a plurality of different dielectric materials 2006 to 2008 may be sequentially deposited by a vapor deposition technique. In some embodiments, the composite etch stop layer 2004 may include a stacked layer including a silicon nitride (Si _x N _y ) layer, a silicon oxynitride (SiO _x N _y ) layer, and a silicon dioxide (SiO ₂ ) Two or more of the layers.

In some embodiments, the same mask layer 2702 (eg, a photoresist layer) and an etching process may be used to pattern a plurality of different dielectric materials 2006 to 2008 and RPO 2002. Using the same mask layer 2702 to pattern multiple different dielectric materials 2006 to 2008 and RPO 2002 can reduce the cost of forming the composite etch stop layer 2004. In such embodiments, a plurality of different dielectric materials 2006 to 2008 and RPO 2002 may have substantially aligned sidewalls.

As shown in the cross-sectional view 2800 of FIG. 28, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the composite etch stop layer 2004. In some embodiments, CESL 406 may be formed by a vapor deposition process. The CESL may include a nitride layer (eg, Si ₃ N ₄ ), a carbide layer (SiC), or the like.

As shown in cross-sectional view 2900 of FIG. 29, a first interlayer dielectric (ILD) layer 118 is formed over CESL 406. In some embodiments, the first ILD layer 118 may include an oxide (eg, SiO ₂ ), an ultra-low dielectric constant dielectric material, a low dielectric constant dielectric material (eg, SiCO), or the like. In some embodiments, the first ILD layer 118 may be formed by a vapor deposition process.

As shown in the cross-sectional view 3000 of FIG. 30, the first ILD layer 118 is selectively exposed to an etchant 3002 (eg, according to the mask layer 3003) to form a plurality of contact openings 1606 and fields within the first ILD layer 118. Board opening 1608. The contact opening 1606 and the field plate opening 1608 have a non-zero etch depth difference of a distance 3004. In some embodiments, the non-zero distance 3004 may be in a range between about 400 Angstroms and about 2000 Angstroms. In some embodiments, the field plate opening 1608 extends into the composite etch stop layer 2004 so that the composite etch is terminated. The sidewalls of layer 2004 define a field plate opening 1608. In various embodiments, the composite etch stop layer 2004 or RPO 2002 may define the bottom of the field plate opening 1608.

In some embodiments, the etchant 3002 can reduce the thickness of the composite etch stop layer 2004 by an amount in a range between about 400 angstroms and about 700 angstroms. In some embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 0 angstroms and about 1,000 angstroms. In some other embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 300 angstroms and about 900 angstroms.

The etchant 3002 used to form the contact openings 1608 and the field plate openings 1608 is selected to etch the material passing through the CESL 406. However, since the composite etch stop layer 2004 is formed of a plurality of different materials, the composite etch stop layer 2004 is able to resist the etching of the etchant 3002 to a high degree. The composite etch stop layer 2004 further allows the contact openings 1606 to extend to the semiconductor substrate 102, and prevents the field plate openings 1608 from extending to the semiconductor substrate 102. The composite etch stop layer 2004 also allows a high degree of uniformity of etch depth on a substrate, between multiple substrates of the same lot, and / or at different positions above multiple substrates of different lots. For example, the composite etch stop layer 2004 allows the etch depth of the field plate openings 1608 on different substrates to be within a deviation of about 2% or less. This etch depth uniformity allows improved component uniformity and performance, which surpasses components without a composite etch stop layer 2004.

As shown in cross-sectional view 3100 of FIG. 31, a plurality of contact openings 1606 and field plate openings 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials can be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.) and / or plating processes (eg, electroplating or electrodeless plating processes). A planarization process (eg, chemical mechanical planarization) may then be performed to remove excess one or more conductive materials and form a flat surface along line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the diffusion barrier layer and / or the lining layer may be deposited into the plurality of contact openings 1606 and the field plate openings 1608 before depositing one or more conductive materials.

As shown in the cross-sectional view 3200 of FIG. 32, a second ILD layer 126 is formed over the first ILD layer 118, and a first back-end process (BEOL) metal wire layer 128 is formed in the second ILD layer 126. In various embodiments, the second ILD layer 126 may be formed by depositing a second ILD material over the first ILD layer 118. The second ILD layer 126 is then etched to form trenches extending within the second ILD layer 126. The trench is filled with a conductive material, and a planarization process (eg, CMP) is performed to remove excess conductive material from above the second ILD layer 126.

FIG. 33 illustrates a flowchart of some embodiments of a method 3300 of forming a high-voltage transistor element with a composite etch stop layer defining a field plate.

At 3302, a gate structure is formed over the substrate. FIG. 25 illustrates a cross-sectional view 2500 of some embodiments corresponding to action 3302.

At 3304, a source region and a drain region are formed in the substrate on opposite sides of the gate structure. In some other embodiments, one or more additional doped regions (eg, a body region, a drift region, etc.) may also be formed in the substrate. FIG. 25 illustrates a cross-sectional view 2500 corresponding to some embodiments of action 3304.

At 3306, a photoresist protective oxide (RPO) is formed above the gate structure and formed laterally between the gate structure and the drain region. FIG. 26 illustrates a cross-sectional view 2600 of some embodiments corresponding to action 3306.

At 3308, a composite etch stop layer is formed over the RPO. FIG. 27 illustrates a cross-sectional view 2700 of some embodiments corresponding to action 3308.

At 3310, a contact etch stop layer (CESL) is formed on the composite etch stop layer. FIG. 28 illustrates a cross-sectional view 2800 of some embodiments corresponding to action 3310.

At 3312, a first interlayer dielectric (ILD) layer is formed over CESL. FIG. 29 illustrates a cross-sectional view 2900 of some embodiments corresponding to action 3312.

At 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The plurality of contact openings and the field plate openings have different depths. FIG. 30 illustrates a cross-sectional view 3000 of some embodiments corresponding to action 3314.

At 3316, a plurality of contact openings and field plate openings are filled with one or more conductive materials. FIG. 31 illustrates a cross-sectional view 3100 of some embodiments corresponding to action 3316.

At 3318, conductive interconnects are formed in the second ILD layer above the first ILD layer. FIG. 32 illustrates a cross-sectional view 3200 of some embodiments corresponding to action 3318.

Therefore, the present disclosure relates to a high-voltage transistor device having a field plate, which is formed at the same time as the conductive contact is formed. The element has a composite etch stop layer for achieving a height difference between the field plate and the conductive contact.

In some embodiments, the present disclosure relates to a compact chip. The integrated chip includes: a gate structure, which is disposed above the substrate between the source region and the drain region; a dielectric layer, which extends laterally from above the gate structure to between the gate structure and the drain region; the composite etching is terminated Layer, having a plurality of different dielectric materials stacked above the dielectric layer; contacting the etch stop layer, directly contacting the upper surface of the composite etch stop layer and a plurality of sidewalls; and a field plate, which is laterally surrounded by the first ILD layer And extends vertically from the top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer. In some embodiments, the composite etch stop layer has a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate extends vertically through the second dielectric material, and the field plate is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material includes silicon nitride and the second dielectric material includes silicon dioxide. In some embodiments, the first dielectric material includes silicon dioxide, and the second dielectric material includes silicon nitride or silicon oxynitride. In some embodiments, the field plate extends vertically through the second dielectric material, and the field plate is vertically separated from the gate structure by the first dielectric material. In some embodiments, the composite etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate. In some embodiments, the composite etch stop layer laterally contacts multiple sidewalls of the field plate. In some embodiments, the bottom of the field plate is vertically separated from the dielectric layer by a composite etch stop layer. In some embodiments, the dielectric layer includes a photoresist protective oxide having a lower surface in contact with the gate structure and an upper surface in contact with the composite etch stop layer.

In other embodiments, the present disclosure relates to a compact chip. The integrated wafer includes: a gate structure, which is disposed above the substrate; a photoresist protective oxide, which extends laterally from above the gate structure to the outermost side wall of the gate structure; a composite etch stop layer with a photoresist protective oxide A first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material; a plurality of conductive contacts laterally surrounded by a first interlayer dielectric (ILD) layer above a substrate; and a field A plate extending from the top of the first ILD layer to the composite etch stop layer and containing the same material as the plurality of conductive contacts, the composite etch stop layer laterally contacts the plurality of sidewalls of the field plate, and the composite etch stop layer The bottom of the field plate is vertically separated from the photoresist protective oxide. In some embodiments, the field plate extends vertically through the second dielectric material, and the field plate is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material is an oxide and the second dielectric material is a nitride. In some embodiments, the composite etch stop layer further includes a third dielectric material in contact with the upper surface of the second dielectric material, and the first dielectric material and the third dielectric material are the same material. In some embodiments, the integrated wafer further includes a contact etch stop layer in direct contact with the upper surface of the composite etch stop layer and the plurality of sidewalls, and the field plate extends through the contact etch stop layer. In some embodiments, the photoresist protective oxide has a first width that is substantially equal to a second width of the composite etch stop layer.

In still other embodiments, the present disclosure relates to a method for forming a integrated wafer. The method includes: forming a gate structure above a substrate between a source region and a drain region within the substrate; forming a dielectric layer above the gate structure and between the gate structure and the drain region; and above the dielectric layer Forming a composite etch stop layer comprising a plurality of stacked dielectric materials; forming a first interlayer dielectric (ILD) layer above the composite etch stop layer; selectively etching the first ILD layer to simultaneously define A plurality of contact openings extending to the substrate and a field plate opening extending to the composite etch stop layer; and filling the plurality of contact openings and field plate openings with one or more conductive materials. In some embodiments, the composite etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate opening extends vertically through the second dielectric material, and the field plate opening is laterally separated from the gate structure by the second dielectric material. In some embodiments, the method further includes: forming a mask layer over the composite etch stop layer; and etching the composite etch stop layer and the dielectric layer according to the mask layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that it may be easy to use the disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes in this document without departing from the spirit and scope of the present disclosure. Changes, substitutions and alterations.

100, 800, 2000, 2200, 2300, 2400‧‧‧ high voltage transistor components

102, 802, 2102 ‧‧‧ substrate

104, 804‧‧‧Source area

105‧‧‧ Arrow

106‧‧‧ Drain

108‧‧‧Gate electrode

110‧‧‧Gate dielectric layer

112‧‧‧Channel area

114, 204, 702, 2104‧‧‧ drift zone

116, 210‧‧‧Gate structure

118, 1504‧‧‧‧First interlayer dielectric layer

120, 814‧‧‧ contact

120a‧‧‧First contact

120b‧‧‧Second contact

120c‧‧‧Third contact

122, 214, 408, 902‧‧‧ field boards

124, 402, 404‧‧‧ dielectric layers

126‧‧‧Second dielectric layer

128‧‧‧ the first and last process metal wire

200, 300, 400, 500, 600, 700a, 700b, 700c, 1000‧‧‧ high voltage LDMOS devices

202, 808, 2106 ‧‧‧ main area

206‧‧‧Extra STI Zone

208, 810‧‧‧ contact area

212‧‧‧ sidewall spacer

302‧‧‧ Quarantine

402‧‧‧ silicide barrier

404‧‧‧field plate etch stop layer

406, 1502‧‧‧‧ Contact etch stop layer

410, 1702‧‧‧‧First metal material

412, 1802‧‧‧‧Second metal material

414‧‧‧lining

416‧‧‧Second interlayer dielectric layer

418, 504, 604‧‧‧‧ First metal wire layer

420‧‧‧ flat surface

502, 602, 904‧‧‧‧Second ILD layer

506, 606‧‧‧ conductive path

704‧‧‧deep well

706‧‧‧ Relatively doped underlying buried layer

708‧‧‧matrix area

710‧‧‧ buried layer

712‧‧‧well

802b‧‧‧back

802f‧‧‧ front side surface

806‧‧‧Epitaxial layer

812‧‧‧ conductive material

816‧‧‧ Overlay metal wire layer

818‧‧‧electric path

900, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2100, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200

906, 2120‧‧‧ Top view

1002‧‧‧self-aligned drift region

1002s‧‧‧Sidewall

1100, 3300‧‧‧Method

1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 3302, 3304, 3306, 3308, 3310, 3312, 3314, 3316, 3318 ‧

1202, 1604, 2702

1204‧‧‧High Energy Dopant

1602‧‧‧The first etchant

1606‧‧‧ contact opening

1608‧‧‧field board opening

1704, 3102‧‧‧ line

2002‧‧‧Photoresist protective oxide

2004‧‧‧Composite etch stop layer

2006, 2302, 2402, ‧‧‧ first dielectric material

2008, 2304, 2404‧‧‧Second dielectric material

2108‧‧‧Horizontal distance

2110‧‧‧ Depth

2112, t ₁ , th ₁ ‧‧‧ first thickness

2114‧‧‧Width

2122‧‧‧length

2116, d 3, 004‧‧‧ distance

2118‧‧‧ silicide layer

2306, 2406‧‧‧Third dielectric material

2408‧‧‧Fourth dielectric material

3002‧‧‧etching agent

t ₂ , th ₂ ‧‧‧ second thickness

th ₃ ‧‧‧ third thickness

th ₄ ‧‧‧ fourth thickness

th ₅ ‧‧‧thickness

s ‧‧‧ pitch

Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of some embodiments of a disclosed high-voltage transistor element having a field plate.

2 to 4 illustrate cross-sectional views of some other embodiments of a disclosed high voltage laterally diffused metal oxide semiconductor field effect transistor (LDMOS) device having a field plate.

FIG. 5 to FIG. 6 are cross-sectional views of some embodiments of a field plate biasing configuration for a high-voltage LDMOS device achieved by metal interconnection wiring.

7A-7C illustrate cross-sectional views of some embodiments of high-voltage LDMOS devices in different switching isolation configurations.

FIG. 8 illustrates a cross-sectional view of a high-voltage transistor element with a source plate facing down.

9A-9B illustrate some embodiments of a disclosed high-voltage LDMOS having a field plate on a metal line layer.

FIG. 10 illustrates some embodiments of a high-voltage LDMOS device having a self-aligned drift region.

11 illustrates a flowchart of some embodiments of a method of forming a high-voltage transistor element having a field plate.

12 to 19 illustrate cross-sectional views of some embodiments of a method of forming a high-voltage transistor element having a field plate.

20 to 24 illustrate some embodiments of the disclosed high voltage transistor device with a composite etch stop layer defining a field plate.

25 to 32 illustrate cross-sectional views of some embodiments of a method of forming a high-voltage transistor element having a composite etch stop layer defining a field plate.

FIG. 33 illustrates a flowchart of some embodiments of a method of forming a high-voltage transistor element with a composite etch stop layer defining a field plate.

Claims (20)

An integrated wafer includes: The gate structure is disposed above the substrate between the source region and the drain region; A dielectric layer extending laterally from above the gate structure to between the gate structure and the drain region; A composite etch stop layer including a plurality of different dielectric materials stacked over the dielectric layer; Contacting the etch stop layer, directly contacting an upper surface and a plurality of sidewalls of the composite etch stop layer; and A field plate is laterally surrounded by a first interlayer dielectric layer and extends vertically from the top of the first interlayer dielectric layer, through the contact etch stop layer, and to the composite etch stop layer in. The integrated wafer as described in claim 1, wherein the composite etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. The integrated wafer according to item 2 of the patent application scope, wherein the field plate extends vertically through the second dielectric material, and the field plate is connected to the gate by the second dielectric material and the gate. The pole structures are laterally separated. The integrated wafer according to item 2 of the patent application scope, wherein the first dielectric material includes silicon nitride, and the second dielectric material includes silicon dioxide. The integrated wafer according to item 2 of the patent application scope, wherein the first dielectric material includes silicon dioxide, and the second dielectric material includes silicon nitride or silicon oxynitride. The integrated wafer according to item 2 of the patent application range, wherein the field plate extends vertically through the second dielectric material, and the field plate is connected to the gate by the first dielectric material The pole structures are vertically separated. The integrated wafer according to item 1 of the patent application scope, wherein the composite etching stop layer has a first thickness directly below the field plate and a second thickness outside the field plate. The integrated wafer as described in claim 1, wherein the composite etch stop layer laterally contacts a plurality of side walls of the field plate. The integrated wafer according to item 1 of the scope of patent application, wherein the bottom of the field plate is vertically separated from the dielectric layer by the composite etch stop layer. The integrated wafer according to item 1 of the scope of patent application, wherein the dielectric layer includes a photoresist protective oxide, the photoresist protective oxide having a lower surface in contact with the gate structure, and the composite The upper surface contacted by the etch stop layer. An integrated wafer includes: Gate structure, placed above the base; A photoresist protective oxide, extending laterally from above the gate structure beyond the outermost side wall of the gate structure; A composite etch stop layer comprising a first dielectric material over the photoresist protective oxide and a second dielectric material in contact with an upper surface of the first dielectric material; A plurality of conductive contacts laterally surrounded by a first interlayer dielectric layer above the substrate; and A field plate extending from the top of the first interlayer dielectric layer to the composite etch stop layer and including the same material as the plurality of conductive contacts, wherein the composite etch stop layer laterally contacts the field Multiple sidewalls of the plate, and the composite etch stop layer vertically separates the field plate from the photoresist protective oxide. The integrated wafer according to item 11 of the patent application scope, wherein the field plate extends vertically through the second dielectric material, and the field plate is connected to the gate by the second dielectric material and the gate. The pole structures are laterally separated. The integrated wafer according to item 11 of the patent application scope, wherein the first dielectric material is an oxide and the second dielectric material is a nitride. The integrated wafer according to item 11 of the scope of patent application, wherein the composite etch stop layer further includes: A third dielectric material is in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material are the same material. The integrated wafer as described in item 11 of the patent application scope further includes: The contact etch stop layer directly contacts the upper surface of the composite etch stop layer and a plurality of sidewalls, wherein the field plate extends through the contact etch stop layer. The integrated wafer according to item 11 of the patent application scope, wherein the photoresist protective oxide has a first width, and the first width is substantially equal to a second width of the composite etch stop layer. A method for forming an integrated wafer includes: Forming a gate structure over the substrate between a source region and a drain region within the substrate; Forming a dielectric layer over the gate structure and between the gate structure and the drain region; Forming a composite etch stop layer over the dielectric layer, wherein the composite etch stop layer includes a plurality of stacked dielectric materials; Forming a first interlayer dielectric layer over the composite etch stop layer; Selectively etching the first interlayer dielectric layer to simultaneously define a plurality of contact openings extending to the substrate and a field plate opening extending to the composite etch stop layer; and The plurality of contact openings and the field plate openings are filled with one or more conductive materials. The method for forming an integrated wafer according to item 17 of the scope of patent application, wherein the composite etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. The method of forming an integrated wafer as described in claim 18, wherein the field plate opening extends vertically through the second dielectric material, and the field plate opening passes through the second dielectric The material is laterally separated from the gate structure. The method for forming a integrated wafer as described in item 17 of the patent application scope further includes: Forming a mask layer over the composite etch stop layer; and The composite etch stop layer and the dielectric layer are etched according to the mask layer.