TW202324631A - An integrated chip - Google Patents

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure, wherein the opening overlies at least a portion of the semiconductor device.

Description

Integrated chip with good heat dissipation performance

A semiconductor device is an electronic component that utilizes the electronic properties of semiconductor materials to affect electronics or related fields. A metal oxide semiconductor field-effect transistor (MOSFET) is a widely used type of semiconductor device. Semiconductor devices are traditionally formed on bulk semiconductor substrates. In recent years, semiconductor-on-insulator substrates that can replace bulk semiconductor substrates have emerged. Another type of semiconductor device is a high voltage device, such as a high voltage laterally diffused metal oxide semiconductor (LDMOS) device, capable of handling high breakdown voltage (eg, greater than about 20V or 50V) and high frequency. In the case of using more semiconductor-on-insulator substrates and high-voltage devices, heat dissipation techniques and/or structures need to be adopted to improve device tolerance and increase device density.

The following disclosures will provide a number of different implementations or examples to achieve different features of the provided patent subject matter. Various components and arrangements are described below in terms of specific embodiments to simplify the present disclosure. Of course, these examples are for illustration only and are not intended to limit the present disclosure. For example, "the first feature is formed on the second feature" in the description includes a variety of implementations, including direct contact between the first feature and the second feature, and also covers that additional features are formed between the first feature and the second feature without direct contact between the two. In addition, in various embodiments, the present disclosure may repeat reference numerals and/or indications. This repetition is for simplicity and clarity of illustration and is not intended to imply a relationship between the various implementations and/or configurations discussed herein.

Furthermore, spatially relative terms, such as "lower", "below", "underneath", "above", "above" and other related terms, are used herein to briefly describe elements or features as shown in the drawings A relationship to another element or feature. These spatially relative terms also encompass different orientations in use or operation of the device in addition to the orientations depicted in the figures. In addition, when the device is rotatable (rotated 90 degrees or other angles), the spatially relative descriptors used herein may also be interpreted accordingly.

Parts of integrated chips (ICs) include semiconductor devices (such as insulated gate field-effect transistors (IGFETs) disposed on/in semiconductor-on-insulator (SOI) substrates. )). A semiconductor-on-insulator substrate includes an insulating layer (eg, a dielectric layer) that separates a first semiconductor layer from a second semiconductor layer. The insulating layer is disposed under (eg directly under) the semiconductor device. An intermetal dielectric (IMD) structure and/or a passivation layer are disposed above the semiconductor device. An interconnection structure, such as a copper interconnection structure, is embedded in the IMD structure.

Typically, an IMD structure and/or a passivation layer are disposed directly above the semiconductor device. IMD structures, passivation layers, and insulating layers are made of materials that inhibit heat dissipation (such as dielectric materials) to prevent heat generated by semiconductors from easily escaping from the integrated chip. Therefore, a typical integrated wafer with a semiconductor-on-insulator substrate may have poor heat dissipation performance (such as low dissipation of heat energy generated by the semiconductor device), which can reduce the performance of the integrated wafer and/or damage the semiconductor device (such as caused by thermal runaway ).

Various embodiments of the present disclosure relate to integrated chips with good heat dissipation properties (eg, high dissipation of heat energy generated by semiconductor devices). The integrated chip of the present disclosure includes a substrate. In some embodiments, the substrate is a semiconductor-on-insulator substrate including a device layer disposed above the insulating layer. The semiconductor device is on/over the substrate. The intermetal dielectric structure is disposed above the substrate and the interlayer dielectric structure. Openings, such as pores in the IMD structure, are disposed in the IMD structure. The opening covers at least a portion of the semiconductor device. Since the opening covers at least a portion of the semiconductor device, heat generated by the semiconductor device can be more efficiently dissipated from the semiconductor device (for example, by having less IMD material over the semiconductor device, heat can be more efficiently dissipated from semiconductor device escapes to the atmosphere). Therefore, the integrated chip of the present disclosure has good heat dissipation performance (such as high dissipation of heat energy generated by semiconductor devices).

For example, in a typical integrated wafer, a portion of the IMD structure (and/or a passivation layer) covers the semiconductor device directly above, which can suppress heat dissipation of the semiconductor device. Unlike typical bulk wafers, the opening covers at least a portion of the semiconductor device. The opening may be more efficient at dissipating thermal energy than a portion of the IMD structure. Therefore, the integrated chip of the present disclosure can improve the heat dissipation performance of a typical integrated chip.

FIG. 1 illustrates a cross-sectional view 100 of a partial embodiment of an integrated wafer including an opening 128 disposed in a first IMD structure 119 .

As shown in the cross-sectional view 100 of FIG. 1 , the integrated chip includes a substrate 102 . The substrate 102 includes any type of semiconductor substrate (eg monocrystalline silicon/CMOS bulk, germanium (Ge), silicon germanium (SiGe), III-V semiconductor, semiconductor-on-insulator, etc.). In some embodiments, the substrate 102 is a semiconductor-on-insulator substrate (such as silicon-on-insulator). In these embodiments, the substrate 102 may include a device layer 104 , an insulating layer 106 , and a handling layer 108 . The device layer 104 is disposed over the insulating layer 106 and the handle layer 108 . The insulating layer 106 is vertically disposed between the handle layer 108 and the device layer 104 .

The device layer 104 is a semiconductor material. The semiconductor material may be or include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), other semiconductor materials, or combinations thereof. In some embodiments, the device layer 104 is silicon (Si). In a further embodiment, the device layer 104 is monocrystalline silicon.

A handle layer 108 is disposed below both the insulating layer 106 and the device layer 104 . The handle layer 108 may be or may include a semiconductor material (eg, silicon, germanium, monocrystalline silicon, polycrystalline silicon, etc.), a doped semiconductor material (eg, doped silicon, doped germanium, etc.), a metal (eg, copper (Cu), aluminum ( Al), tungsten (W), gold (Au), silver (Ag), platinum (Pt), etc.) or similar.

An insulating layer 106 vertically separates the handle layer 108 from the device layer 104 . The insulating layer 106 electrically isolates the device layer 104 from the handle layer 108 . The insulating layer 106 may be or include, for example, an oxide (eg, silicon dioxide (SiO ₂ )), a nitride (eg, silicon nitride (SiN)), an oxynitride (eg, silicon oxynitride (SiON)), a low-k dielectric Dielectric materials (such as dielectric materials with a dielectric constant less than about 3.9), high-k dielectric materials (such as dielectric materials with a dielectric constant greater than about 3.9 such as hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide ( HfSiO) or similar), undoped silicate glass (silicate glass; USG), doped silicon dioxide (such as carbon-doped silicon dioxide), borosilicate glass (borosilicate glass; BSG), phosphorus Silicate glass (phosphosilicate glass; PSG), boron-doped phosphosilicate glass (BPSG), fluorosilicate glass (fluorosilicate glass; FSG), spin-on glass (spin-on glass; SOG) ), other dielectric materials or a combination of the above.

The first semiconductor device 110 (eg, insulated gate field-effect transistors (IGFET)) is disposed on/over the substrate 102 . In some embodiments, the first semiconductor device 110 is disposed on/over the device layer 104 . For example, the first semiconductor device 110 includes a pair of source/drain regions 112 , a gate dielectric 114 and a gate electrode 116 . A pair of source/drain regions 112 are regions of the device layer 104 having a first doping type (eg, n-type).

A gate dielectric 114 is disposed above the device layer 104 and between the source/drain regions of the pair of source/drain regions 112 . Gate electrode 116 covers gate dielectric 114 . In some embodiments, the gate dielectric 114 and the gate electrode 116 are collectively referred to as a gate stack. In some embodiments, the gate electrode 116 is or includes polysilicon. In these embodiments, the gate dielectric 114 may be or include, for example, an oxide such as silicon dioxide (SiO ₂ ). In other embodiments, the gate electrode 116 may be or include a metal such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt ( Co) or similar. In these embodiments, gate dielectric 114 may be or include a high-k dielectric material such as hafnium oxide (HfO), tantalum oxide (TaO), hafnium silicon oxide (HfSiO), tantalum hafnium oxide (HfTaO), Aluminum (AlO), Zirconia (ZrO), or similar.

An interlayer dielectric (interlayer dielectric; ILD) structure 118 is disposed above both the first semiconductor device 110 and the substrate 102 . The ILD structure 118 includes one or more stacked ILD layers, which may respectively include low-k dielectric materials (eg, dielectric materials with a dielectric constant less than about 3.9), oxides (eg, silicon dioxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiON)), undoped silicate glass (USG), doped silicon dioxide (such as carbon doped silicon dioxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG ) or similar. In some embodiments, the ILD structure 118 is a single ILD layer.

A first intermetal dielectric (IMD) structure 119 is disposed over both the IMD structure 118 and the substrate 102 . The first IMD structure 119 includes one or more stacked IMD layers, which may respectively include low-k dielectric materials (such as dielectric materials with a dielectric constant less than about 3.9), oxides (such as two Silicon oxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiON)), undoped silicate glass (USG), doped dioxide Silicon (e.g. carbon-doped silica), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on type glass (SOG) or similar.

The interconnection structure 120 (eg, a metal interconnection) is disposed (eg, embedded) in the ILD structure 118 and the first IMD structure 119 . The interconnection structure 120 is disposed above the substrate 102 . The interconnection structure 120 includes a plurality of conductive contacts 122 (such as metal contacts), a plurality of conductive lines 124 (such as metal wires), and a plurality of conductive vias 126 (such as metal vias). For the clarity of the illustration, only a part of the plurality of conductive contacts 122 , a part of the plurality of conductive lines 124 , and a part of the plurality of conductive vias 126 are marked in the figure. The interconnect structure 120 is configured to provide electrical connections between devices in the integrated chip. That is, a plurality of conductive lines 124, a plurality of conductive vias 126, and a plurality of conductive contacts 122 are electrically coupled together in a predetermined manner and arranged in an integrated chip to provide electrical connections between various devices. .

The conductive contact 122 is disposed in the ILD structure 118 . The conductive contact 122 extends through the ILD structure 118 to contact the pair of source/drain regions 112 and the gate electrode 116 . In some embodiments, the plurality of conductive contacts 122 may be or include, for example, tungsten (W), copper (Cu), aluminum (Al), or the like.

A plurality of conductive lines 124 and a plurality of conductive vias 126 are disposed above the conductive contacts 122 and alternately alternately from the conductive contacts 122 to the top surface of the first IMD structure 119 . In some embodiments, the plurality of conductive lines 124 and the plurality of conductive vias 126 may be or include, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt) or the like thing.

The opening 128 is disposed in the first IMD structure 119 . The sidewalls 119s of the first IMD structure 119 respectively at least partially define the sidewalls of the opening 128 . For example, the first sidewall 119s ₁ of the sidewall 119s of the first IMD structure 119 at least partially defines the first sidewall of the opening 128; the second sidewall of the sidewall 119s of the first IMD structure 119 119s ₂ , at least partially defining the second sidewall of the opening 128, and so on. In some embodiments, the bottom surface of the opening 128 (eg, the bottommost surface of the opening 128 ) is defined by the top surface of the first IMD structure 119 .

The opening 128 covers at least a portion of the first semiconductor device 110 . For example, in some embodiments, opening 128 covers gate electrode 116 (and gate dielectric 114 ). In a further embodiment, the opening 128 covers the gate electrode 116 (and the gate dielectric 114 ) and at least one source/drain region of the pair of source/drain regions 112 . In other embodiments, the opening 128 covers at least one source/drain region of the pair of source/drain regions 112 . In these embodiments, the opening 128 may cover at least a source/drain region of the pair of source/drain regions 112 and at least a portion of the gate electrode 116 (and at least a portion of the gate dielectric 114 ). Because the opening 128 covers at least a portion of the first semiconductor device 110 , thermal energy generated by the first semiconductor device 110 can be efficiently dissipated from the first semiconductor device 110 (eg, from the first semiconductor device 110 to the atmosphere). Therefore, the integrated chip of the present disclosure has good heat dissipation performance (eg, high dissipation of heat generated by semiconductor devices).

FIG. 2 illustrates a simplified top view 200 of a partial embodiment of the integrated chip of FIG. 1 . The simplified top view 200 of FIG. 2 is "simplified" in that, in the simplified top view 200 of FIG. Interlayer dielectric structure 118 .

As shown in the top view 200 of FIG. 2 , the opening 128 has a perimeter 128p. The perimeter 128p of the opening 128 is defined by the sidewalls 119s of the first IMD structure 119 . For example, the perimeter 128p of the opening 128 is defined by the first sidewall 119s ₁ of the first IMD structure 119 , the second sidewall 119s ₂ of the first IMD structure 119 , the first IMD structure The third sidewall 119s ₃ of the first IMD structure 119 and the fourth sidewall 119s ₄ of the first IMD structure 119 are defined.

In some embodiments, the perimeter 128p of the opening 128 may have a square shape. It should be understood that the perimeter 128p of the opening 128 is not limited to a square shape, but may have other geometric shapes. For example, the perimeter 128p of the opening 128 can be rectangular, circular, elliptical, oblong, triangular, other geometric shapes, or combinations thereof. In some embodiments, as shown in the top view 200 of FIG. 2 , the perimeter 128 p of the opening 128 is defined by four of the sidewalls 119 s of the first IMD structure 119 . In addition to being defined by four of the sidewalls 119s of the first IMD structure 119, it should be understood that the perimeter 128p of the opening 128 may be connected by any number of sidewalls of the first IMD structure 119. The closed loop formed together is defined.

As also shown in the top view 200 of FIG. 2 , the opening 128 covers a portion of the first semiconductor device 110 . In some embodiments, a portion of the first semiconductor device 110 is disposed laterally within the perimeter 128p of the opening 128 . The perimeter 128p of the opening 128 laterally surrounds a portion of the first semiconductor device 110 in a closed loop. For example, as shown in the top view 200 of FIG. 2, the perimeter 128p of the opening 128 extends laterally around the gate electrode 116 and the pair of source/drain regions 112 such that the gate electrode 116 and the pair of source The /drain region 112 is disposed laterally within the perimeter 128p of the opening 128 . Because a portion of the first semiconductor device 110 is laterally disposed within the perimeter 128p of the opening 128 , thermal energy generated by the first semiconductor device 110 can be more efficiently dissipated from the first semiconductor device 110 .

FIG. 3 illustrates a cross-sectional view 300 of some other embodiments of the integrated chip of FIG. 1 .

As shown in the cross-sectional view 300 of FIG. 3 , the integrated wafer includes a second IMD structure 302 . The second IMD structure 302 is vertically disposed between the ILD structure 118 and the first IMD 119 . The second IMD structure 302 includes one or more stacked IMD layers, which may respectively include low-k dielectric materials (such as dielectric materials with a dielectric constant less than about 3.9), oxides (such as two Silicon oxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiON)), undoped silicate glass (USG), doped dioxide Silicon (e.g. carbon-doped silica), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on type glass (SOG) or similar. In some embodiments, the second IMD structure 302 is a single IMD layer. The interconnection structure 120 is disposed (eg, embedded) in the second IMD structure 302 .

In some embodiments, the third IMD structure 304 is vertically disposed between the second IMD structure 302 and the first IMD structure 119 . In these embodiments, the top surface of the third IMD structure 304 may define the bottom surface of the opening 128 (eg, the bottommost surface of the opening 128 ). In other embodiments, the third IMD structure 304 may be omitted. In these embodiments, the top surface of the second IMD structure 302 may define the bottom surface of the opening 128 (eg, the bottommost surface of the opening 128 ). The third IMD structure 304 includes one or more stacked IMD layers, which may respectively include low-k dielectric materials (such as dielectric materials with a dielectric constant less than about 3.9), oxides (such as two Silicon oxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiON)), undoped silicate glass (USG), doped dioxide Silicon (e.g. carbon-doped silica), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on type glass (SOG) or similar. In some embodiments, the third IMD structure 304 is a single IMD layer. The interconnection structure 120 is disposed (eg, embedded) in the third IMD structure 304 .

The plurality of conductive lines 124 are disposed in the plurality of conductive layers 306 (eg, the plurality of metal layers). The plurality of conductive layers 306 includes N conductive layers, where N is any integer greater than or equal to 1. For example, as shown in the cross-sectional view 300 of FIG. 3 , the plurality of conductive layers 306 includes 4 conductive layers (eg, N is equal to 4). A plurality of conductive layers 306 extend laterally through the first IMD structure 119 and the second IMD structure 302 . For example, a first conductive layer 306 _N-3 (eg, metal layer 1 ) of the plurality of conductive layers 306 extends laterally through the second IMD structure 302 , and a second conductive layer of the plurality of conductive layers 306 306 _N-2 (such as metal layer 2 ) extends laterally through the first IMD structure 119 , and the third conductive layer 306 _{N- 1} (such as metal layer 3 ) of the plurality of conductive layers 306 extends laterally through the first IMD structure 119 . An IMD structure 119 , and a fourth conductive layer 306 _N (eg, the metal layer 4 ) of the plurality of conductive layers 306 extends laterally through the first IMD structure 119 . In some embodiments, the plurality of conductive layers 306 extend laterally through the third IMD structure 304 . In other embodiments, the plurality of conductive layers 306 may not extend laterally through the third IMD structure 304 . In a further embodiment, the Nth conductive layer (for example, the fourth conductive layer 306 _N ) of the plurality of conductive layers 306 is the uppermost conductive layer of the plurality of conductive layers 306 .

The plurality of conductive wires 124 includes M groups of conductive wires, wherein M is any integer greater than or equal to 1. For example, as shown in the cross-sectional view 300 of FIG. 3 , the plurality of conductive wires 124 includes 4 groups of conductive wires (for example, M is equal to 4). Each of the M sets of conductive lines includes one or more plurality of conductive lines 124 . Each of the plurality of conductive layers 306 includes one of M groups of conductive lines. For example, as shown in the cross-sectional view ₃₀₀ of FIG _. 306 _N-2 includes the second group of conductive lines 124 _M-2 , the third conductive layer 306 _N-1 in the plurality of conductive layers 306 includes the third group of conductive lines 124 _M-1 , and the third group of conductive lines 306 in the plurality of conductive layers 306 The fourth conductive layer _306N includes a fourth set of conductive lines _124M .

The plurality of conductive layers 306 are disposed on top of each other. For example, the second conductive layer 306N _-2 is disposed above the first conductive layer 306N _-3 , the third conductive layer _306N-1 is disposed above the second conductive layer 306N _-2 , and the fourth conductive layer _306N It is disposed on the third conductive layer 306 _N-1 . The plurality of conductive vias 126 vertically extend between the plurality of conductive layers 306 and electrically couple the plurality of conductive lines 124 of the plurality of conductive layers 306 together in a predetermined manner. For example, a first group of the plurality of conductive vias 126 extends vertically between the first conductive layer 306N _-3 and the second conductive layer 306N _-2 , and connects the first conductive vias in a predetermined manner. The set of conductive lines _124M-3 is electrically coupled to the second set of conductive lines _124M-2 ; the second set of conductive vias in the plurality of conductive vias 126 are in the second conductive layer 306N _-2 and the third conductive layer 306 _N-1 extends vertically and electrically couples the second set of conductive lines 124 _{M- 2} to the third set of conductive lines 124 _M-1 in a predetermined manner, and so on.

As shown in the cross-sectional view 300 of FIG. 3 , the first passivation layer 308 is disposed over the first IMD structure 119 , the interconnect structure 120 and the substrate 102 . The first passivation layer 308 may be or include, for example, oxides (such as silicon dioxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiO _{X NY} ) ), some other passivation materials or a combination of the above. In some embodiments, the material of the first passivation layer 308 is different from that of the first IMD structure 119 . In a further embodiment, the first passivation layer 308 has a planar top surface.

The sidewalls 119 s of the first IMD structure 119 and the sidewalls 308 s of the first passivation layer 308 at least partially define the sidewalls of the opening 128 . For example, the first sidewall 119s ₁ of the first IMD structure 119 and the first sidewall 308s ₁ of the sidewalls 308s of the first passivation layer 308 at least partially define the first sidewall of the opening 128 ; and the first The second sidewall 119s ₂ of the IMD structure 119 and the second sidewall 308s ₂ of the sidewalls 308s of the first passivation layer 308 at least partially define the second sidewall of the opening 128 . In some embodiments, the first sidewall 119s ₁ of the first IMD structure 119 is aligned (eg, aligned) with the first sidewall 308s ₁ of the first passivation layer 308 . In a further embodiment, the second sidewall 119s ₂ of the first IMD structure 119 is aligned (eg, aligned) with the second sidewall 308s ₂ of the first passivation layer 308 .

The plurality of conductive lines 124 are separated from the opening 128 . More specifically, the plurality of conductive lines 124 are separated from the sidewalls of the opening 128 and the bottom surface of the opening 128 . In a further embodiment, the second set of conductive lines 124 _M−2 , the third set of conductive lines 124 _M−1 , and the fourth set of conductive lines 124 _M are laterally separated from the sidewall of the opening 128 . In a further embodiment, the first set of conductive lines _{124M- 3} are vertically separated from the sidewall of the opening 128 .

In some embodiments, the plurality of conductive vias 126 are separated from the opening 128 . In a further embodiment, the plurality of conductive contacts 122 are spaced apart from the opening 128 . In a further embodiment, the internal connection structure 120 is separated from the opening 128 (for example, the plurality of conductive lines 124 , the plurality of conductive vias 126 and the plurality of conductive contacts 122 are separated from the opening 128 ).

As also shown in the cross-sectional view 300 of FIG. Part of the plurality of conductive vias 126 is disposed on the first side (eg, the right side) of the opening 128 and embedded in the first IMD structure 119 . Further, portions of the plurality of conductive lines 124 and portions of the plurality of conductive vias 126 define a second set 312 of conductive features of the interconnect structure 120, wherein the portions of the plurality of conductive lines 124 and portions of the plurality of conductive vias define the second set 312 of conductive features of the interconnect structure 120. The hole 126 is disposed on a second side (relative to the first side) (eg, the left side) of the opening 128 and is embedded in the first IMD structure 119 . In some embodiments, the first set of conductive features 310 is electrically coupled to the second set of conductive features 312 through the third set of conductive features 314 of the interconnect structure 120 . The third set of conductive features 314 includes a portion of the plurality of conductive lines 124 of the first group of conductive lines 124M _-3 .

FIG. 4 illustrates a simplified top view 400 of a partial embodiment of the integrated chip of FIG. 3 . The simplified top view 400 of FIG. 4 is "simplified" in that, in the simplified top view 400 of FIG. structure 304 , a portion of interconnect structure 120 , and a portion of ILD structure 118 .

As shown in the top view 400 of FIG. 4 , the perimeter 128p of the opening 128 is defined by the sidewalls 308s of the first passivation layer 308 . For example, the perimeter 128p of the opening 128 is composed of the first sidewall 308s ₁ of the first passivation layer 308 , the second sidewall 308s ₂ of the first passivation layer 308 , the third sidewall 308s ₃ of the first passivation layer 308 , the first passivation layer A fourth side wall 308s ₄ of 308 is defined. Although not shown in the top view 400 of FIG. 4 , it should be understood that the perimeter 128p of the opening 128 is defined by both the sidewalls 308s of the first passivation layer 308 and the sidewalls 119s of the first IMD structure 119 .

FIG. 5 shows a cross-sectional view 500 of some other embodiments of the integrated chip of FIG. 1 .

As shown in the cross-sectional view 500 of FIG. 5, one or more input/output (I/O) structures 502 (eg, pads, solder bumps, etc.) are disposed in the first passivation layer 308 and the first IMD structure. 119 above. In some embodiments, one or more input/output (I/O) structures 502 are at least partially disposed over the first passivation layer 308 . One or more upper conductive vias 504 are disposed in the first passivation layer 308 and electrically couple the input/output (I/O) structure 502 to the interconnection structure 120 . Input/output (I/O) structures 502 and upper conductive vias 504 are or include, for example, copper (Cu), aluminum (Al), aluminum copper (AlCu), tungsten (W), gold (Au), silver (Ag ), lead (Pb), tin (Sn), zinc (Zn), antimony (Sb), other conductive materials or a combination of the above.

As shown in the cross-sectional view 500 of FIG. 5 , the first top surface _304u1 of the third IMD structure 304 defines the bottom surface of the opening 208 (eg, the bottommost surface of the opening 208 ). The first top surface 304u ₁ of the third IMD structure 304 is vertically disposed between the second top surface 304u ₂ of the third IMD structure 304 and the substrate 102 . In some embodiments, the first top surface 304u ₁ of the third IMD structure 304 is laterally disposed between two portions of the second top surface 304u ₂ of the third IMD structure 304 . In a further embodiment, the second top surface 304u ₂ of the third IMD structure 304 may laterally surround the first top surface 304u ₁ of the third IMD structure 304 .

FIG. 6 shows a cross-sectional view 600 of some other embodiments of the integrated chip of FIG. 5 .

As shown in the cross-sectional view 600 of FIG. 6 , the second passivation layer 602 is disposed above the first passivation layer 308 . In some embodiments, the second passivation layer 602 is disposed above the upper conductive via 504 . In a further embodiment, the input/output (I/O) structure 502 is at least partially disposed in the second passivation layer 602 . The second passivation layer 602 may be or may include, for example, an oxide (such as silicon dioxide (SiO ₂ )), a nitride (such as silicon nitride (SiN)), an oxynitride (such as silicon oxynitride (SiO _{X NY} ) ), other passivation materials or a combination of the above. In some embodiments, the material of the second passivation layer 602 is different from that of the first IMD structure 119 and/or the first passivation layer 308 . In a further embodiment, the second passivation layer 602 has a flat top surface.

The sidewalls 119 s of the first IMD structure 119 , the sidewalls 308 s of the first passivation layer 308 , and the sidewalls 602 s of the second passivation layer 602 at least partially define the sidewalls of the opening 128 . For example, the first sidewall 119s ₁ of the first IMD structure 119 , the first sidewall 308s ₁ of the first passivation layer 308 , and the first sidewall 602s ₁ of the sidewall 602s of the second passivation layer 602 are at least partially The first sidewall of the opening 128 is defined, and the second sidewall 119s ₂ of the first IMD structure 119 , the second sidewall 308s ₂ of the first passivation layer 308 and the second sidewall 602s of the second passivation layer 602 Sidewall 602s ₂ at least partially defines a second sidewall of opening 128 .

As also shown in cross-sectional view 600 of FIG. 6 , one or more etch stop layers 604 are disposed over substrate 102 . For example, the first etch stop layer 604 a , the second etch stop layer 604 b and the third etch stop layer 604 c are disposed on the substrate 102 . The interconnection structure 120 is partially disposed in the etch stop layer 604 (eg, the plurality of conductive vias 126 vertically extend through the etch stop layer 604 ). The etch stop layer 604 is disposed between (and/or in) the first IMD structure 119 , the second IMD structure 302 and the third IMD structure 304 . For example, the first etch stop layer 604a is disposed between the third IMD structure 304 and the first IMD structure 119, and the second etch stop layer 604b and the third etch stop layer 604c are disposed between In the first IMD structure 119 . The etch stop layer 604 can be or include, for example, an oxide (eg, silicon dioxide (SiO ₂ )), a nitride (eg, silicon nitride (SiN)), an oxynitride (eg, silicon oxynitride (SiO _{X NY} )). , carbide (such as silicon carbide (SiC)), other dielectric materials or a combination of the above.

Sidewalls of etch stop layer 604 may at least partially define sidewalls of opening 128 . For example, the sidewalls 604bs of the second etch stop layer 604b and the sidewalls 604cs of the third etch stop layer 604c partially define the sidewalls of the opening 128 . More specifically, both the first sidewall 604bs1 of the sidewalls 604bs of the second _etch stop layer 604b and the first sidewall 604cs1 of the sidewalls 604cs of the third etch stop layer 604c partially define the _first sidewall of the opening 128. and the second sidewall 604bs ₂ of the sidewalls 604bs of the second etch stop layer 604b and the second sidewall 604cs ₂ of the sidewalls 604cs of the third etch stop layer 604c partially define the second sidewall of the opening 128. side wall. In some embodiments, the top surface of one of the etch stop layers 604 defines the bottom surface of the opening 128 . For example, the top surface of the first etch stop layer 604 a defines the bottom surface of the opening 128 .

Although only three etch stop layers 604 are shown in FIG. 6 , it should be understood that a bulk wafer may include any number of etch stop layers disposed over the substrate 102 . And it should be understood that although FIG. 6 only shows two passivation layers (eg, the first passivation layer 308 and the second passivation layer 602 ), any number of passivation layers may be disposed on the substrate 102 . It should also be understood that any number of etch stop and passivation layers.

FIG. 7 illustrates a cross-sectional view 700 of some other embodiments of the integrated chip of FIG. 6 .

As shown in the cross-sectional view 700 of FIG. 7 , the top surface of one of the etch stop layers 604 may define the bottom surface of the opening 128 . For example, the first top surface 604au ₁ of the first etch stop layer 604 a defines the bottom surface of the opening 128 . The first top surface 604au ₁ of the first etch stop layer 604 a is vertically disposed between the second top surface 604 au ₂ of the first etch stop layer 604 a and the substrate 102 . In some embodiments, the first top surface 604au ₁ of the first etch stop layer 604a is laterally disposed between two portions of the second top surface 604au ₂ of the first etch stop layer 604a. In a further embodiment, the second top surface 604au ₂ of the first etch stop layer 604a may laterally surround the first top surface 604au ₁ of the first etch stop layer 604a.

FIG. 8 illustrates a cross-sectional view 800 of some other embodiments of the integrated chip of FIG. 3 .

As shown in the cross-sectional view 800 of FIG. 8 , the first well region 802 is disposed in the substrate 102 . In some embodiments, the first well region 802 is disposed in the device layer 104 . The first well region 802 is a region of the device layer 104 having a second doping type (eg, p-type) opposite to the first doping type (eg, n-type). The pair of source/drain regions 112 is disposed in the first well region 802 .

The second well region 804 is disposed in the substrate 102 . In some embodiments, the second well region 804 is disposed in the device layer 104 . The second well region 804 is a region of the device layer 104 having the first doping type. The first well region 802 is at least partially disposed in the second well region 804 .

The first isolation structure 806 is disposed in the substrate 102 . In some embodiments, the first isolation structure 806 is disposed in the device layer 104 . The first isolation structure 806 is configured to electrically isolate the first semiconductor device 110 from other devices (not shown in the figure) of the integrated wafer. The first isolation structure 806 may have angled sidewalls. In other embodiments, the sidewalls of the first isolation structure 806 may be substantially straight (eg, vertical). In some embodiments, the first isolation structure 806 laterally surrounds the first semiconductor device 110 . In some embodiments, the first isolation structure 806 may be or include, for example, an oxide (such as silicon dioxide (SiO ₂ )), a nitride (such as silicon nitride (SiN)), an oxynitride (such as silicon oxynitride (SiON)), carbides (such as silicon carbide (SiC)), other dielectric materials, or combinations of the above. In some embodiments, the first isolation structure 806 is called a shallow trench isolation (STI) structure.

FIG. 9 illustrates a simplified top view 900 of a partial embodiment of the integrated chip of FIG. 8 . The simplified top view 900 of FIG. 9 is "simplified" in that, in the simplified top view 900 of FIG. structure 304 , a portion of interconnect structure 120 , and a portion of ILD structure 118 .

As shown in the top view 900 of FIG. 9 , the first well region 802 has a perimeter 802p (eg, an outer perimeter). The perimeter 802p of the first well region 802 is shown phantom (through dashed lines) in the top view 900 of FIG. 9 . In some embodiments, the perimeter 128p of the opening 128 laterally surrounds the perimeter 802p of the first well region 802 . It should be appreciated that the second well section 804 has an inner perimeter that corresponds to the perimeter 802p of the first well section 802 . Accordingly, it should also be understood that in some embodiments, the perimeter 128p of the opening 128 laterally surrounds the inner perimeter of the second well region 804 . Although not shown in the top view 900 of FIG. 9 , it should be understood that the perimeter 128p of the opening 128 may be disposed laterally between the inner perimeter of the second well 804 and the outer perimeter of the second well 804 .

As also shown in the top view 900 of FIG. 9 , the first isolation structure 806 has an inner perimeter 806ip and an outer perimeter 806op. The inner perimeter 806ip of the first isolation structure 806 and the outer perimeter 806op of the first isolation structure 806 are shown virtually (through dashed lines) in the top view 900 of FIG. 9 . In some embodiments, the perimeter 128p of the opening 128 laterally surrounds the inner perimeter 806ip of the first isolation structure 806 . In a further embodiment, the perimeter 128p of the opening 128 is disposed laterally between the inner perimeter 806ip of the first isolation structure 806 and the outer perimeter 806op of the first isolation structure 806 . In other embodiments, the perimeter 128p of the opening 128 laterally surrounds both the inner perimeter 806ip of the first isolation structure 806 and the outer perimeter 806op of the first isolation structure 806 .

FIG. 10 shows a cross-sectional view 1000 of some other embodiments of the integrated chip of FIG. 8 .

As shown in the cross-sectional view 1000 of FIG. 10 , the third well region 1002 is disposed in the device layer 104 . The third well region 1002 is a region of the device layer 104 with a second doping type (eg, p-type). A fourth well region 1004 is also disposed in the device layer 104 . The fourth well region 1004 is a region of the device layer 104 with the first doping type (eg, n-type).

A second semiconductor device 1006 (such as a double-diffused metal oxide semiconductor field-effect transistor (DMOS)) is disposed on/over the device layer 104 . The second semiconductor device 1006 has a drain region 1008 . The drain region 1008 is a region of the device layer 104 having the first doping type. The drain region 1008 is disposed in the fourth well region 1004 . A first one of the plurality of conductive contacts 122 is electrically coupled to the drain region 1008 . The second semiconductor device 1006 also includes a source region 1010 , a body contact region 1012 , a gate dielectric 1014 and a gate electrode 1016 . The source region 1010 is a region of the device layer 104 having a first doping type. The source region 1010 is disposed in the third well region 1002 . The body contact region 1012 is a region of the device layer 104 having the second doping type. The body contact region 1012 is disposed in the third well region 1002 . A second one of the plurality of conductive contacts 122 is electrically coupled to both the source region 1010 and the body contact region 1012 . A gate dielectric 1014 is disposed above the device layer 104 and laterally between the source region 1010 and the drain region 1008 . Gate electrode 1016 covers gate dielectric 1014 . A third one of the plurality of conductive contacts 122 is electrically coupled to the gate electrode 1016 .

In some embodiments, the second isolation structure 1018 is disposed in the device layer 104 . The second isolation structure 1018 is laterally disposed between the drain region 1008 and the gate electrode 1016 . In some embodiments, the gate dielectric 1014 (and the gate electrode 1016 ) may partially cover the second isolation structure 1018 . The second isolation structure 1018 may have angled sidewalls. In other embodiments, the sidewalls of the second isolation structure 1018 may be substantially straight (eg, vertical). In some embodiments, the second isolation structure 1018 may be or include, for example, oxides (such as silicon dioxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiON)), carbides (such as silicon carbide (SiC)), other dielectric materials, or combinations of the above. In a further embodiment, the second isolation structure 1018 may be called a shallow trench isolation structure. In a further embodiment, the second isolation structure 1018 is a part of the first isolation structure 806 .

The third isolation structure 1020 is disposed in the substrate 102 . In some embodiments, the third isolation structure 1020 is disposed in the device layer 104 . The third isolation structure 1020 vertically extends to the insulating layer 106 through the device layer 104 . In some embodiments, the third isolation structure 1020 vertically extends to the processing layer 108 through the device layer 104 and the insulating layer 106 . In a further embodiment, the third isolation structure 1020 extends vertically through the first isolation structure 806 .

The third isolation structure 1020 may have angled sidewalls. In other embodiments, the sidewalls of the third isolation structure 1020 may be substantially straight (eg, vertical). In some embodiments, the third isolation structure 1020 laterally surrounds the second semiconductor device 1006 . In some embodiments, the third isolation structure 1020 may be or include, for example, oxides (such as silicon dioxide (SiO ₂ )), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiON)), carbides (such as silicon carbide (SiC)), other dielectric materials, or combinations of the above. In some embodiments, the third isolation structure 1020 is called a deep trench isolation (deep trench isolation; DTI).

FIG. 11 illustrates a simplified top view 1100 of a partial embodiment of the integrated chip of FIG. 10 . The simplified top view 1100 of FIG. 11 is "simplified" in that, in the simplified top view 1100 of FIG. structure 304 , a portion of interconnect structure 120 , and a portion of ILD structure 118 .

As shown in the top view 1100 of FIG. 11 , the perimeter 128p of the opening 128 covers and aligns (eg, is center-aligned and mid-aligned) with the layout of the third isolation structure 1020 . Furthermore, the third isolation structure 1020 has an inner perimeter 1020ip and an outer perimeter 1020op. The outer perimeter 1020op of the third isolation structure 1020 is shown phantom (through dashed lines) in the top view 1100 of FIG. 11 .

In some embodiments, the perimeter 128p of the opening 128 laterally surrounds the inner perimeter 1020ip of the third isolation structure 1020 . In a further embodiment, the perimeter 128p of the opening 128 is disposed laterally between the inner perimeter 1020ip of the third isolation structure 1020 and the outer perimeter 1020op of the third isolation structure 1020 . In other embodiments, the perimeter 128p of the opening 128 laterally surrounds both the inner perimeter 1020ip of the third isolation structure 1020 and the outer perimeter 1020op of the third isolation structure 1020 .

Also shown in the top view 1100 of FIG. 11 , the second isolation structure 1018 is a part of the first isolation structure 806 . In addition, the second isolation structure 1018 has a first sidewall 1018sw ₁ and a second sidewall 1018sw ₂ opposite to the first sidewall 1018sw ₁ . The perimeter 128p of the opening 128 may laterally surround both the first sidewall 1018sw ₁ of the second isolation structure 1018 and the second sidewall 1018sw ₂ of the second isolation structure 1018 .

FIG. 12 illustrates a perspective view 1200 of a partial embodiment of the integrated chip of FIG. 6 .

As shown in the perspective view 1200 of FIG. 12 , the opening 128 is disposed in the area 1202 of the integrated wafer. More specifically, the sidewalls and the bottom surface of the opening 128 are disposed within the region 1202 . The region 1202 is disposed within one or more of the first IMD structure 119 , the second IMD structure 302 and the third IMD structure 304 . In some embodiments, region 1202 is disposed within first passivation layer 308 (and second passivation layer 602 ) and within one or more of one or more etch stop layers 604 . For example, as shown in the perspective view 1200 of FIG. 12, the region 1202 is disposed within the first IMD structure 119, the third IMD structure 304, the first passivation layer 308, and the third etch stop layer 604c. . Region 1202 has a length, width and height. The length of region 1202 is greater than the length of opening 128 . The width of region 1202 is greater than the width of opening 128 . The height of region 1202 is greater than the height of opening 128 .

FIG. 13 illustrates a cross-sectional view 1300 of a partial embodiment of the integrated chip of FIG. 12 . The cross-sectional view 1300 of FIG. 13 is taken along line A-A in FIG. 12 . The cross-sectional view 1300 of FIG. 13 depicts only the features of the integrated wafer of FIG. 12 , which are located above the second IMD structure 302 .

As shown in cross-sectional view 1300 of FIG. 13 , region 1202 is at least partially defined by the area of the built-up wafer where no conductive features of interconnect structure 120 are disposed. For example, as shown in the cross-sectional view 1300 of FIG. 13 , the interconnection structure 120 has no conductive features (eg, the plurality of conductive lines 124 and the plurality of conductive vias 126 ) disposed in the region 1202 . In some embodiments, sides of region 1202 are defined by sides of conductive features (eg, one or more of conductive lines 124 and/or one or more of conductive vias 126 ). For example, the first side of the region 1202 is defined by the sidewall of the first conductive line (and/or the first conductive via), and the second side of the region 1202 (opposite the first side of the region 1202 ) is defined by The sidewall definition of the second conductive line (and/or the second conductive via). Additionally, the bottom side of region 1202 may be defined by the top surface of the third conductive line (and/or the third conductive via). Because interconnect structure 120 has no conductive features disposed in region 1202, and because opening 128 is disposed within region 1202, opening 128 does not adversely affect the integrated wafer (eg, does not degrade the structural integrity of interconnect structure 120). .

FIG. 14 illustrates a perspective view 1400 of some other embodiments of the integrated chip of FIG. 12 .

As shown in the perspective view 1400 of FIG. 14 , a plurality of openings 1402 a to 1402 d are disposed in the first IMD structure 119 and the first passivation layer 308 . For example, the plurality of openings 1402a to 1402d include a first opening 1402a, a second opening 1402b, a third opening 1402c and a fourth opening 1402d. In some embodiments, the plurality of openings 1402 a to 1402 d have substantially similar coverage areas (eg, the width, length, and shape of the periphery of the upper end of the openings are substantially the same). In a further embodiment, the coverage areas of the plurality of openings 1402a to 1402d may have a square shape, as shown in the perspective view 1400 of FIG. 14 . In other embodiments, the coverage areas of the plurality of openings 1402 a - 1402 d may have other geometric shapes (eg, rectangle, circle, ellipse, oblong circle, triangle, etc.). In a further embodiment, the plurality of openings 1402a-1402d have substantially similar heights (eg, depths).

The plurality of openings 1402a-1402d are laterally spaced apart from each other. The plurality of openings 1402 a - 1402 d have substantially similar features (eg, structural features) to opening 128 . Because the integrated wafer includes a plurality of openings 1402a to 1402d, the heat generated by the semiconductor devices of the integrated wafer can be dissipated more efficiently (eg, due to the larger total area of the openings in the first IMD structure 119).

The plurality of openings 1402a-1402d are disposed in the plurality of regions 1404a-1404d of the integrated wafer. For example, the first opening 1402a is disposed in the first region 1404a, the second opening 1402b is disposed in the second region 1404b, the third opening 1402c is disposed in the third region 1404c, and the fourth opening 1402d is disposed in the fourth region 1404d. Plurality of regions 1404a-1404d have substantially similar features (eg, structural features) to region 1202 .

FIG. 15 illustrates a cross-sectional view 1500 of a partial embodiment of the integrated chip of FIG. 14 .

As shown in the cross-sectional view 1500 of FIG. 15 , a plurality of semiconductor devices 1502 a - 1502 b (eg, insulated gate field effect transistors) are disposed on/over the device layer 104 . For example, the third semiconductor device 1502 a is disposed on/over the device layer 104 , and the fourth semiconductor device 1502 b is disposed on/over the device layer 104 . The plurality of semiconductor devices 1502 a - 1502 b may have substantially similar features to the first semiconductor device 110 and/or the second semiconductor device 1006 .

The first opening 1402a at least partially covers the third semiconductor device 1502a. The second opening 1402b at least partially covers the fourth semiconductor device 1502b. Because the first opening 1402a at least partially covers the third semiconductor device 1502a, and because the second opening 1402b at least partially covers the fourth semiconductor device 1502b, the heat energy generated by the plurality of semiconductor devices 1502a to 1502b can be dissipated more efficiently ( eg due to the opening being arranged closer to the semiconductor device).

FIG. 16 shows a cross-sectional view 1600 of some other embodiments of the integrated chip of FIG. 15 .

As shown in the cross-sectional view 1600 of FIG. 16, the first opening 1402a has a different footprint than the second opening 1402b. For example, the first opening 1402a has a first width, and the second opening 1402b has a second width greater than the first width. Accordingly, the first opening 1402a has a different footprint than the second opening 1402b. It should be understood that, in some embodiments, the first opening 1402a and the second opening 1402b may have the same width but still have different coverage areas. For example, the first width and the second width may be substantially the same, but the first opening 1402a may have a different length (and/or overall shape) than the second opening 1402b.

As also shown in the cross-sectional view 1600 of FIG. 16, the first opening 1402a has a different height than the second opening 1402b. For example, the first opening 1402a has a first height (eg, depth) and the second opening 1402b has a second height (eg, depth) smaller than the first height. Although not shown in the cross-sectional view 1600 of FIG. 16, it should be understood that in some embodiments, the bottom surface of the first opening 1402a may be defined by a first etch stop layer (eg, a second etch stop layer 604b), and the second opening 1402b The bottom surface of may be defined by a second etch stop layer (eg, third etch stop layer 604c ) that is vertically separated from the first etch stop layer. Since the first opening 1402a can have a different footprint and/or height from the second opening 1402b, the heat generated by the plurality of semiconductor devices 1502a to 1502b can be dissipated more efficiently (eg, the footprint and height of the openings 1402a to 1402d Based on the size of the corresponding regions 1404a to 1402d, the size of the regions 1404a to 1402d may be different due to the layout of the interconnection structure 120, so that not every opening 1402a to 1402d can fit into the smallest of the regions 1404a to 1404d. one of).

FIG. 17 illustrates a cross-sectional view 1700 of some other embodiments of the integrated chip of FIG. 10 .

As shown in the cross-sectional view 1700 of FIG. 17 , in some embodiments, both the first opening 1402 a and the second opening 1402 b at least partially cover the second semiconductor device 1006 . Because both the first opening 1402a and the second opening 1402b at least partially cover the second semiconductor device 1006, the heat energy generated by the second semiconductor device 1006 can be dissipated more efficiently. For example, the integrated wafer may not have one large area covering the second semiconductor device 1006 (see e.g. area 1202), but may have multiple (laterally separated from each other) smaller areas disposed on the second semiconductor device 1006 above (for example due to the layout of the interconnection structure 120 , which excludes large areas but allows multiple smaller areas). Therefore, both the first opening 1402a and the second opening 1402b at least partially cover the second semiconductor device 1006, can more efficiently dissipate the resulting semiconductor device 1006 than just one small opening (or without any large openings). thermal energy.

18-23 illustrate a series of cross-sectional views of some embodiments of a method of forming an integrated wafer, including a plurality of openings disposed in the first IMD structure 119 . Although FIGS. 18 to 23 are described with reference to a method, it should be understood that the structures shown in FIGS. 18 to 23 are not limited to the method and may exist independently of the method.

As shown in cross-sectional view 1800 of FIG. 18 , a workpiece 1802 is received. Workpiece 1802 includes substrate 102 . In some embodiments, the substrate 102 is a semiconductor-on-insulator substrate (such as silicon-on-insulator). In these embodiments, substrate 102 includes device layer 104 , insulating layer 106 , and handle layer 108 .

A plurality of semiconductor devices 1502 a - 1502 b are formed on/over the device layer 104 . For example, the third semiconductor device 1502 a and the fourth semiconductor device 1502 b are formed on/over the device layer 104 . In some embodiments, each of the plurality of semiconductor devices 1502a-1502b includes a pair of source/drain regions, a gate dielectric, and a gate electrode. An ILD structure 118 is formed over both the plurality of semiconductor devices 1502 a - 1502 b and the device layer 104 .

The first IMD structure 119 is formed over the ILD structure 118 and the plurality of semiconductor devices 1502a to 1502b. One or more etch stop layers 604 are formed over the substrate 102 and in the first IMD structure 119 . For example, the first etch stop layer 604 a and the second etch stop layer 604 b are disposed on the substrate 102 and in the first IMD structure 119 . The interconnect structure 120 is formed over the substrate 102 and in the ILD structure 118 , the first IMD structure 119 and in the one or more etch stop layers 604 . The interconnection structure 120 includes a plurality of conductive contacts 122 (such as metal contacts), a plurality of conductive lines 124 (such as metal wires), and a plurality of conductive vias 126 (such as metal vias). In some embodiments, the plurality of conductive contacts 122 , the plurality of conductive lines 124 and the plurality of conductive vias 126 are referred to as conductive features (of the interconnect structure 120 ). The plurality of semiconductor devices 1502a to 1502b, the ILD structure 118, the first IMD structure 119, one or more etch stop layers 604 and inner Connection structure 120 .

As shown in the cross-sectional view 1900 of FIG. 19 , the first passivation layer 308 is formed over the first IMD structure 119 and the interconnect structure 120 . For example, chemical vapor deposition (chemical vapor deposition; CVD), physical vapor deposition (physical vapor deposition; PVD), atomic layer deposition (atomic layer deposition; ALD), spin coating process, other deposition process or the above combined to form the first passivation layer 308 . In some embodiments, the first passivation layer 308 consists of a substantially planar top surface. In a further embodiment, the first passivation layer 308 is formed through a blanket deposition process.

As shown in the cross-sectional view 2000 of FIG. 20 , a first patterned mask layer 2002 (eg, positive/negative photoresist, hard mask, etc.) is formed over the first passivation layer 308 . The first patterned mask layer 2002 includes a first opening 2004 (eg, a first opening). The first opening 2004 at least partially covers the third semiconductor device 1502a. The first opening 2004 also covers the first portion of the first passivation layer 308 and the first portion of the first IMD structure 119 . The conductive features of the interconnect structure 120 are separated from the first portion of the first passivation layer 308 and the first portion of the first IMD structure 119 . Although not shown in the cross-sectional view 2000 of FIG. 20 , it should be understood that one or more input/output structures may be formed in/over the first passivation layer 308 prior to forming the first patterned mask layer 2002 (see e.g. Figure 5).

In some embodiments, the process of forming the first patterned mask layer 2002 includes depositing a mask layer (not shown in the figure) on the first passivation layer 308 . The masking layer can be deposited by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin-on-coating process, other deposition processes, or combinations thereof. Thereafter, the mask layer is exposed to a pattern (for example, through a lithography process such as photolithography, EUV lithography, or similar methods) and developed, thereby forming a first patterned mask layer on the first passivation layer 308 2002.

As shown in the cross-sectional view 2100 of FIG. 21 , the first opening 1402 a is formed in the first passivation layer 308 and the first IMD structure 119 . The first opening 1402a is formed and covers at least a part of the third semiconductor device 1502a. In some embodiments, the formed first opening 1402a has substantially vertical sidewalls. In a further embodiment, the first opening 1402a is formed such that the top surface of the second etch stop layer 604b defines the bottom surface of the first opening 1402a. In other embodiments, the first opening 1402a is formed such that the first top surface of the first IMD structure 119 (or other IMD structure) defines the bottom surface of the first opening 1402a.

In some embodiments, the process of forming the first opening 1402a includes using the first patterned mask layer 2002 on the first passivation layer 308, and the first passivation layer 308 and the first IMD structure 119 On, performing an etching process. The etching process selectively etches the first passivation layer 308 and the first IMD structure 119 according to the first patterned mask layer 2002 . Therefore, the etching process removes the first portion of the first passivation layer 308 and the first portion of the first IMD structure 119 , thereby forming the first opening 1402 a. In some embodiments, the etching process is stopped on the second etch stop layer 604b such that the top surface of the second etch stop layer 604b defines the bottom surface of the first opening 1402a. In a further embodiment, the etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, some other etching processes, or a combination thereof. Subsequently, in some embodiments, the first patterned mask layer 2002 is stripped.

As shown in the cross-sectional view 2200 of FIG. 22 , a second patterned mask layer 2202 (eg, positive/negative photoresist, hard mask, etc.) is formed over the first passivation layer 308 and in the first opening 1402a. The second patterned mask layer 2202 includes a second opening 2204 (eg, a second opening). The second opening 2204 at least partially covers the fourth semiconductor device 1502b.

The second opening 2204 also covers the second portion of the first passivation layer 308, the second portion of the first IMD structure 119, the first portion of the second etch stop layer 604b and the first IMD structure 119. the third part of . The second portion of the first IMD structure 119 covers the third portion of the first IMD structure 119 . The conductive features of the interconnect structure 120 are separated by the second portion of the first passivation layer 308, the second portion of the first IMD structure 119, the third portion of the first IMD structure 119, and the second etch The first portion of the stop layer 604b.

In some embodiments, forming the second patterned mask layer 2202 includes depositing a mask layer (not shown in the figure) on the first passivation layer 308 and in the first opening 1402a. The masking layer can be deposited by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin-on-coating process, other deposition processes, or combinations thereof. Subsequently, the mask layer is exposed to a pattern (for example, through a lithography process such as photolithography, EUV lithography, or similar methods) and developed, thereby forming a first passivation layer 308 above and in the first opening 1402a. Second, pattern the mask layer 2202 .

As shown in the cross-sectional view 2300 of FIG. 23 , the second opening 1402b is formed in the first passivation layer 308 , the first IMD structure 119 and the second etch stop layer 604b. The second opening 1402b is formed and covers at least a part of the fourth semiconductor device 1502b. A second opening 1402b is formed and spaced laterally from the first opening 1402a. In some embodiments, the formed second opening 1402b has substantially vertical sidewalls. In a further embodiment, the second opening 1402b is formed such that the top surface of the first etch stop layer 604a defines the bottom surface of the second opening 1402b. In other embodiments, the second opening 1402b is formed such that the second top surface of the first IMD structure 119 (or other IMD structure) defines the bottom surface of the second opening 1402b.

In some embodiments, the process of forming the second opening 1402 b includes performing a first etching process on the first passivation layer 308 and the first IMD structure 119 . With the second patterned mask layer 2202 just above the first passivation layer 308 and in the first opening 1402a, a first etching process is performed. The first etching process selectively etches the first passivation layer 308 and the first IMD structure 119 according to the second patterned mask layer 2202 . Thus, the first etch process removes the second portion of the first passivation layer 308 and the second portion of the first IMD structure 119 . In some embodiments, the first etch process stops on the second etch stop layer 604b. In a further embodiment, the first etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof.

Subsequently, a second etching process is performed on the second etching stop layer 604b. With the second patterned mask layer 2202 just above the first passivation layer 308 and in the first opening 1402a, a second etching process is performed. The second etching process selectively etches the second etch stop layer 604 b according to the second patterned mask layer 2202 . Therefore, the second etch process removes the first portion of the second etch stop layer 604b. In some embodiments, the second etch process stops on a layer of the first IMD structure 119 disposed (directly) under the second etch stop layer 604b. In a further embodiment, the second etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof.

Then, a third etching process is performed on the first IMD structure 119 . With the second patterned mask layer 2202 just above the first passivation layer 308 and in the first opening 1402a, a third etching process is performed. The third etching process selectively etches the first IMD structure 119 according to the second patterned mask layer 2202 . Therefore, the third etch process removes the third portion of the first IMD structure 119 . In some embodiments, the third etching process is stopped on the first etch stop layer 604a, so that the top surface of the first etch stop layer 604a defines the bottom surface of the second opening 1402b. In a further embodiment, the third etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof. Subsequently, in some embodiments, the second patterned mask layer 2202 is peeled off.

24-27 show a series of cross-sectional views of some other embodiments of the method of FIGS. 18-23 . Although FIGS. 24-27 are described with reference to a method, it should be understood that the structures shown in FIGS. 24-27 are not limited to the method, and may exist independently of the method.

As shown in the cross-sectional view 2400 of FIG. 24 , a third patterned mask layer 2402 (eg, positive/negative photoresist, hard mask, etc.) is formed over the first passivation layer 308 . The third patterned mask layer 2402 includes a plurality of openings 2404 a to 2404 b (eg, openings). For example, the third patterned mask layer 2402 includes a third opening 2404a (such as a first opening) and a fourth opening 2404b (such as a second opening). The third opening 2404a is laterally spaced apart from the fourth opening 2404b.

In some embodiments, the plurality of openings 2404a-2404b have substantially similar footprints. In other embodiments, the plurality of openings 2404a-2404b have different coverage areas. For example, as shown in the cross-sectional view 2400 of FIG. 24 , the third opening 2404 a has a different coverage area than the fourth opening 2404 b. In some embodiments, the plurality of openings 2404a to 2404b at least partially cover the plurality of semiconductor devices 1502a to 1502b respectively. In other embodiments, the plurality of openings 2404 a - 2404 b may at least partially cover one of the plurality of semiconductor devices 1502 a - 1502 b (see eg FIG. 17 ).

A plurality of openings 2404 a to 2404 b cover part of the first passivation layer 308 and part of the first IMD structure 119 . For example, the third opening 2404a covers the first portion of the first passivation layer 308 and the first portion of the first IMD structure 119; and the fourth opening 2404b covers the second portion of the first passivation layer 308 and the first A second portion of the IMD structure 119 . The conductive features of the interconnect structure 120 are separated from the first and second portions of the first passivation layer 308 and the first and second portions of the first IMD structure 119 .

In some embodiments, the process of forming the third patterned mask layer 2402 includes depositing a mask layer (not shown in the figure) on the first passivation layer 308 . The masking layer can be deposited by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin-on-coating process, other deposition processes, or combinations thereof. Subsequently, the mask layer is exposed to a pattern (eg, through a lithography process such as photolithography, EUV lithography, or similar methods) and developed, thereby forming a third patterned mask over the first passivation layer 308. Layer 2402.

As shown in the cross-sectional view 2500 of FIG. 25 , the fifth opening 2502 is formed in the first passivation layer 308 and the first IMD structure 119 . In some embodiments, the formed fifth opening 2502 has substantially vertical sidewalls. In a further embodiment, the fifth opening 2502 is formed such that the first top surface of the second etch stop layer 604 b defines the bottom surface of the fifth opening 2502 . In other embodiments, the fifth opening 2502 is formed such that the first top surface of the first IMD structure 119 (or other IMD structure) defines the bottom surface of the fifth opening 2502 .

As also shown in the cross-sectional view 2500 of FIG. 25 , the sixth opening 2504 is formed in the first passivation layer 308 and the first IMD structure 119 . In some embodiments, the formed sixth opening 2504 has substantially vertical sidewalls. In a further embodiment, the sixth opening 2504 is formed such that the second top surface of the second etch stop layer 604 b defines the bottom surface of the sixth opening 2504 . In other embodiments, the sixth opening 2504 is formed such that the second top surface of the first IMD structure 119 (or other IMD structure) defines the bottom surface of the sixth opening 2504 .

In some embodiments, the process of forming the fifth opening 2502 and the sixth opening 2504 includes using the third patterned mask layer 2402 on the first passivation layer 308, and between the first passivation layer 308 and the first metal On the dielectric structure 119, an etching process is performed. The etching process selectively etches the first passivation layer 308 and the first IMD structure 119 according to the third patterned mask layer 2402 . Therefore, the etching process removes the first portion and the second portion of the first passivation layer 308 and removes the first portion and the second portion of the first IMD structure 119, thereby forming the fifth opening 2502 and the sixth opening 2504 ( eg through the same etch). In some embodiments, the etching process stops on the second etch stop layer 604b. In further embodiments, the etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof.

As shown in the cross-sectional view 2600 of FIG. 26 , a fourth patterned mask layer 2602 (eg, positive/negative photoresist, hard mask, etc.) is formed over the first passivation layer 308 and in the fifth opening 2502 . In some embodiments, the fourth patterned mask layer 2602 is formed on the third patterned mask layer 2402 . In other embodiments, the third patterned mask layer 2402 is stripped before the formation of the fourth patterned mask layer 2602 .

The fourth patterned mask layer 2602 includes fifth openings 2604 (eg fifth openings). In some embodiments, the fifth opening 2604 is laterally displaced relative to the fourth opening 2404b. In these embodiments, as shown in the cross-sectional view 2600 of FIG. 26 , the fourth patterned mask layer 2602 is partially formed within the sixth opening 2504 . The fifth opening 2604 covers the second portion of the second etch stop layer 604 b and the third portion of the first IMD structure 119 . The conductive features of the interconnect structure 120 are separated from the second portion of the second etch stop layer 604 b and the third portion of the first IMD structure 119 .

In some embodiments, the process of forming the fourth patterned mask layer 2602 includes depositing a mask layer (not shown in the figure) above the first passivation layer 308 and in the fifth opening 2502 and the sixth opening 2504 . In a further embodiment, a mask layer is also deposited over the third patterned mask layer 2402 . The masking layer can be deposited by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin-on-coating process, other deposition processes, or combinations thereof. Subsequently, the mask layer is exposed to a pattern (for example, by a lithography process such as photolithography, extreme ultraviolet light lithography, or similar methods) and developed, so that the first passivation layer 308 (and the third patterned mask layer 2402 ), in the fifth opening 2502 and part of the sixth opening 2504 , a fourth patterned mask layer 2602 is formed.

As shown in the cross-sectional view 2700 of FIG. 27 , the seventh opening 2702 is formed in the first passivation layer 308 and the first IMD structure 119 . The seventh opening 2702 is formed by extending at least a portion of the depth of the sixth opening 2504 . In some embodiments, the seventh opening 2702 is formed such that the top surface of the first etch stop layer 604 a defines the bottommost surface of the seventh opening 2702 . In other embodiments, the seventh opening 2702 is formed such that the third top surface of the first IMD structure 119 (or other IMD structure) defines the bottommost surface of the seventh opening 2702 .

In some embodiments, the seventh opening 2702 is formed with a frame 2704 . The frame 2704 includes a portion of the first IMD structure 119 (and a portion of the second etch stop layer 604b ) disposed laterally between opposing sidewalls of the sixth opening 2504 (see eg FIG. 25 ). More specifically, the frame 2704 includes a portion of the first IMD structure 119 (and a portion of the second etch stop layer 604b), with the sixth opening 2504 and the fourth patterned mask layer 2602 overlying the portion (see eg Figure 26). In some embodiments, the top surface of the frame 2704 is defined by the third top surface of the second etch stop layer 604b. In other embodiments, the top surface of the frame 2704 is defined by the fourth top surface of the first IMD structure 119 (or other IMD structure). In some embodiments, the top surface of the frame 2704 may cover one or more conductive features of the interconnection structure 120 vertically disposed between the top surface of the frame 2704 and the bottommost surface of the seventh opening 2702 .

In some embodiments, the process of forming the seventh opening 2702 includes performing a first etching process on the second etch stop layer 604b. With the fourth patterned mask layer 2602 (and the third patterned mask layer 2402 ) located just above the first passivation layer 308 , in the fifth opening 2502 and part of the sixth opening 2504 , a first etching process is performed. The first etching process selectively etches the second etch stop layer 604 b according to the fourth patterned mask layer 2602 (and the third patterned mask layer 2402 ). Thus, the first etch process removes the second portion of the second etch stop layer 604b. In some embodiments, the first etching process is stopped on one layer of the first IMD structure 119, and the one layer of the first IMD structure 119 is (for example, directly) disposed on the second etch stop layer. 604b below. In a further embodiment, the first etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof.

Then, a second etching process is performed on the first IMD structure 119 . With the fourth patterned mask layer 2602 (and the third patterned mask layer 2402 ) located just above the first passivation layer 308 , in the fifth opening 2502 and part of the sixth opening 2504 , a second etching process is performed. The second etching process selectively etches the first IMD structure 119 according to the fourth patterned mask layer 2602 (and the third patterned mask layer 2402 ). Therefore, the second etching process removes the third portion of the first IMD structure 119 . In some embodiments, the second etching process is stopped on the first etch stop layer 604 a such that the top surface of the first etch stop layer 604 a defines the bottommost surface of the seventh opening 2702 . In a further embodiment, the second etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other etching processes, or a combination thereof. Subsequently, in some embodiments, the fourth patterned mask layer 2602 (and the third patterned mask layer 2402) is stripped.

By forming the seventh opening 2702 in the above method, the heat generated by the plurality of semiconductor devices 1502a to 1502b can be dissipated more effectively. For example, by forming sixth opening 2504 and then extending the depth of sixth opening 2504 to form seventh opening 2702 which may have a greater overall height (eg, overall depth). Therefore, the bottommost surface of the seventh opening 2702 can be disposed closer to the fourth semiconductor device 1502b, thereby improving the rate at which heat energy generated by the fourth semiconductor device 1502b can escape from the fourth semiconductor device 1502b.

FIG. 28 illustrates a flowchart 2800 of some embodiments of a method of forming an integrated wafer including an opening disposed in an IMD structure. It should be understood that the flow chart 2800 of FIG. 28 depicts a series of steps or situations, but does not limit the interpretation of these steps or situations. For example, some steps may occur in a different order and/or concurrently than those shown and/or described herein. In addition, not all illustrated steps need to illustrate one or more aspects or embodiments herein, and one or more steps described herein may be performed in one or more separate steps and/or stages .

In step 2802, a workpiece comprising a substrate is received, wherein a semiconductor device is disposed on the substrate, wherein an IMD structure is disposed above the substrate and the semiconductor device, and wherein a plurality of conductive features are disposed in the IMD structure and above the substrate. FIG. 18 illustrates a cross-sectional view 1800 of some embodiments corresponding to step 2802 .

In step 2804, a passivation layer is formed over the IMD structure and the plurality of conductive features. FIG. 19 illustrates a cross-sectional view 1900 of some embodiments corresponding to step 2804 .

In step 2806, an opening is formed in the passivation layer and the IMD structure, wherein the opening covers at least a portion of the semiconductor device. 20-23 illustrate a series of cross-sectional views 2000-2300 of some embodiments corresponding to step 2806. 24-27 illustrate a series of cross-sectional views 2400-2700 of some embodiments corresponding to step 2806.

In some embodiments, the integrated circuit may include a high voltage transistor disposed on the front surface of the substrate. The high voltage transistor includes a source region and a drain region separated from each other by a gate structure, and the high voltage transistor may have a breakdown voltage greater than about 20 volts. The integrated circuit includes electrodes disposed on the backside surface of the substrate. The electrodes can be configured to enhance the performance of the high voltage transistor by manipulating the electric field generated by the high voltage transistor in the substrate (eg, reducing the peak electric field). The electrode is located directly under the high voltage transistor and separated from the backside surface of the substrate by an insulating layer. By manipulating the electric field generated by the high voltage transistor, the absolute value of the breakdown voltage of the high voltage transistor can be increased. For example, the electrodes can be grounded or maintained at a suitable bias to improve performance with respect to the breakdown voltage of the high voltage transistor. In addition, a backside dielectric structure can be provided across the entire bottom surface of the electrode, wherein the backside dielectric structure is located directly below the high voltage transistor device. The backside dielectric structure may be part of a backside structure, such as an input/output structure, and may be configured to isolate electrodes from other devices and/or structures disposed on the backside surface of the substrate.

During operation of the high voltage transistor, high heat may build up in the substrate in/around the doped regions (eg, source region, drain region, well region, etc.) of the high voltage transistor. As the operating voltage of the high voltage transistor increases, the heat will increase and may cause leakage current between layers and/or delamination. The backside dielectric structure and other structures/layers are placed on the bottom surface of the electrode and are made of materials that inhibit the easy dissipation of thermal energy (such as dielectric materials), which inhibit the thermal energy generated by the high voltage transistor from IC fugitive. Therefore, since the backside dielectric structure is located directly below the high voltage transistor and is disposed across the entire bottom surface of the electrode, the integrated circuit may have poor heat dissipation performance (such as low heat energy generated by the high voltage transistor). escape). This can degrade the performance of the integrated circuit and/or can cause damage/collapse of the high voltage transistor (eg, caused by thermal runaway).

Accordingly, various embodiments of the present disclosure provide an integrated circuit with high voltage transistors for improved heat dissipation. The high voltage transistor is disposed on the front surface of the substrate. The electrodes are arranged under the high voltage transistor and separated from the backside surface of the substrate by an insulating layer. In addition, the backside dielectric structure is disposed under the electrodes. The backside dielectric structure has sidewalls defining an opening (eg, an aperture in the backside dielectric structure) directly beneath the high voltage transistor and exposing at least a portion of the bottom surface of the electrode. Because the opening is located below at least a portion of the high voltage transistor, heat generated by the high voltage transistor can be more efficiently dissipated from the high voltage transistor (e.g., by the electrodes and less dielectric under the high voltage transistor material, heat energy can escape from the high voltage transistor to the atmosphere more efficiently). To some extent, this will increase the heat dissipation performance of the integrated circuit and reduce the damage/breakdown of the high voltage transistor.

FIG. 29A shows a cross-sectional view 2900a of a partial embodiment of an integrated circuit including an opening 2905 disposed in a backside dielectric structure 2908 beneath the second semiconductor device 1006 .

As shown in cross-sectional view 2900 of FIG. 29, the integrated circuit includes a substrate 102 having a front side surface 102f and an opposite back side surface 102b. In some embodiments, the substrate 102 may be or include silicon, bulk silicon, a silicon-on-insulator substrate, other suitable semiconductor materials, or the like. The insulating layer 2904 and the conductive layer 2906 are disposed on the backside surface 102 b of the substrate 102 . The insulating layer 2904 separates the conductive layer 2906 from the substrate 102 . A backside dielectric structure 2908 is disposed on the conductive layer 2906 . In various embodiments, the conductive layer 2906 includes a metal such as copper, aluminum, tungsten, gold, silver, platinum, other metallic materials, or any combination thereof. In some embodiments, the insulating layer 2904 and the backside dielectric structure 2908 include oxide (such as silicon dioxide), silicon nitride, silicon oxynitride, undoped silicate glass, doped silicon dioxide , borosilicate glass, other dielectric materials or any combination of the above. In various embodiments, backside dielectric structure 2908 is a single continuous layer or includes two or more dielectric layers.

The first isolation structure 806 extends from the front surface 102f of the substrate 102 to a point below the front surface 102f. The first isolation structure 806 may be configured as a shallow trench isolation structure. In addition, the third isolation structure 1020 extends from the front surface 102f of the substrate 102 to the insulating layer 2904 . The third isolation structure 1020 may be configured as a deep trench isolation structure. In various embodiments, the first isolation structure 806 and the third isolation structure 1020 may be or include, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon dioxide, other dielectric materials, or any combination thereof. In addition, the second semiconductor device 1006 is disposed on/over the front surface 102 f of the substrate 102 . The first isolation structure 806 and the third isolation structure 1020 respectively laterally surround the second semiconductor device 1006 and are configured to electrically isolate the second semiconductor device 1006 from other devices disposed on/in the substrate 102 . In a further embodiment, one or more through substrate vias (TSVs) (see, eg, FIGS. 30A-30C ) are disposed in the third isolation structure 1020 and electrically coupled to the conductive layer 2906 .

In some embodiments, the second semiconductor device 1006 includes a gate structure 2910 disposed on the front surface 102f, a drain region 1008, a source region 1010, a body contact region 1012, a third well region 1002 and a fourth well region 1004 . The gate structure 2910 includes a gate electrode 1016 over the substrate 102 and a gate dielectric 1014 disposed between the gate electrode 1016 and the substrate 102 . The drain region 1008 is laterally separated from the source region 1010 by the gate structure 2910 and the second isolation structure 1018 . In some embodiments, the second isolation structure 1018 is a segment of the first isolation structure 806 . In addition, the body contact region 1012 and the source region 1010 are disposed in the third well region 1002 , and the drain region 1008 is disposed in the fourth well region 1004 .

When biased, the gate electrode 1016 is configured to generate an electric field that controls the movement of charge carriers within the third well region 1002 between the source region 1010 and the drain region 1008 . For example, in operation, a gate-to-source voltage may be selectively applied to the gate electrode 1016 relative to the source region 1010 such that in the third well region 1002 and laterally between the source region 1010 and the drain Conductive pathways are formed between regions 1008 . In some embodiments, the third well region 1002 and the base contact region 1012 respectively contain the first doping type (for example, p-type), and the fourth well region 1004, the source region 1010 and the drain region 1008 respectively contain the same doping type as the first doping type. A second doping type opposite to the first doping type (eg, n-type). The first doping type is p-type doping, the second doping type is n-type doping, or vice versa. In some embodiments, the second semiconductor device 1006 is configured as a high voltage transistor, such as a laterally diffused metal oxide semiconductor device. In further embodiments, the second semiconductor device 1006 may be any type of MOSFET, bipolar junction transistor (BJT), other suitable semiconductor devices, or the like.

At least a portion of the conductive layer 2906 directly below the second semiconductor device 1006 may be referred to as an electrode and configured to manipulate the electric field generated by the gate electrode 1016 (eg, reduce the peak electric field). To some extent, this will increase the absolute value of the breakdown voltage of the second semiconductor device 1006, thereby improving the overall performance of the integrated circuit. For example, during operation, the conductive layer 2906 can be biased at a suitable voltage to improve the breakdown voltage performance of the second semiconductor device 1006 . In addition, the conductive layer 2906 includes sidewalls that define one or more gaps disposed directly under the second semiconductor device 1006 . In various embodiments, each gap has a shape corresponding to the shape of the capping structures of the second semiconductor device 1006, such as the third well region 1002, the fourth well region 1004, the gate structure 2910, the source region 1010 And/or the shape of the drain region 1008 . Having the conductive layer 2906 with gaps of the above shape and layout can improve the uniformity of the electric field in the substrate 102 (eg further reduce the peak electric field), thereby further improving the performance of the breakdown voltage of the second semiconductor device 1006 . The gap disposed in the conductive layer 2906 is filled with a non-conductive material such as the first dielectric structure 2903 . In some embodiments, the first dielectric structure 2903 may include the same material as the insulating layer 2904 or the backside dielectric structure 2908 . In a further embodiment, the first dielectric structure 2903 is air and/or omitted such that the gap in the conductive layer 2906 is an opening exposing at least a portion of the bottom surface of the insulating layer 2904 .

The interconnection structure 120 is disposed on the front surface 102 f of the substrate 102 . In some embodiments, the interconnection structure 120 includes an interlayer dielectric structure 118, a first intermetal dielectric structure 119, a plurality of conductive contacts 122, a plurality of conductive lines 124 (such as a plurality of wires), and a plurality of conductive vias. Hole 126. The ILD structure 118 covers the front surface 102f of the substrate 102 and the second semiconductor device 1006 . The first IMD structure 119 covers the ILD structure 118 . The conductive contact 122 is disposed within the ILD structure 118 and is electrically coupled to the second semiconductor device 1006 . In addition, the conductive lines 124 and the conductive vias 126 are disposed in the first IMD structure 119 and electrically coupled to the plurality of conductive contacts 122 . The ILD structure 118 and the first IMD structure 119 may be or include, for example, a low-k dielectric material (eg, a dielectric material with a dielectric constant less than about 3.9), an oxide (eg, silicon dioxide), Silicon nitride, silicon carbide, undoped silicate glass, doped silicon dioxide, other suitable dielectric materials or any combination thereof.

The backside dielectric structure 2908 includes opposing sidewalls _{2908s 1} , 2908s ₂ that at least partially define an _opening 2905 disposed within the backside dielectric structure 2908 . In various embodiments, the top surface of opening 2905 is defined by at least a portion of the bottom surface of conductive layer 2906 and the bottom surface of first dielectric structure 2903 . The opening 2905 is located below the second semiconductor device 1006 such that the second semiconductor device 1006 is laterally separated from the sidewalls 2908s ₁ and 2908s ₂ of the backside dielectric structure 2908 . Because the opening 2905 is located below the second semiconductor device 1006 , thermal energy generated by the second semiconductor device 1006 (eg, during operation of the second semiconductor device 1006 ) can escape from the second semiconductor device 1006 more efficiently. For example, by having less material (eg, less dielectric material) beneath the conductive layer 2906 and the second semiconductor device 1006, heat is more efficiently dissipated from the second semiconductor device 1006 to the atmosphere. This increases the heat dissipation performance of the integrated circuit and reduces damage and/or breakdown of the second semiconductor device 1006 .

FIG. 29B shows a plan view 2900b of the integrated circuit of FIG. 29A taken along line A-A'. For convenience of illustration, the conductive layer 2906 , the first dielectric structure 2903 , the insulating layer 2904 , part of the substrate 102 , the third well region 1002 and the fourth well region 1004 are omitted in the plan view 2900 b of FIG. 29B .

As shown in plan view 2900b of FIG. 29B , backside dielectric structure 2908 has an inner perimeter 2908ip that defines the perimeter of opening 2905 . In various embodiments, the perimeter of the opening 2905 is defined by the four sidewalls of the backside dielectric structure 2908 . In some embodiments, the perimeter of the opening 2905 has a rectangular, square, circular, oval, or other geometric shape. The periphery of the opening 2905 laterally surrounds the second semiconductor device 1006 in a closed path. For example, gate structure 2910 , body contact region 1012 , source region 1010 and drain region 1008 are disposed laterally within the perimeter of opening 2905 . Since the second semiconductor device 1006 is laterally disposed within the periphery of the opening 2905 , heat energy generated by the second semiconductor device 1006 can be more efficiently dissipated from the second semiconductor device 1006 .

29C shows a plan view 2900c of a conductive layer 2906 facing the backside surface 102b of the substrate 102 of the integrated circuit of FIG. 29A. The plan view 2900c of FIG. 29C is taken along the line AA' of FIG. 29A, and for the convenience of illustration, the plan view 2900c of FIG. 29C omits the first dielectric structure 2903, the insulating layer 2904, part of the substrate 102, the Mitsui district 1002 and fourth well district 1004.

As shown in plan view 2900c of FIG. 29C , conductive layer 2906 has an inner perimeter 2906ip that defines the perimeter of a gap in conductive layer 2906 . In a still further embodiment, the perimeter of the gap is equal to the perimeter of the first dielectric structure (2903 in Figure 29A). Furthermore, the shape of the gap in conductive layer 2906 corresponds to the shape of source region 1010 , where the gap is located directly below source region 1010 (see, eg, FIG. 29A ).

30A shows a cross-sectional view 3000a of an alternative embodiment of the integrated circuit of FIGS. 29A to 29C , wherein a first plurality of through substrate vias 3002 laterally surround a second semiconductor device 1006, and a backside structure 3001 is disposed on the backside of the substrate 102. on the side surface 102b.

As shown in the cross-sectional view 3000a of FIG. 30A , in various embodiments, the conductive layer 2906 is electrically coupled to the first plurality of TSVs 3002 . The first plurality of TSVs 3002 extend through the third isolation structure 1020 and laterally surround the second semiconductor device 1006 . The backside structure 3001 includes a backside dielectric structure 2908 , a second plurality of through substrate vias 3004 and a plurality of contact pads 3012 . In some embodiments, the backside dielectric structure 2908 includes a first dielectric layer 3007 , a second dielectric layer 3008 and a third passivation layer 3010 . At least one TSV of the second plurality of TSVs 3004 is electrically coupled to the first plurality of TSVs 3002 via the paths of the conductive contacts 122 , the conductive lines 124 , and the conductive vias 126 . In addition, the second plurality of TSVs 3004 are electrically coupled to the plurality of contact pads 3012 . The second plurality of TSVs 3004 are separated from the conductive layer 2906 by one or more second dielectric structures 3006 . In some embodiments, the contact pads 3012 are configured to electrically couple the integrated circuit to another integrated circuit (not shown). In addition, the first dielectric layer 3007 , the second dielectric layer 3008 and the third passivation layer 3010 respectively include opposite sidewalls that are aligned and define the opening 2905 .

FIG. 30B shows a plan view 3000b of the integrated circuit of FIG. 30B, which is taken along line A-A' of the cross-sectional view 3000a of FIG. 30A. For convenience of illustration, the plan view 3000b of FIG. 30B omits the conductive layer 2906 , the first dielectric structure 2903 , the insulating layer 2904 , part of the substrate 102 , the third well region 1002 and the fourth well region 1004 .

As shown in plan view 3000b of FIG. 30B , the first plurality of TSVs 3002 may be, for example, circular and aligned with the inner perimeter 3010ip of the third passivation layer 3010 . In some embodiments, the inner perimeter 3010ip of the third passivation layer 3010 defines the perimeter of the opening 2905 .

FIG. 30C shows a plan view 3000c of the conductive layer 2906 facing the backside surface 102b of the substrate 102 of the integrated circuit in FIG. 30A. The plan view 3000c of FIG. 30C is taken along the line AA' of the cross-sectional view 3000a of FIG. 30A. For the convenience of illustration, the plan view 3000c of FIG. 30C omits the first dielectric structure 2903, the insulating layer 2904, and part of the substrate 102. , the third well area 1002 and the fourth well area 1004.

As shown in plan view 3000c of FIG. 30C , conductive layer 2906 has an inner perimeter 2906ip that defines the perimeter of a gap in conductive layer 2906 . In various embodiments, at least one TSV of the first plurality of TSVs 3002 is laterally aligned with at least a portion of the inner perimeter 2906ip of the conductive layer 2906 .

31A illustrates a cross-sectional view 3100a of a portion of an alternative embodiment of the integrated circuit of FIG. 30A , wherein a first plurality of through substrate vias 3002 extends continuously from interconnect structure 120 to a point below conductive layer 2906 . In some embodiments, each TSV of the first plurality of TSVs 3002 directly contacts two opposite sidewalls of the conductive layer 2906 .

31B illustrates a cross-sectional view 3100b of a portion of an alternate embodiment of the integrated circuit of FIG. 30A , wherein the first plurality of through-substrate vias 3002 directly contacts the bottom surface of the conductive layer 2906 . In various embodiments, the first plurality of TSVs 3002 are laterally separated from the conductive layer 2906 by at least one second dielectric structure 3006 .

31C shows a cross-sectional view 3100c of an alternative embodiment of the integrated circuit of FIG. 30A , where the gap in the conductive layer 2906 and the first dielectric structure 2903 are located directly below the drain region 1008 . In some embodiments, the first dielectric structure 2903 has the same shape and/or the same width as the drain region 1008 when viewed from above. In a further embodiment, the width of the first dielectric structure 2903 is greater than the width of the drain region 1008 .

FIG. 31D shows a cross-sectional view 3100d of a partial alternative embodiment of the integrated circuit of FIG. 30A , where the gap in the conductive layer 2906 and the first dielectric structure 2903 are located directly below the gate electrode 1016 . In some embodiments, the first dielectric structure 2903 has the same shape and/or the same width as the gate electrode 1016 when viewed from above. In a further embodiment, the width of the first dielectric structure 2903 is greater than the width of the gate electrode 1016 .

32-42 illustrate a series of cross-sectional views 3200-4200 of some embodiments of a method of forming an integrated circuit including an opening disposed in a backside dielectric structure. Although the cross-sectional views 3200-4200 shown in FIGS. 32-42 are described with reference to a method, it should be understood that the structures shown in FIGS. . Although FIG. 32 to FIG. 42 describe a series of steps, it should be understood that the order of these steps is not limited, and the order of these steps can be changed in other embodiments, and the disclosed method can also be applied in other structures. In other embodiments, some steps shown and/or described may be omitted entirely or partially.

As shown in cross-sectional view 3200 of FIG. 32, a substrate 102 having a front side surface 102f and a back side surface 102b is received. In some embodiments, the substrate 102 may be or include, for example, silicon, bulk silicon, silicon germanium, germanium, gallium arsenide, other suitable semiconductor materials, or any combination thereof. In a further embodiment, the substrate 102 may include a first doping type (eg, p-type) with a doping concentration ranging from about 10 ¹⁴ to about 10 ¹⁶ atoms per cubic centimeter (atoms/cm ³ ).

The first isolation structure 806 and the third isolation structure 1020 are formed in the substrate 102 . In some embodiments, the process of forming the first isolation structure 806 includes etching the substrate 102 to define one or more trenches extending into the front surface 102f of the substrate 102, and filling the one or more trenches with a dielectric material. tank (eg, by chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, etc.). In a further embodiment, the process of forming the third isolation structure 1020 includes etching the substrate 102 and/or the first isolation structure 806 to define one or more trenches extending into the front side surface 102f of the substrate 102 and for intervening The electrical material fills one or more trenches (eg, by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.). The first isolation structure 806 and the third isolation structure 1020 may respectively be or include silicon dioxide, silicon nitride, silicon carbide, other dielectric materials, or any combination thereof.

In addition, the third well region 1002 and the fourth well region 1004 are formed in the substrate 102 . In various embodiments, the third well region 1002 may be formed by a first ion implantation process, and the fourth well region 1004 may be formed by a second ion implantation process. In some embodiments, the third well region 1002 and the fourth well region 1004 may be formed before forming the third isolation structure 1020 . In a further embodiment, the third well region 1002 includes the first doping type (eg, p-type), and the doping concentration is in the range of about 10 ¹⁶ to about 10 ¹⁸ atoms per cubic centimeter. In a further embodiment, the fourth well region 1004 includes the second doping type (eg, n-type), and the doping concentration is in the range of about 10 ¹⁶ to about 10 ¹⁸ atoms per cubic centimeter. In various embodiments, the first doping type is n-type and the second doping type is p-type, or vice versa.

As shown in the cross-sectional view 3300 of FIG. 33 , the gate structure 2910 , the body contact region 1012 , the source region 1010 and the drain region 1008 are formed in/on the substrate 102 to form the second semiconductor device 1006 . The gate structure 2910 covers the front side surface 102f of the substrate 102 and includes a gate electrode 1016 overlying the gate dielectric 1014 . In some embodiments, the process of forming the gate structure 2910 includes: depositing a gate dielectric material over the front surface 102f of the substrate 102 (for example, by chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, etc.); depositing gate electrode material over the gate dielectric material (e.g., by chemical vapor deposition, physical vapor deposition, sputtering, electroplating, etc.); middle), etch the gate dielectric material and the gate electrode material to define the gate dielectric 1014 and the gate electrode 1016 . The gate dielectric 1014 can be or include, for example, silicon dioxide, a high-k dielectric material (eg, a dielectric material with a dielectric constant greater than about 3.9), other dielectric materials, or any combination thereof. The gate electrode 1016 can be or include, for example, titanium, aluminum, tungsten, titanium nitride, tantalum, polysilicon, other conductive materials, or any combination thereof.

In some embodiments, the body contact region 1012 , the source region 1010 and the drain region 1008 are formed by one or more ion implantation processes. In some embodiments, the body contact region 1012 includes the first doping type (eg, p-type), and the doping concentration is in the range of about 10 ¹⁸ to about 10 ²⁰ atoms per cubic centimeter. In a further embodiment, the source region 1010 and the drain region 1008 respectively contain the second doping type (for example, n-type), and the doping concentration is in the range of about 10 ¹⁸ to about 10 ²⁰ atoms per cubic centimeter .

As shown in the cross-sectional view 3400 of FIG. 34 , the interconnect structure 120 is formed above the front side surface 102 f of the substrate 102 . The interconnection structure 120 includes an ILD structure 118 , a first IMD structure 119 , a plurality of conductive contacts 122 , a plurality of conductive lines 124 and a plurality of conductive vias 126 . In various embodiments, the ILD structure 118 and the first IMD structure may be deposited by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or other suitable growth or deposition processes. 119. In addition, the formation of the conductive contacts 122 , the conductive lines 124 and the conductive vias 126 may include one or more single damascene and/or dual damascene processes.

As shown in the cross-sectional view 3500 of FIG. 35 , the substrate 102 is turned over, and an insulating layer 2904 and a conductive layer 2906 are formed over the backside surface 102 b of the substrate 102 . The insulating layer 2904 can be formed by, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable growth or deposition processes. The conductive layer 2906 can be formed by, for example, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable growth or deposition processes. In a further embodiment, before forming the insulating layer 2904 and the conductive layer 2906 , a thinning process may be performed on the backside surface 102 b of the substrate 102 to reduce the thickness of the substrate 102 (not shown in the figure).

As shown in the cross-sectional view 3600 of FIG. 36 , a patterning process is performed on the conductive layer 2906 to form a plurality of openings 3602 and gaps 3604 in the conductive layer 2906 . In some embodiments, the patterning process includes: forming a patterned mask layer (not shown in the figure) on the conductive layer 2906; etching the conductive layer 2906 according to the patterned mask layer, thereby forming the opening 3602 and the gap 3604; and A removal process is performed to remove the patterned mask layer (not shown in the figure). In various embodiments, etching may include a wet etching process, a dry etching process, a reactive ion etching process, or the like. The gap 3604 can be laterally aligned with the source region 1010 of the second semiconductor device 1006 . In a further embodiment, the gap 3604 may be laterally aligned with another structure of the second semiconductor device 1006 (eg, the drain region 1008 , the gate electrode 1016 , etc.) (see eg, FIG. 31C or 31D ).

As shown in the cross-sectional view 3700 of FIG. 37 , a first dielectric structure 2903 and one or more second dielectric structures 3006 are formed in the gap (the gap 3604 in FIG. 36 ) and the opening (the opening 3602 in FIG. 36 ), respectively. . In various embodiments, the process of forming the first dielectric structure 2903 and the second dielectric structure 3006 includes: on the conductive layer 2906 and in the gap (gap 3604 of FIG. 36 ) and opening (opening 3602 of FIG. 36 ). Inside, deposit a dielectric material (for example, by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.); and perform a planarization process (for example, by chemical mechanical polishing (CMP) or similar methods ) to remove excess dielectric material from above the conductive layer 2906 . The first dielectric structure 2903 and the second dielectric structure 3006 may be or include, for example, silicon dioxide, silicon nitride, silicon carbide, other suitable dielectric materials, or any combination thereof. In a further embodiment, the first dielectric structure 2903 and the second dielectric structure 3006 include the same material as the insulating layer 2904 and/or part of the insulating layer 2904 .

As shown in the cross-sectional view 3800 of FIG. 38 , a first dielectric layer 3007 is formed on the conductive layer 2906 , and a second dielectric layer 3008 is formed on the first dielectric layer 3007 . In some embodiments, the first dielectric layer 3007 and the second dielectric layer 3008 are deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable growth or deposition processes. The first dielectric layer 3007 and the second dielectric layer 3008 may be or include, for example, silicon dioxide, silicon nitride, low-k dielectric materials, other dielectric materials, or any combination thereof.

As shown in cross-sectional view 3900 of FIG. 39 , a first plurality of through-substrate holes 3002 and a second plurality of through-substrate holes 3004 are formed extending through conductive layer 2906 and substrate 102 . The first plurality of TSVs 3002 laterally surround the second semiconductor device 1006 and are electrically coupled to the conductive layer 2906 . In some embodiments, the process of forming the first plurality of through-substrate holes 3002 and the second plurality of through-substrate holes 3004 includes: forming a first patterned mask layer (not shown in the figure) on the second dielectric layer 3008 ); patterning the second dielectric layer 3008 and the underlying layers/structures to form a plurality of TSV openings; above the second dielectric layer 3008 and within the plurality of TSV openings, depositing a conductive material (eg by chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, etc.) and pattern the conductive material according to a second patterned mask layer (not shown). In various embodiments, the first plurality of TSVs 3002 and the second plurality of TSVs 3004 may be or include, for example, polysilicon, doped polysilicon, copper, aluminum, gold, silver, platinum, other suitable conductive material or any combination of the above.

As shown in the cross-sectional view 4000 of FIG. 40 , a third passivation layer 3010 is formed on the second dielectric layer 3008 . In some embodiments, the third passivation layer 3010 is deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable growth or deposition processes. The third passivation layer 3010 can be or include, for example, silicon dioxide or other suitable dielectric materials. In various embodiments, the third passivation layer 3010 is part of the backside dielectric structure 2908 , wherein the formation of the backside dielectric structure 2908 includes the process steps shown and/or described in FIGS. 38 and 40 .

As shown in the cross-sectional view 4100 of FIG. 41 , a patterning process is performed on the backside dielectric structure 2908 to form an opening 2905 exposing the surface of the conductive layer 2906 and the surface of the first dielectric structure 2903 . In various embodiments, the opening 2905 is formed by the sidewalls of the first dielectric layer 3007, the sidewalls of the second dielectric layer 3008, the sidewalls of the third passivation layer 3010, the surface of the conductive layer 2906 and the surface of the first dielectric structure 2903. surface to define. In a further embodiment, the opening 2905 is laterally aligned with the second semiconductor device 1006 and facilitates the dissipation of thermal energy generated by the second semiconductor device 1006 from the substrate 102 . In some embodiments, the patterning process includes: forming a patterned mask layer 4102 on the third passivation layer 3010; etching the backside dielectric structure 2908 according to the patterned mask layer 4102; and performing a removal process to The patterned mask layer 4102 (not shown in the figure) is removed. In some embodiments, etching the backside dielectric structure 2908 includes performing a wet etch process, a dry etch process, a reactive ion etch process, or the like.

As shown in the cross-sectional view 4200 of FIG. 42 , a plurality of contact pads 3012 are formed on/in the third passivation layer 3010 . The contact pads 3012 may be or include, for example, nickel, gold, copper, aluminum, other metallic materials, or any combination thereof.

43 illustrates a flowchart 4300 of some embodiments of a method of forming an integrated circuit including an opening disposed in a backside dielectric structure. Although the method is shown and/or described as a series of steps or situations, it should be understood that the method is not limited in terms of order or steps. Therefore, in some embodiments, steps other than those shown and/or described may occur in a different order and/or simultaneously. In addition, in some embodiments, these illustrated steps or situations can be divided into multiple steps or situations, and can be executed simultaneously with other steps or sub-steps or in batches. In some embodiments, some illustrated steps or situations may be omitted, and other non-illustrated steps or situations may be included.

In step 4302, an isolation structure is formed in a substrate having a front surface opposite a back surface. FIG. 32 illustrates a cross-sectional view 3200 of some embodiments corresponding to step 4302 .

In step 4304, a semiconductor device is formed on the front side surface of the substrate. 32 and 33 illustrate cross-sectional views 3200 and 3300 of some embodiments corresponding to step 4304 .

In step 4306, interconnect structures are formed on the front side surface of the substrate. FIG. 34 illustrates a cross-sectional view 3400 of some embodiments corresponding to step 4306 .

In step 4308, an insulating layer and a conductive layer are formed on the backside surface of the substrate. FIG. 35 illustrates a cross-sectional view 3500 of some embodiments corresponding to step 4308 .

In step 4310, gaps are formed in the conductive layer such that the gaps are laterally aligned with one or more structures of the semiconductor device. FIG. 36 illustrates a cross-sectional view 3600 of a partial embodiment corresponding to step 4310 .

In step 4312, a backside dielectric structure is formed on the surface of the conductive layer. In addition, a plurality of through-substrate holes are formed extending through the substrate to the interconnection structure. 38-40 illustrate cross-sectional views 3800-4000 of some embodiments corresponding to step 4312.

In step 4314, the backside dielectric structure is patterned to form openings in the backside dielectric structure and expose at least a portion of the surface of the conductive layer. The opening is laterally aligned with the semiconductor device. FIG. 41 illustrates a cross-sectional view 4100 of a partial embodiment corresponding to step 4314 .

In step 4316, a plurality of contact pads are formed on the backside dielectric structure. FIG. 42 illustrates a cross-sectional view 4200 of a partial embodiment corresponding to step 4316.

Thus, in some embodiments, the present application relates to integrated circuits and includes semiconductor devices disposed in/on the front side surface of the substrate. The conductive layer is disposed on the backside surface of the substrate, and the backside dielectric structure is disposed on the bottom surface of the conductive layer. The backside dielectric structure includes sidewalls defining an opening exposing at least a portion of a bottom surface of the backside dielectric structure, wherein the opening is located directly below the semiconductor device.

FIG. 44 shows a cross-sectional view 4400 of an integrated circuit according to an alternate embodiment of the integrated circuit of FIG. 30A , wherein the integrated circuit includes both opening 2905 and opening 128 . In some embodiments, opening 128 at least partially covers opening 2905 . In other embodiments, opening 128 is laterally offset from opening 2905 . In some embodiments, heat generated by the second semiconductor device 1006 can escape from the second semiconductor device 1006 even more efficiently because the integrated circuit includes both the opening 2905 and the opening 128 .

In some embodiments, this application provides integrated wafers. The integrated chip includes a substrate. A semiconductor device is arranged on the substrate. The interlayer dielectric structure is disposed above the substrate and the semiconductor device. A first intermetal dielectric structure is disposed above the substrate and the interlayer dielectric structure. An opening is disposed in the first IMD structure, wherein the opening covers at least a part of the semiconductor device.

In some embodiments, the application provides an integrated chip. The integrated wafer includes a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate includes a device layer disposed above an insulating layer. A semiconductor device is disposed on the device layer. The interlayer dielectric structure is disposed above the substrate and the semiconductor device. An intermetal dielectric structure is disposed above the substrate and the interlayer dielectric structure. A conductive interconnect structure is embedded in the ILD structure and the IMD structure, wherein the conductive interconnect structure is defined by a plurality of conductive features. A passivation layer is disposed on the IMD structure and the conductive internal connection structure. a first opening disposed in the passivation layer and the IMD structure, wherein the first opening covers at least a portion of the semiconductor device, and wherein each of the plurality of conductive features is separated from the first opening .

In some embodiments, the present application provides a method of forming an integrated wafer, the method comprising receiving a workpiece comprising a semiconductor-on-insulator substrate, wherein a semiconductor device is disposed on a device layer of the semiconductor-on-insulator substrate wherein an intermetal dielectric structure is disposed over the device layer and the semiconductor device, and wherein a plurality of conductive features are disposed over the intermetal dielectric structure and the semiconductor-on-insulator substrate. A passivation layer is formed over the IMD structure and the conductive features. An opening is formed in the passivation layer and the IMD structure, wherein the opening covers at least a portion of the semiconductor device.

In some embodiments, the application provides an integrated circuit, the integrated circuit includes: a substrate having a front surface opposite to a back surface; a semiconductor device disposed on the front surface of the substrate ; an insulating layer disposed on the backside surface of the substrate; a conductive layer disposed on the insulating layer; and a backside dielectric structure disposed along the conductive layer, wherein the backside dielectric structure An opening is provided in the material structure, and the opening directly covers at least a part of the semiconductor device.

In some embodiments, the application provides an integrated circuit, the integrated circuit includes: a high voltage transistor disposed on a front surface of a substrate, wherein the high voltage transistor includes a gate electrode, laterally separated Between a source region and a drain region, wherein a well region is arranged between the source region and the drain region; a conductive layer is arranged on a backside surface of the substrate; a first interlayer an electrical structure extending through the conductive layer and located below the high voltage transistor; and a low-k dielectric structure disposed on a bottom surface of the conductive layer, wherein the low-k dielectric structure includes an opening defining an opening A plurality of sidewalls, the opening exposes at least a portion of the bottom surface of the conductive layer, the conductive layer is located under the high voltage transistor.

In some embodiments, this application provides a method for forming an integrated circuit, including forming a semiconductor device on a front surface of a substrate; depositing an insulating layer on a back surface of the substrate; layer, depositing a conductive layer; on the conductive layer, forming a backside dielectric structure; and patterning the backside dielectric structure to form an opening extending through the backside dielectric structure , and expose a surface of the conductive layer, wherein the semiconductor device is laterally located within a periphery of the opening.

The features of several embodiments are summarized above, so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same advantages and/or perform the same purposes as the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the present disclosure.

100, 200~4400: sectional view/top view/plan view 102: substrate 102f: front surface 102b: back surface 104: device layer 106, 2904: insulating layer 108: processing layer 110: first semiconductor device 112: a pair of source electrodes /drain region 114, 1014: gate dielectric 116, 1016: gate electrode 118: interlayer dielectric structure 119: first intermetal dielectric structure 119s, 308s, 602s, 604bs, 604cs, 2908s ₁ , 2908s ₁ : side wall 119s ₁ , 308s ₁ , 602s ₁ , 604bs ₁ , 604cs ₁ , 1018sw ₁ : first side wall 119s ₂ , 308s ₂ , 602s ₂ , 604bs ₂ , 604cs ₂ , 1018sw ₂ : second side wall 119s ₃ : No. Three side walls 119s ₄ : fourth side wall 120: internal connection structure 122: conductive contacts 124, 124 _M-3 , 124 _M-2 , 124 _M-1 , 124 _M : conductive wires, the first group of conductive wires, the second group of conductive Line, third set of conductive lines, fourth set of conductive lines 126: conductive via 128, 2905, 3602: opening 128p, 802p: perimeter 302: second IMD structure 304: third IMD structure 304u ₁ , 604au ₁ : first top surface 304u ₂ , 604au ₂ : second top surface 306, 306 _N-3 , 306 _N-2 , 306 _{N- 1} , 306 _N : conductive layer, first conductive layer, second Conductive layer, third conductive layer, fourth conductive layer 308: first passivation layer 310: first set of conductive features 312: second set of conductive features 314: third set of conductive features 502: input/output (I/ O) Structure 504: upper conductive via 602: second passivation layer 604, 604a, 604b, 604c,: etch stop layer, first etch stop layer, second etch stop layer, third etch stop layer 802: first well Zone 804: second well zone 806: first isolation structure 806ip, 1020ip, 2908ip, 2906ip, 3010ip: inner perimeter 806op, 1020op: outer perimeter 1002: third well zone 1004: fourth well zone 1006: second semiconductor device 1008 : drain region 1010: source region 1012: base contact region 1018: second isolation structure 1020: third isolation structure 1202: regions 1402a, 1402b, 1402c, 1402d: first opening, second opening, third opening, first opening Four openings 1404a, 1404b, 1404c, 1404d: first area, second area, third area, fourth area 1502a, 1502b: third semiconductor device, fourth semiconductor device 1802: workpiece 2002: first patterned mask Layer 2004: first opening 2202: second patterned mask layer 2204: second opening 2402: third patterned mask layer 2404a, 2404b: third opening, fourth opening 2502: fifth opening 2504 : sixth opening 2602: fourth patterned mask layer 2604: fifth opening 2702: seventh opening 2704: frame 2802~2804, 4302~4316: step 2903: first dielectric structure 2906: conductive layer 2908: Backside dielectric structure 2910: gate structure 3001: backside structure 3002: first plurality of through-substrate holes 3004: second plurality of through-substrate holes 3006: second dielectric structure 3007: first dielectric layer 3008 : second dielectric layer 3010: third passivation layer 3012: contact pad 3604: gap 4102: patterned mask layer

Aspects of the present disclosure are best understood from the following detailed description when examined with accompanying drawings. It should be noted that the various features are not drawn to scale with reference to standard industry practice. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a portion of an embodiment of an integrated wafer including openings disposed in a first IMD structure. FIG. 2 illustrates a simplified top view of a partial embodiment of the integrated chip of FIG. 1 . FIG. 3 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 1 . FIG. 4 illustrates a simplified top view of a partial embodiment of the integrated chip of FIG. 3 . FIG. 5 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 1 . FIG. 6 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 5 . FIG. 7 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 6 . FIG. 8 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 3 . FIG. 9 illustrates a simplified top view of a partial embodiment of the integrated chip of FIG. 8 . FIG. 10 is a cross-sectional view of some other embodiments of the integrated chip of FIG. 8 . FIG. 11 illustrates a simplified top view of some embodiments of the integrated chip of FIG. 10 . FIG. 12 is a perspective view of some embodiments of the integrated chip shown in FIG. 6 . FIG. 13 is a cross-sectional view of some embodiments of the integrated chip shown in FIG. 12 . FIG. 14 is a perspective view of some other embodiments of the integrated chip shown in FIG. 12 . FIG. 15 is a cross-sectional view of some embodiments of the integrated chip shown in FIG. 14 . FIG. 16 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 15 . FIG. 17 is a cross-sectional view of some other embodiments of the integrated chip shown in FIG. 10 . 18-23 illustrate a series of cross-sectional views of some embodiments of a method of forming an integrated wafer including a plurality of openings disposed in a first IMD structure. 24-27 show a series of cross-sectional views of some other embodiments of the method shown in FIGS. 18-23. 28 is a flowchart illustrating some embodiments of a method of forming an integrated wafer including an opening disposed in an IMD structure. 29A illustrates a cross-sectional view of a portion of an embodiment of an integrated circuit including an opening in a backside dielectric structure disposed beneath a second semiconductor device. 29B to 29C show various plan views of the integrated circuit of FIG. 29A taken along line A-A'. FIG. 30A shows a cross-sectional view of a partial alternative embodiment of the integrated circuit of FIG. 29A. 30B and 30C show various plan views of the integrated circuit of FIG. 30A taken along line A-A'. 31A-31D show cross-sectional views of various alternative embodiments of the integrated circuit of FIG. 30A. 32-42 illustrate a series of cross-sectional views of some embodiments of a method of forming an integrated circuit including an opening disposed in a backside dielectric structure. 43 is a flow diagram of some embodiments of a method of forming an integrated circuit including an opening disposed in a backside dielectric structure. FIG. 44 illustrates a cross-sectional view of an integrated circuit of a partial alternative embodiment of the integrated circuit of FIG. 30A.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

102: Substrate

104: Device layer

106: insulation layer

108: Processing layer

118:Interlayer dielectric structure

119: The first intermetal dielectric structure

120: Internal connection structure

122: Conductive contact

124: conductive thread

126: Conductive vias

308: the first passivation layer

806: The first isolation structure

1002: The third well area

1004: The fourth well area

1006: the second semiconductor device

1008: Drain area

1010: source region

1012: Substrate contact area

1014: gate dielectric

1016: gate electrode

1018: Second isolation structure

1020: The third isolation structure

1402a: first opening

1402b: second opening

Claims (20)

An integrated chip, including: a substrate; a semiconductor device disposed on the substrate; an interlayer dielectric structure disposed above the substrate and the semiconductor device; a first IMD structure disposed over the substrate and the ILD structure; and An opening is disposed in the first IMD structure, wherein the opening covers at least a part of the semiconductor device. The integrated chip as described in claim 1, wherein: The substrate is a semiconductor-on-insulator substrate; The semiconductor-on-insulator substrate includes a device layer disposed over an insulating layer; and The semiconductor device is disposed on the device layer. The integrated wafer as claimed in claim 1, wherein the opening has a perimeter defined by a plurality of sidewalls of the first IMD structure, and wherein the portion of the semiconductor device is laterally disposed on the opening in the perimeter. The integrated chip as described in claim 3 further includes: A passivation layer is disposed over the first IMD structure, wherein the perimeter of the opening is defined by the sidewalls of the first IMD structure and the sidewalls of the passivation layer. The integrated chip as claimed in claim 3, wherein the periphery of the opening laterally surrounds the portion of the semiconductor device in a closed loop. The integrated chip as described in Claim 5, wherein: The semiconductor device includes a gate electrode; and The gate electrode is disposed in the periphery of the opening. The integrated chip as described in Claim 6, wherein: The semiconductor device includes a pair of source/drain regions; and The pair of source/drain regions is disposed in the periphery of the opening. The integrated chip as described in claim 5 further includes: An isolation structure is disposed in the substrate and laterally surrounds the semiconductor device, wherein the periphery of the opening covers and is substantially aligned with a layout of the isolation structure. The integrated chip as described in Claim 8, wherein: the isolation structure has an inner perimeter and an outer perimeter; and The perimeter of the opening is disposed laterally between the inner perimeter of the isolation structure and the outer perimeter of the isolation structure. The integrated chip as described in claim 5 further includes: a first doped well region disposed in the substrate, wherein a pair of source/drain regions of the semiconductor device is disposed in the first doped well region; and A second doped well region, disposed in the substrate, wherein the first doped well region is at least partially disposed in the second doped well region, wherein the second doped well region has the same The mixed well region is of opposite doping type, and wherein the periphery of the opening laterally surrounds the first doped well region. The integrated wafer as claimed in claim 10, wherein the periphery of the opening is laterally disposed between a periphery of the first doped well region and a periphery of the second doped well region. The integrated chip as described in claim 1 further includes: A conductive interconnection structure embedded in the interlayer dielectric structure and the first intermetal dielectric structure, wherein the conductive interconnection structure includes a plurality of conductive layers vertically stacked, wherein each of the conductive layers includes One or more conductive lines, and one or more of the conductive layers are vertically disposed between a bottom of the opening and a top surface of the first IMD structure. The integrated chip as claimed in claim 12, wherein each of the one or more conductive lines of each of the conductive layers is separated from the opening. The integrated chip as described in claim 13 further includes: A second IMD structure disposed over the ILD structure, wherein: the second intermetal dielectric structure is vertically disposed between the first intermetal dielectric structure and the interlayer dielectric structure; the conductive interconnect structure is embedded in the second IMD structure; The conductive interconnect structure includes a first set of conductive features embedded in the first IMD structure on a first side of the opening; the conductive interconnect structure includes a second set of conductive features embedded in the first IMD structure on a second side of the opening, the second side opposite the first side; the conductive interconnect structure includes a third set of conductive features embedded in the second IMD structure and underlying the first IMD structure; and The third set of conductive features electrically couples the first set of conductive features to the second set of conductive features. An integrated circuit, comprising: a substrate having a front surface opposite to a back surface; a semiconductor device disposed on the front surface of the substrate; an insulating layer disposed on the backside surface of the substrate; a conductive layer disposed on the insulating layer; and A backside dielectric structure is disposed along the conductive layer, wherein an opening is set in the backside dielectric structure, and the opening directly covers at least a part of the semiconductor device. The integrated circuit of claim 15, wherein a top surface of the opening is defined by a bottom surface of the conductive layer. The integrated circuit of claim 15, wherein a perimeter of the opening is defined by sidewalls of the backside dielectric structure, wherein the semiconductor devices are laterally separated within the perimeter of the opening. The integrated circuit as described in Claim 17, further comprising: A deep trench isolation structure extends into the front side surface of the substrate and laterally surrounds the semiconductor device, wherein the deep trench isolation structure directly covers a first sidewall of the sidewalls. A method of forming an integrated wafer, comprising: Receiving a workpiece comprising a semiconductor-on-insulator substrate, wherein a semiconductor device is disposed on a device layer of the semiconductor-on-insulator substrate, and wherein an intermetallic dielectric structure is disposed over the device layer and the semiconductor device , and wherein a plurality of conductive features are disposed in the intermetal dielectric structure and over the semiconductor-on-insulator substrate; forming a passivation layer over the IMD structure and the conductive features; and An opening is formed in the passivation layer and the IMD structure, wherein the opening covers at least a portion of the semiconductor device. The method of claim 19, wherein forming an opening in the passivation layer and the IMD structure comprises: A patterned mask layer is formed over the passivation layer, wherein the patterned mask layer includes an opening covering a portion of the passivation layer and a portion of the IMD structure, and each of the The conductive features are separated from both the portion of the passivation layer and the portion of the IMD structure; and With the patterned mask layer positioned, an etching process is performed to remove the portion of the passivation layer and the portion of the IMD structure.

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