CN207781612U - Power semiconductor - Google Patents

Abstract

This application discloses power semiconductors.The power semiconductor includes：Multiple grooves in semiconductor substrate；Positioned at the insulating laminate of multiple lower trench sidewalls and bottom；At least part is located at the shielded conductor in multiple grooves, and shielded conductor extends to its bottom above multiple grooves, and is isolated from each other by insulating laminate between semiconductor substrate；It is located at the grid conductor of shielded conductor both sides in multiple groove tops；The source electrode being electrically connected with source region and shielded conductor；And the gate electrode being electrically connected with grid conductor, wherein, it is isolated from each other by at least one layer in insulating laminate between grid conductor and shielded conductor, is isolated from each other by gate-dielectric between grid conductor and body area, is isolated from each other by insulating laminate between shielded conductor and semiconductor substrate.The power semiconductor forms separation layer to avoid the short circuit of grid source at the top of shielded conductor.

Description

Power semiconductor

Technical field

The utility model is related to technical field of electronic devices, more particularly, to power semiconductor.

Background technology

Power semiconductor is also known as power electronic devices, including power diode, thyristor, VDMOS (vertical double expansions Dispersed metallic oxide semiconductor) field-effect transistor, LDMOS (lateral diffusion metal oxide semiconductor) field-effect transistors with And IGBT (insulated gate bipolar transistor) etc..VDMOS field-effect transistors include the shape on the apparent surface of semiconductor substrate At source region and drain region, in the on-state, longitudinal flow of the electric current mainly along semiconductor substrate.

In the high frequency of power semiconductor uses, lower conduction loss and switching loss are evaluation device performances Important indicator.On the basis of VDMOS field-effect transistors, further develop groove type MOS field-effect transistor, wherein Grid conductor is formed in the trench, and gate-dielectric is formed on trenched side-wall to separate grid conductor and semiconductor layer, thus The direction of side wall forms raceway groove in the semiconductor layer along groove.Groove (Trench) technique from level by raceway groove due to becoming vertical Directly, the influence for eliminating planar structure parasitism JFET resistance, makes cellular size be substantially reduced.It is close to increase primitive unit cell on this basis Degree improves the overall width of unit area chip interior raceway groove, so that it may so that channel width-over-length ratio of the device on unit silicon chip increases To make electric current increase, conducting resistance declines and relevant parameter is optimized, and realizes smaller size of tube core and possesses bigger Power and high performance target, therefore trench process is more and more applies in novel power semiconductor.

However, with the raising of cell density, electrode resistance can increase, and switching loss accordingly increases, and gate leakage capacitance Cgd is straight Connect the switching characteristic for being related to device.In order to reduce gate leakage capacitance Cgd, division gate groove (Split Gate are further developed Trench is abbreviated as SGT) type power semiconductor, wherein grid conductor extends to drift region, while grid conductor and leakage It is separated using thick-oxide between pole, to reduce gate leakage capacitance Cgd, improves switching speed, reduce switching loss.With This shielded conductor below grid conductor and is connected simultaneously with source electrode, common to be grounded, flat to introduce charge Weigh effect, has reduction surface field (Reduced Surface Field, abbreviation in the vertical direction of power semiconductor For RESURF) effect, it is further reduced conducting resistance Rdson, to reduce conduction loss.

Cutting for the manufacturing method key step of SGT power semiconductors according to prior art is shown respectively in Fig. 1 a and 1b Face figure.As shown in Figure 1a, groove 102 is formed in semiconductor substrate 101.The first insulating layer is formed in the lower part of groove 102 103, shielded conductor 104 fills groove 102.On the top of groove 102, two openings separated by shielded conductor 104 are formed.Into One step, as shown in Figure 1 b, gate-dielectric is formed in the upper portion side wall of groove 102 and the expose portion of shielded conductor 104 105, then conductive material is filled to form two grid conductors 106 in two openings that shielded conductor 104 separates.

In the SGT power semiconductors, shielded conductor 104 is connected with the source electrode of power semiconductor, For generating RESURF effects.Two grid conductors 106 are located at the both sides of shielded conductor 104.Shielded conductor 104 is partly led with power It is separated by the first insulating layer 103 between the drain region of body device, is separated by gate-dielectric 105 between gate electrode 106.Grid It is separated by gate-dielectric 105 between well region in conductor 106 and semiconductor substrate 101, to form raceway groove in well region.Such as Shown in figure, the thickness of the first insulating layer 103 is less than the thickness of gate-dielectric 105.

According to SGT theories, no matter which kind of SGT structure, the material of shielded conductor 104 is required for and the isolation of the second conductive material And the material for isolation needs to meet certain capacitance parameter, is otherwise susceptible to the short circuit of grid source, gate leakage capacitance Cgd exceptions etc. Failure.How optimised devices structure and to meet the parameter and reliability requirement of product, while wiring method being accomplished most efficient, low Cost is the content to be studied of those skilled in the art.

Utility model content

In view of the above problems, the purpose of this utility model is to provide a kind of power semiconductors, wherein being led in shielding Separation layer is formed at the top of body to avoid the short circuit of grid source, to improve reliability.

One side according to the present utility model provides a kind of manufacturing method of power semiconductor, including：It is mixed first Multiple grooves are formed in the semiconductor substrate of miscellany type；Insulating laminate, institute are formed on the side wall of the multiple groove and bottom It includes the first insulating layer and second insulating layer to state insulating laminate, and first insulating layer surrounds the second insulating layer；Described Shielded conductor is filled in multiple grooves, the first opening is formed at the top of the shielded conductor；On the top of the multiple groove Form the second opening positioned at the shielded conductor both sides, the side wall on the multiple groove top of the second opening exposure； Separation layer is formed in first opening and second opening；Grid electricity is formed on the side wall on the multiple groove top to be situated between Matter；Grid conductor is formed to fill second opening；Second is formed in the region of the semiconductor substrate adjacent trench to mix The areas miscellany Xing Ti, second doping type are opposite with first doping type；Described first is formed in the body area The source region of doping type；And source electrode and gate electrode are formed, the source electrode is led with the source region and the shielding Body is electrically connected, and the gate electrode is electrically connected with the grid conductor, wherein between the grid conductor and the shielded conductor It is isolated from each other by at least one layer in the insulating laminate, by the gate-dielectric between the grid conductor and the body area It is isolated from each other, is isolated from each other by the insulating laminate between the shielded conductor and the semiconductor substrate.

Preferably, further include planarization steps between the step of filling shielded conductor and the step of forming the second opening.

Preferably, before planarization steps, the shielded conductor, first insulating layer and the second insulating layer point Do not include the first part being located in the multiple groove and second be laterally extended on the semiconductor substrate surface Point, in planarization steps, using first insulating layer as stop-layer, remove the shielded conductor and the second insulating layer Respective second part so that, the respective first part top and described first of the shielded conductor and the second insulating layer The surface of insulating layer flushes.

Preferably, in the step of forming the second opening, the first part of first insulating layer is removed positioned at described more The part on a groove top so that the shielded conductor upwardly extends scheduled height from the semiconductor substrate surface.

Preferably, the step of formation grid conductor includes：Depositing first conductive layer is to fill second opening, and described the One conductive layer includes the first part being located in second opening and is laterally extended on the semiconductor substrate surface Second part；And the second part of the grid layer conductor is patterned to wiring.

Preferably, in patterning step, described first is completely removed in the first area of the semiconductor substrate and is led The second part of electric layer partly removes the second part of first conductive layer in the second area of the semiconductor substrate, In the first area of the semiconductor substrate, the second part of the grid conductor is removed.

Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area, The first area and the second area are separated from each other.

Preferably, first insulating layer is made of silica, and the second insulating layer is by being selected from silicon nitride, nitrogen oxides Or at least one of polysilicon composition.

Preferably, the width of the multiple groove is in the range of 0.2 to 10 micron, model of the depth at 0.1 to 50 micron In enclosing.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple The bottom width of groove.

Preferably, the step of the step of filling the shielded conductor and the formation grid conductor, respectively includes at least once Deposition.

Another aspect according to the present utility model provides a kind of power semiconductor, including：In semiconductor substrate Multiple grooves, the semiconductor substrate be the first doping type；Positioned at the areas the semiconductor substrate Zhong Ti, the body area is adjacent Nearly the multiple groove top, and be the second doping type, second doping type is opposite with first doping type；Position Source region in the body area, the source region are the first doping type；Positioned at the exhausted of the multiple lower trench sidewalls and bottom Edge lamination, the insulating laminate include the first insulating layer and second insulating layer, and first insulating layer insulate around described second Layer；At least part is located at the shielded conductor in the multiple groove, and the shielded conductor extends above the multiple groove To its bottom, and it is isolated from each other by the insulating laminate between the semiconductor substrate；In the multiple groove top Grid conductor positioned at the shielded conductor both sides；The source electrode being electrically connected with the source region and the shielded conductor；And The gate electrode being electrically connected with the grid conductor, wherein by the insulation between the grid conductor and the shielded conductor At least one layer in lamination is isolated from each other, and is isolated from each other by the gate-dielectric between the grid conductor and the body area, It is isolated from each other by the insulating laminate between the shielded conductor and the semiconductor substrate.

Preferably, the shielded conductor upwardly extends scheduled height from the semiconductor substrate surface.

Preferably, the grid conductor further includes the second part being laterally extended on the semiconductor substrate surface, institute The second part of grid layer conductor is stated as wiring so that the source electrode and the gate electrode are separated from each other.

Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area.

Preferably, first insulating layer is made of silica, and the second insulating layer is by being selected from silicon nitride, nitrogen oxides Or at least one of polysilicon composition.

Preferably, the width of the multiple groove is in the range of 0.2 to 10 micron, model of the depth at 0.1 to 50 micron In enclosing.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple The bottom width of groove.

Preferably, the power semiconductor is selected from cmos device, BCD devices, mosfet transistor, IGBT and Xiao One kind in special based diode.

In the method according to the utility model embodiment, SGT structures are formed in power semiconductor, wherein Insulating laminate is formed between shielded conductor and semiconductor substrate, to reduce gate leakage capacitance Cgd.Further, at the bottom of groove Portion forms the doped region with semiconductor substrate opposite dopant type.During the work of power semiconductor, doped region and half The carrier of conductor substrate mutually exhausts, and to make full use of electric equilibrium theoretical, further decreases gate leakage capacitance Cgd.The step It can be employed directly for forming the photoresist mask of groove, be manufactured into so as to reduce process complexity and reduction This.

In a preferred embodiment, grid conductor includes the first part being located in groove and second as wiring layer Part, the second part connect with the first part and are laterally extended on a semiconductor substrate.The second part of grid conductor As wiring layer so that gate electrode may be located remotely from source electrode, to improve the reliability of power semiconductor.Further Ground, this method are used for the rewiring of gate electrode without additional conductive layer, so as to reduce process complexity and subtract Few manufacturing cost.

In a preferred embodiment, shielded conductor from semiconductor substrate surface upwardly extends scheduled height (height is big Cause the thickness equal to the first insulating layer).In the step of forming grid conductor, grid conductor is covered in above shielded conductor.So Afterwards, in an etching step, above the first area of semiconductor substrate, grid conductor can be completely removed and be located on shielded conductor The part of side.Further, separation layer is formed at the top of shielded conductor.The design can improve the reliable of power semiconductor Property, short circuit occurs between the grid source to avoid power semiconductor, that is, avoids the formation of since source region, via source electrode electricity Pole, shielded conductor, contact hole reach the short circuit paths of gate electrode.

This method realizes SGT structures by better simply processing step, solves complex process in common process, is susceptible to While parameter and reliability requirement to meet product of the short circuit of grid source, the problems such as gate leakage capacitance Cgd is abnormal, in conjunction with specific work Wiring method is accomplished most efficient, low cost by skill step.Compared with prior art, 0.25~0.35um techniques, this method are based on The photoresist mask used in currently manufactured technique can be reduced by 3~4 photoresist masks.

The utility model embodiment use a kind of reduction source drain capacitance separate gate power semiconductor device structure and its Forming method can also apply in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.

Description of the drawings

By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from, in the accompanying drawings：

The section of the manufacturing method key step of power semiconductor according to prior art is shown respectively in Fig. 1 a and 1b Figure.

Fig. 2 shows the flow charts according to the manufacturing method of the power semiconductor of this implementation new embodiment.

Fig. 3 a to 3i show the sectional view of the method, semi-conductor device manufacturing method different phase according to this implementation new embodiment.

Specific implementation mode

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Reference numeral indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown Certain well known parts.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.

It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario The form of presentation of face " or " A is on B and abuts therewith ".In this application, " A is in B " indicates that A is located in B, and And A and B is abutted rather than A is located in the doped region formed in B.

In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices The general designation of conductor structure, including all layers formed or region.

Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art Material is constituted.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC and IV race semiconductor, such as Si、Ge。

Fig. 2 shows the flow chart according to the manufacturing methods of the SGT power semiconductors of the utility model embodiment, Fig. 3 a The sectional view in different step is shown respectively to 3i.It is described according to the utility model embodiment below in conjunction with Fig. 2 and 3a to 3i Manufacturing method the step of.

This method starts from semiconductor substrate 101.Semiconductor substrate is, for example, to be doping to the silicon substrate of N-type, the silicon substrate Longitudinal uniform doping, resistivity is for example between the range of 1~15 Ω cm.Semiconductor substrate has opposite first surface And second surface.Preferably, in the first surface of semiconductor substrate, pass through the works such as photoetching, etching, ion implanting, impurity activation Skill forms the partial pressure ring structure of power semiconductor, and the partial pressure ring structure belongs to the well known knot of one kind of this field device architecture Structure part, this will not be detailed here.Preferably, it is brilliant that the semiconductor substrate 101 used in the present embodiment could be formed with MOS field-effects The semiconductor devices such as body pipe, IGBT isolated-gate field effect transistor (IGFET)s, Schottky diode.

In step S101, groove is respectively formed in the first area of semiconductor substrate 101 201 and second area 202 102, as shown in Figure 3a.

The technique for being used to form groove 102 includes forming Etching mask by photoetching and etching, via Etching mask Opening etching removal semiconductor substrate 101 expose portion.

In this embodiment, first area 201 refers to the wiring area of source region and shielded conductor in SGT structures, second Region 202 refers to the wiring area of grid conductor in SGT structures.

Groove 102 is extended downwardly from the surface of semiconductor substrate 101, and is reached in the semiconductor substrate 101 and made a reservation for Depth.In this embodiment, the width of groove 102 is, for example, 0.2 to 10 micron, and depth is, for example, 0.1 to 50 micron.SGT The width of the groove of structure is wider much than the groove of the convention trench power semiconductor of identical conducting level of efficiency, and its The depth of groove is also deeply more many than the groove of convention trench power semiconductor.

Preferably, the sidewall slope of groove 102, for example, relative to vertical trench 102 top at 85 to 89 degree angle, So that the bottom width of groove 102 is less than top width.The angle of groove is more oblique, is conducive to follow-up each dielectric layer, conductive material Filling, caused by reduction blind the problems such as defect.

In step s 102, insulating laminate is sequentially formed on the surface of semiconductor substrate 101, which includes altogether The first insulating layer 122 and second insulating layer 123 of shape, as shown in Figure 3b.

In groove 102, the first insulating layer 122 surrounds second insulating layer 123.First insulating layer 122 and second insulating layer 123 are made of different insulating materials.In this embodiment, the first insulating layer 122 is for example made of silica.Second insulating layer 123 are for example formed by being selected from least one of silicon nitride, nitrogen oxides or polysilicon.Preferably, second insulating layer 123 is by nitrogen SiClx forms.The thickness of first insulating layer 122 is, for example, 500 to 50000 angstroms, the thickness of second insulating layer 123 be, for example, 50 to 5000 angstroms.The thickness of first insulating layer 122 is bigger, then gate leakage capacitance Cgd is smaller.

The technique for being used to form the first insulating layer 122 includes by thermal oxide, chemical vapor deposition (CVD) or high density etc. Ion body chemical vapor phase growing forms oxide layer in the inner wall of groove 102.The side of the oxide layer conformally covering groove 102 Wall and bottom, to still retain a part of inner space of groove 102.

The technique for being used to form second insulating layer 123 includes passing through chemical vapor deposition (CVD) or high-density plasma Chemical vapor deposition forms nitride layer on 122 surface of the first insulating layer.The nitride layer conformally covers the first insulating layer 122 surface, to still retain a part of inner space of groove 102.

In step s 103, shielded conductor 104 is formed in groove 102, as shown in Figure 3c.

The shielded conductor 104 is for example made of the non-crystalline silicon or polysilicon that adulterate.It is used to form the technique of shielded conductor 104 Such as including using process deposits polysilicons such as sputterings so that polysilicon fills the remainder of groove 102, and using chemistry Mechanical planarization (CMP) removal is located at the polysilicon outside groove 102 so that the polysilicon of filling groove 102 forms shielding and leads Body 104.

The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius, Thickness is, for example, 1000 to 100000 angstroms.By controlling the doping concentration of shielded conductor 104, its resistance can be adjusted.In the reality It applies in example, the square resistance Rs of shielded conductor 104 is, for example, less than 20 ohm.Further, the square resistance Rs of shielded conductor 104 Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, shielded conductor 104 Material selection amorphous, it is easier to form lower square resistance Rs.

In above-mentioned deposition step, one or many materials for depositing and forming shielded conductor 104 may be used.Multiple When deposition, the rate of subsequent deposition process is less than previous deposition step, to which deposition rate is gradually reduced.In trench fill process In, the slower filling effect of deposition rate is better, the filling of channel bottom packing ratio the top of the groove difficulty, therefore in multiple filling, preceding The rate of face deposition needs to be less than the rate of any primary depositing below.

In above-mentioned chemical-mechanical planarization step, stop-layer is used as using the first insulating layer 122, to not only remove Polysilicon is located at the part outside groove 102, and further also removal second insulating layer 123 is located at the part outside groove 102.Cause This, the top of shielded conductor 104 and second insulating layer 123 is flushed with the surface of the first insulating layer 122.

Preferably, a part of polysilicon is removed in 104 top etching of shielded conductor, to form the first opening 1241.

The etch process is, for example, dry etching.Due to the selectivity of etchant, relative to the first insulating layer 122 and second Insulating layer 123 removes the expose portion of shielded conductor 104, is formed to a part of polysilicon of etch-back shielded conductor 104 Opening 1241.The opening 1241 is used to provide the accommodation space of separation layer, so as to improve the mechanical strength of the separation layer.

In step S104, a part for etching the first insulating layer 122 of removal is located to be formed on the top of groove 102 Second opening 1242 of 104 both sides of shielded conductor, and fill separation layer in the first opening 1241 and the second opening 1242 131, as shown in Figure 3d.Second opening 1242 exposes the upper portion side wall of groove 102 again.

The etch process is, for example, wet etching.Due to the selectivity of etchant, relative to semiconductor substrate 101, second Insulating layer 123 and shielded conductor 104 remove the expose portion of the first insulating layer 122.The etching not only removes the first insulating layer 122 Part outside groove 102, but also the first insulating layer of etch-back 122 is located at the part inside groove 102, to exposure The surface of semiconductor substrate 101.Second insulating layer 123 and a part for shielded conductor 104 from the surface of semiconductor substrate 101 to The height of upper extension correspond to the first insulating layer 122 thickness, for example, 500 to 50000 angstroms.The height of the extension is conducive to follow-up Contact hole hole opening technology.The depth that first insulating layer 122 extends from the top down of semiconductor substrate 101 is, for example, 0.5 to 5 micro- Rice.After the etching, the first insulating layer 122 is located at the lower sides of groove 102 and a part for bottom retains so that shielding is led It is still isolated from each other by insulating laminate between the lower part and semiconductor substrate 101 of body 104.

The technique for being used to form separation layer 131 includes passing through thermal oxide, chemical vapor deposition (CVD) or high-density plasma Body chemical vapor phase growing.In this embodiment, separation layer 131 is for example made of silica.In this step, separation layer 131 is not It is made only in the first opening 1241, and is also formed in the second opening 1242.Therefore, the thickness for selecting separation layer 131, makes A part of depth that separation layer 131 is only only filled with the second opening 1242 is obtained, so that the space of the second opening 1242 can be further Accommodate grid conductor.The thickness of separation layer 131 is, for example, 500 to 5000 angstroms.After forming separation layer 131, the second opening 1242 depth is preferably 0.5 to 5 micron.In step S105, on the top of the upper portion side wall and shielded conductor 104 of groove 102 Portion forms gate-dielectric 105, as shown in Figure 3 e.

Thermal oxide may be used in the technique for being used to form gate-dielectric 105.The temperature of the thermal oxide be, for example, 950 to 1200 degrees Celsius.The exposure silicon materials of semiconductor substrate 101 and shielded conductor 104 form silica in thermal oxidation process. In step of thermal oxidation, the surface of semiconductor substrate 101 is also exposed in atmosphere.Gate-dielectric 105 is not placed only in groove 102 Upper portion side wall on, and be covered on the surface of semiconductor substrate 101.

Compared with fine and close semiconductor substrate 101, shielded conductor 104 is the amorphous or polycrystalline material of heavy doping, structure More loose, doping concentration is higher.As a result, gate-dielectric 105 is located at the thickness ratio of the second part on 104 surface of shielded conductor The thickness of first part on 101 surface of semiconductor substrate and in groove 102 is big.The first part of gate-dielectric 105 Thickness be, for example, 50 to 5000 angstroms, the thickness of second part is, for example, 60 to 10000 angstroms.

In step s 106, grid conductor 106 is formed in the trench, and adjacent with groove 102 in semiconductor substrate 101 Region in form body area 107 and source region 108, as illustrated in figure 3f.

The grid conductor 106 is for example made of the non-crystalline silicon or polysilicon that adulterate.It is used to form the technique of grid conductor 106 Such as including using process deposits polysilicons such as sputterings so that polysilicon fills the second opening 1242 of 104 both sides of shielded conductor.

The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius, Thickness is, for example, 1000 to 100000 angstroms.By controlling the doping concentration of grid conductor 106, its resistance can be adjusted.In the reality It applies in example, the square resistance Rs of grid conductor 106 is, for example, less than 20 ohm.Further, the square resistance Rs of grid conductor 106 Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, grid conductor 106 Material selection amorphous, it is easier to form lower square resistance Rs.

In above-mentioned deposition step, one or many materials for depositing and forming grid conductor 106 may be used.Multiple When deposition, the rate of subsequent deposition process is less than previous deposition step, to which deposition rate is gradually reduced.In trench fill process In, the slower filling effect of deposition rate is better, the filling of channel bottom packing ratio the top of the groove difficulty, therefore in multiple filling, preceding The rate of face deposition needs to be less than the rate of any primary depositing below.

Then, Etching mask is formed by photoetching and etching, and position is removed via the opening etching of Etching mask Part above the first area of semiconductor substrate 101 so that second area of the shielded conductor 104 in semiconductor substrate 101 Top is laterally extended.

Then, the areas PXing Ti 107 are formed in semiconductor substrate 101, and the source region of N-type is formed in body area 107. The technique for being used to form body area 107 and source region 108 is, for example, multiple ion implanting.By selecting suitable dopant to form difference Then the doped region of type carries out thermal annealing with activator impurity.In ion implanting, using shielded conductor 104 and grid conductor 106 are used as hard mask, the lateral position in body area 107 and source region 108 can be limited, so as to save photoresist mask. The angle of the ion implanting is, for example, zero degree, i.e., relative to the surface vertical injection of semiconductor substrate 101.By controlling ion The energy of injection can limit the injection depth of body area 107 and source region 108, to limit upright position.

When forming body area 107, the dopant used can also be first to note B11 to note BF2 again, inject energy for B11 or BF2 Amount is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.Forming source region 108 When, for the dopant used for P+ or AS+, Implantation Energy is 60~150Kev, and implantation dosage is 1E14~1E16, thermal annealing temperatures It is 800 to 1100 degrees Celsius.

In this step, SGT structures are formed in groove 102, include that shielded conductor 104 and grid in groove is led Body 106.Grid conductor 106 includes the first part being located in groove 102, and semiconductor substrate 101 above extension the Two parts.The first part of grid conductor 106 is formed in the second opening 1242 of 104 both sides of shielded conductor, to which shielding is led Body 104 is clipped in the middle.It is isolated from each other by second insulating layer 123 between shielded conductor 104 and grid conductor 106.Shielded conductor 104 Lower part extend to the lower part of groove 102, be isolated each other by insulating laminate between semiconductor substrate 101, the insulating laminate Including the first insulating layer 122 and second insulating layer 123.Grid conductor 106 is adjacent with body area 107 and source region 108, and by grid Dielectric 105 is isolated from each other.

The separation layer 131 formed in above-mentioned steps surrounds shielded conductor 104 jointly with second insulating layer 123, further Improve the buffer action between shielded conductor 104 and grid conductor 106, to avoid via shielded conductor 104 and grid conductor The 106 source and drain short circuits occurred, improve reliability.

In step s 107, the dielectric layer 109 between the surface deposits of semiconductor structure, as shown in figure 3g.

Interlayer dielectric layer 109 covers the first area of semiconductor substrate 101 and second area interlayer dielectric layer 109 can be by It is formed selected from least one of silica, silicon nitride, silicon oxynitride, and can be single layer or laminated construction.In the reality It applies in example, interlayer dielectric layer 109 for example can be the boron-phosphorosilicate glass (BPSG) that thickness is 2000 to 15000 angstroms.

In step S108, is formed in interlayer dielectric layer 109 and reach source region 108, grid conductor 106 and shielded conductor 104 multiple contact holes 125, and contact zone 110 is respectively formed in the bottom of multiple contact holes 125 by ion implanting, such as Shown in Fig. 3 h.

The technique for being used to form contact hole 125 is, for example, dry etching.The sidewall slope of contact hole 125, such as relative to The angle that the top of vertical trench 102 is spent at 85 to 89.9 so that the bottom width of contact hole 125 is less than top width.Contact The angle in hole 125 is more oblique, the problems such as being conducive to the filling of subsequent conductive material, reduce defect caused by blind.

In the first area of semiconductor substrate 101 201, first group of contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109 and gate-dielectric 105, extend to the predetermined depth in shielded conductor 104, and second group of contact hole is worn successively Cross the predetermined depth in interlayer dielectric layer 109, gate-dielectric 105, the arrival body of source region 108 area 107.The predetermined depth is, for example, 0.1 to 1 micron.

In the second area 202 of semiconductor substrate 101, the third group contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109 extends to the predetermined depth in grid conductor 106.

In ion implanting, using interlayer dielectric layer as hard mask, the lateral position of contact zone 110 is limited, so as to To save photoresist mask.The dopant that the ion implanting uses can also be first to note B11 to note BF2 again for B11 or BF2, Implantation Energy is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.In ion After injection, thermal annealing can be carried out to activate dopant.

Further, in the second area 202 of semiconductor substrate 101, grid conductor 106 includes not only filling groove 102 first part and second part, and include from the third portion that groove 102 is laterally extended on 101 surface of semiconductor substrate Point.The Part III is as wiring layer.This mainly considers that the groove width of power semiconductor is limited.Screen in the trench It covers conductor 104 to be formed after contact hole, the contact hole in the first area 201 of semiconductor substrate 101 is intensive.In order to improve source region Electric isolution between 108 and grid conductor 106, using the Part III of grid conductor 106 as wiring layer so that the multiple In contact hole 125, the contact hole for source region may be located remotely from the contact hole of grid conductor 106, to reduce technology difficulty, provide The reliability of power semiconductor.

In step S109, source electrode 111 and gate electrode 112 are formed, as shown in figure 3i.

The step is for example including deposited metal layer and patterning.The metal layer for example by be selected from Ti, TiN, TiSi, W, One kind in AL, AlSi, AlSiCu, Cu, Ni or its composition of alloy.Metal layer pattern is melted into source electrode 111 by etching With gate electrode 112.As shown, source electrode 111 and gate electrode 112 are isolated from each other.

In the first area of semiconductor substrate 101 201, source electrode 111 is via in the multiple contact hole 125 One group of contact hole reaches shielded conductor 104, and source region 108 is reached via second group of contact hole in the multiple contact hole 125, from And source region 108 and shielded conductor 104 are electrically connected to each other.In the second area 202 of semiconductor substrate 101, gate electrode 112 Grid conductor 106 is reached via the third group contact hole in the multiple contact hole 125.

After step S109, the metallization of power semiconductor is had been carried out.Further, according to the needs of product, Passivation layer protection can be increased, complete the processing of power semiconductor Facad structure.By being thinned, carrying on the back a systems such as gold, scribing Row postchannel process completes the final realization of device.

Although should be noted that in above-mentioned sectional view, the shielded conductor 104 in different grooves is isolated from each other, and grid is led Body 106 is isolated from each other, however, in actual power semiconductor, from planar structure, the screen in above-mentioned difference groove Covering conductor 104 can be connected to each other, and grid conductor 106 can also be connected to each other.In one embodiment, the connection type is for example It is that grid conductor 106 in different grooves 102 is integrally formed by single conductive layer, and the shielded conductor in different grooves 102 104 are integrally formed by single conductive layer.In alternate embodiments, which is, for example, to utilize public source electrode will Shielded conductor 104 in different grooves 102 is connected to each other, and utilizes public gate electrode by the grid in different grooves 102 Pole conductor 106 is connected to each other.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including element.

For example above according to the embodiments of the present invention, there is no all details of detailed descriptionthe for these embodiments, also not Limit the specific embodiment that the utility model is only.Obviously, as described above, can make many modifications and variations.This explanation These embodiments are chosen and specifically described to book, is in order to preferably explain the principles of the present invention and practical application, to make Skilled artisan can utilize the utility model and modification on the basis of the utility model to use well.This Utility model is limited only by the claims and their full scope and equivalents.

Claims (9)

1. a kind of power semiconductor, which is characterized in that including：

Multiple grooves in semiconductor substrate, the semiconductor substrate are the first doping type；

Positioned at the areas the semiconductor substrate Zhong Ti, the body area is the second doping type adjacent to the multiple groove top, Second doping type is opposite with first doping type；

Source region in the body area, the source region are the first doping type；

Positioned at the insulating laminate of the multiple lower trench sidewalls and bottom, the insulating laminate includes the first insulating layer and second Insulating layer, first insulating layer surround the second insulating layer；

At least part is located at the shielded conductor in the multiple groove, and the shielded conductor extends above the multiple groove To its bottom, and it is isolated from each other by the insulating laminate between the semiconductor substrate；

It is located at the grid conductor of the shielded conductor both sides in the multiple groove top；

The source electrode being electrically connected with the source region and the shielded conductor；And

The gate electrode being electrically connected with the grid conductor,

Wherein, separation layer is formed at the top of the shielded conductor, by described between the grid conductor and the shielded conductor Separation layer is isolated from each other, and is isolated from each other by at least one layer in the insulating laminate, the grid conductor and the body area Between be isolated from each other by gate-dielectric, between the shielded conductor and the semiconductor substrate by the insulating laminate each other every From,

The grid conductor is used to reroute and is electrically connected with gate electrode with realizing.

2. power semiconductor according to claim 1, which is characterized in that the shielded conductor is served as a contrast from the semiconductor Bottom surface upwardly extends scheduled height.

3. power semiconductor according to claim 1, which is characterized in that the grid conductor further includes described half The second part being laterally extended on conductor substrate surface, the second part of grid layer conductor is as wiring so that the source electrode electricity Pole and the gate electrode are separated from each other.

4. power semiconductor according to claim 1, which is characterized in that the source electrode is located at first area In, the gate electrode is located in second area.

5. power semiconductor according to claim 1, which is characterized in that first insulating layer is by silica group At the second insulating layer is formed by being selected from least one of silicon nitride, nitrogen oxides or polysilicon.

6. power semiconductor according to claim 1, which is characterized in that the width of the multiple groove 0.2 to In the range of 10 microns, depth is in the range of 0.1 to 50 micron.

7. power semiconductor according to claim 1, which is characterized in that first doping type is N-type and p-type In one kind, second doping type be N-type and p-type in another kind.

8. power semiconductor according to claim 1, which is characterized in that the sidewall slope of the multiple groove makes The top width for obtaining the multiple groove is more than the bottom width of the multiple groove.

9. power semiconductor according to claim 1, which is characterized in that the power semiconductor be selected from One kind in cmos device, BCD devices, mosfet transistor, IGBT and Schottky diode.