CN111129123A

CN111129123A - Combined etching stop layer for contact field plate etching, integrated chip and forming method thereof

Info

Publication number: CN111129123A
Application number: CN201910454866.2A
Authority: CN
Inventors: 卢卉庭; 王培伦; 钟于彰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-10-30
Filing date: 2019-05-29
Publication date: 2020-05-08
Anticipated expiration: 2039-05-29
Also published as: TWI719430B; CN111129123B; TW201941428A

Abstract

The invention relates to an integrated chip. In some embodiments, an integrated chip has a gate structure disposed over a substrate between a source region and a drain region and a dielectric layer extending laterally from over the gate structure to between the gate structure and the drain region. A combined etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. The contact etch stop layer directly contacts the upper surface and sidewalls of the combined etch stop layer. A field plate is laterally surrounded by a first interlayer dielectric (ILD) layer, and extends from a top of the first ILD layer, through the contact etch stop layer, and into the combined etch stop layer. Embodiments of the invention also provide a combined etch stop layer for contact field plate etching and a method of forming an integrated chip.

Description

Combined etching stop layer for contact field plate etching, integrated chip and forming method thereof

Technical Field

Embodiments of the invention relate generally to the field of semiconductor technology and, more particularly, to a combined etch stop layer for contact field plate etching, an integrated chip, and methods of forming the same.

Background

Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). An Integrated Chip (IC) may use many different types of transistor devices depending on the application of the IC. In recent years, the ever-increasing market for cellular and RF (radio frequency) devices has led to a significant increase in the use of high voltage transistor devices. For example, high voltage transistor devices are commonly used in power amplifiers in RF transmit/receive chains due to the ability of the high voltage transistors to handle high breakdown voltages (e.g., greater than about 50V) and high frequencies.

Disclosure of Invention

According to an aspect of the present invention, there is provided an integrated chip including: a gate structure disposed over the substrate between the source region and the drain region; a dielectric layer extending laterally from over the gate structure to between the gate structure and the drain region; a combination etch stop layer comprising a plurality of different dielectric materials stacked over the dielectric layer; a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer; and a field plate laterally surrounded by a first interlayer dielectric (ILD) layer and extending vertically through the contact etch stop layer from a top of the first ILD layer and into the combined etch stop layer.

According to another aspect of the present invention, there is provided an integrated chip comprising: a gate structure disposed over the substrate; a resist protection oxide extending laterally from above the gate structure over an outermost sidewall of the gate structure; a combined etch stop layer comprising a first dielectric material over the etch-resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material; a plurality of conductive contacts laterally surrounded by a first interlayer dielectric (ILD) layer over the substrate; and a field plate extending from a top of the first interlayer dielectric layer to the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein the combined etch stop layer laterally contacts a sidewall of the field plate and vertically separates the field plate from the resist protection oxide.

According to yet another aspect of the present invention, there is provided a method of forming an integrated chip, comprising: forming a gate structure over a substrate between a source region and a drain region within the substrate; forming a dielectric layer over the gate structure and between the gate structure and the drain region; forming a combined etch stop layer over the dielectric layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials; forming a first inter-layer dielectric (ILD) layer over the combined etch stop layer; selectively etching the first interlayer dielectric layer to simultaneously define a contact opening extending to the substrate and a field plate opening extending to the combined etch stop layer; and filling the contact opening and the field plate opening with one or more conductive materials.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device having a field plate.

Fig. 2-4 show cross-sectional views of some additional embodiments of the disclosed high voltage lateral diffused mosfet (ldmos) device with a field plate.

Fig. 5-6 illustrate cross-sectional views of some embodiments of field plate biasing configurations of high voltage LDMOS devices implemented by metal interconnect wiring.

Fig. 7A-7C illustrate cross-sectional views of some embodiments of a high-voltage LDMOS device in different switch isolation configurations.

Fig. 8 shows a cross-sectional view of a high voltage transistor device with the source electrode of the field plate down (i.e., source electrode below).

Fig. 9A-9B illustrate some embodiments of the disclosed high-voltage LDMOS having a field plate on a metal line layer.

Fig. 10 illustrates some embodiments of a high voltage LDMOS device with a self-aligned drift region.

Fig. 11 illustrates a flow diagram of some embodiments of a method of forming a high voltage transistor device having a field plate.

Fig. 12-19 illustrate cross-sectional views of some embodiments of methods of forming a high voltage transistor device having a field plate.

Fig. 20-24 illustrate some embodiments of the disclosed high voltage transistor device having a combined etch stop layer defining a field plate.

Fig. 25-32 illustrate cross-sectional views of some embodiments of methods of forming a high voltage transistor device with a combined etch stop layer defining a field plate.

Fig. 33 illustrates a flow diagram of some embodiments of a method of forming a high voltage transistor device having a combined etch stop layer defining a field plate.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …", "below …", "below", "above …", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

High voltage transistor devices are typically constructed with field plates. The field plate is a conductive element, wherein the field plate is placed over the channel region to enhance performance of the high voltage transistor device by controlling the electric field generated by the gate electrode (e.g., reducing the peak electric field). By controlling the electric field generated by the gate electrode, the high voltage transistor device can achieve a higher breakdown voltage. For example, LDMOS (laterally diffused metal oxide semiconductor) transistor devices typically include a field plate that extends from a channel region to an adjacent drift region disposed between the channel region and a drain region.

The field plate can be formed in a number of different ways. For example, the field plate may be formed by a conductive gate material (e.g., polysilicon) extending from the gate electrode toward the drift region. However, in this configuration, the field plate is kept in line with the gate bias (bias), which increases the gate-to-drain capacitance (Cgd) and degrades the switching loss of the device. Alternatively, the conductive gate material can be patterned to form a separate field plate. This configuration reduces the gate-to-drain capacitance (Cgd), but the placement of the field plate is typically limited by design rules. In yet another alternative embodiment, non-gate materials may be used for field plate formation. However, this solution uses additional processing steps, which increase the manufacturing cost of the resulting integrated chip.

The present invention therefore relates to a high voltage transistor device having a field plate made of non-gate material, wherein the field plate is formed simultaneously with the formation of back end of line (BEOL) metal layers to enable a low cost manufacturing method. In some embodiments, a high voltage transistor device has a gate electrode disposed on a substrate between a source region and a drain region within the substrate. The dielectric layer extends laterally from over the gate electrode to a drift region disposed between the gate electrode and the drain region. The field plate is located within a first interlayer dielectric (ILD) layer overlying the substrate. The field plate extends laterally from over the gate electrode to over the drift region and vertically from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts of the same material as the field plates extend vertically from the bottom surface of the first ILD layer to the top surface of the first ILD layer.

Fig. 1 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device 100 having a field plate 122.

The high voltage transistor device 100 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate. The semiconductor substrate 102 has a first doping type, while the source region 104 and the drain region 106 have a second doping type, having a higher doping concentration than the semiconductor substrate 102. In some embodiments, the first doping type is n-type doping and the second doping is p-type doping.

A gate structure 116 is disposed over the semiconductor substrate 102 at a location laterally disposed between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. Upon receiving a bias voltage, the gate electrode 108 is configured to generate an electric field to control movement of charge carriers within a channel region 112 laterally disposed between the source region 104 and the drain region 106. For example, during operation, the gate-source voltage (V)_GS) May be selectively applied to the gate electrode 108 relative to the source region 104 to form a conductive channel in the channel region 112. At application of V_GSTo form a conductive channel, a drain-source voltage (V) is applied_DS) To move charge carriers (e.g., as indicated by arrows 105) between the source region 104 and the drain region 106.

The channel region 112 extends laterally from the source region 104 to an adjacent drift region 114 (e.g., a drain extension region). The drift region 114 includes a second doping type having a relatively low doping concentration to provide a higher resistance at high operating voltages. A gate structure 116 is disposed over the channel region 112. In some embodiments, the gate structure 116 may extend from above the channel region 112 to a position above a portion of the drift region 114.

A first interlayer dielectric (ILD) layer 118 is disposed over the semiconductor substrate 102. One or more conductive metal structures are disposed within ILD layer 118. In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 configured to provide vertical connections between the source regions 104, the drain regions 106, or the gate electrodes 108 and a first back-end-of-line (BEOL) metal line layer 128, wherein the first back-end-of-line (BEOL) metal line layer 128 is disposed within the second ILD layer 126 above the first ILD layer 118.

The one or more conductive metal structures may further include a field plate 122 disposed within the first ILD layer 118 at a location above the gate electrode 108 and a portion of the drift region 114. The field plate 122 comprises the same conductive material as the plurality of contacts 120. The field plate 122 may be disposed over a dielectric layer 124, wherein the dielectric layer 124 is configured to separate the field plate 122 from the drift region 114 and the gate electrode 108. In some embodiments, the dielectric layer 124 extends laterally across the field plate 122 in one or more directions.

During operation, the field plate 122 is configured to act on an electric field generated by the gate electrode 108. The field plate 122 may be configured to alter a distribution of an electric field generated by the gate electrode 108 in the drift region 114, thereby enhancing an internal electric field of the drift region 114 and increasing a drift doping concentration of the drift region 114, thereby enhancing a breakdown voltage capability of the high voltage transistor device 100.

Fig. 2 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device, including a high voltage laterally diffused mosfet (ldmos) device 200 having a field plate 214.

The LDMOS device 200 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, while the source region 104 and the drain region 106 comprise highly doped regions of a second doping type different from the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type. In some embodiments, the doping concentration of the source region 104 and the drain region 106 may be about 10¹⁹cm^-3And is largeAbout 10²⁰cm^-3Within the range of (a).

A contact region 208 (e.g., a P-type tap or an n-type tap) having a first doping type (e.g., P + doping) laterally abuts the source region 104. The contact region 208 provides an ohmic connection to the semiconductor substrate 102. In some embodiments, the doping concentration of the contact region 208 may be about 10¹⁸cm^-3And about 10²⁰cm^-3Within the range of (a). The contact region 208 and the source region 104 are disposed within the body region 202. The body region 202 has a first doping type and a doping concentration higher than the doping concentration of the semiconductor substrate 102. For example, the doping concentration of the semiconductor substrate 102 may be about 10¹⁴cm^-3And about 10¹⁶cm^-3And the doping concentration of the body region 202 may be about 10¹⁶cm^-3And about 10¹⁸cm^-3Within the range of (a) to (b).

The drain region 106 is disposed within a drift region 204, which is disposed within the semiconductor substrate 102 at a location laterally adjacent to the body region 202. The drift region 204 comprises a second doping type having a relatively low doping concentration, wherein the drift region 204 provides a higher resistance when the LDMOS device 200 is operated at high voltage. In some embodiments, the doping concentration of the drift region 204 may be about 10¹⁵cm^-3And about 10¹⁷cm^-3Within the range of (a) to (b).

A gate structure 210 is disposed over the semiconductor substrate 102 at a location laterally disposed between the source region 104 and the drain region 106. In some embodiments, the gate structure 210 may extend laterally from above the body region 202 to a position above a portion of the drift region 204. The gate structure 210 includes a gate electrode 108, the gate electrode 108 being separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may comprise silicon dioxide (SiO)₂) Or a high-k gate dielectric material and the gate electrode 108 may comprise a polysilicon or metal gate material (e.g., aluminum). In some embodiments, the gate structure 210 may further include a gate electrode 108 disposed on opposite sides of the gate electrodeSidewall spacers 212. In some embodiments, the sidewall spacers 212 may comprise nitride-based sidewall spacers (e.g., comprising SiN) or oxide-based sidewall spacers (e.g., SiO)₂SiOC, etc.).

One or more dielectric layers 124 are disposed over the gate electrode 108 and the drift region 204. In some embodiments, the one or more dielectric layers 124 extend continuously from over a portion of the gate electrode 108 to over a portion of the drift region 204. In some embodiments, one or more dielectric layers 124 may be conformally disposed on the drift region 204, the gate electrode 108, and the sidewall spacers 212.

A field plate 214 is disposed over the one or more dielectric layers 124 and is laterally surrounded by the first ILD layer 118. The field plate 214 extends from over the gate electrode 108 to over the drift region 204. The size of the field plate 214 may vary depending on the size and characteristics of the LDMOS device 200. In some embodiments, the field plate 214 may have a dimension between about 50 nanometers and about 1 micron. In other embodiments, the field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may comprise a dielectric material having a relatively low dielectric constant (e.g., less than or equal to about 3.9) that provides electrical isolation between the plurality of contacts 120 and/or the field plates 122. In some embodiments, the first ILD layer 118 may comprise an ultra-low k dielectric material or a low k dielectric material (e.g., SiCO).

The field plates 214 extend vertically from the dielectric layer 124 to the top surface of the first ILD layer 118. In some embodiments, the field plates 214 may extend vertically to a height greater than or equal to the height of the contacts 120 and the top surface of the first ILD layer 118. The field plate 122 has a non-planar surface that abuts one or more dielectric layers 124. The non-planar surface causes the field plate 122 to have a first thickness t in the region above the gate electrode 108₁And has a thickness t greater than the first thickness t in the region overlying the drift region 204₁Second thickness t₂。

A plurality of contacts 120 are also surrounded by the first ILD layer 118. The plurality of contacts 120 may include a first contact 120a coupled to the contact region 208, a second contact 120b coupled to the drain region 106, and a third contact 120c coupled to the gate electrode 108. In some embodiments, the first contact 120a may include a mating contact (not shown) in contact with the contact region 208 and the source region 104. In some embodiments, the plurality of contacts 120 and the field plate 122 may comprise the same metallic material. For example, the plurality of contacts 120 and the field plate 122 may include one or more of tungsten (W), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), aluminum copper (AlCu), copper (Cu), and/or other similar conductive materials.

Fig. 3 shows a cross-sectional view of some additional embodiments of the disclosed high-voltage LDMOS device 300 with the field plate 214.

The LDMOS device 300 comprises an isolation region 302, the isolation region 302 being provided within the drift region 204 at a position laterally arranged between the gate structure 214 and the drain region 106. The isolation region 302 improves the isolation between the gate structure 210 and the drain region 106 in order to prevent dielectric breakdown between the gate structure 210 and the drift region 204 when the LDMOS device 300 is operated at a large operating voltage. For example, the isolation region 302 may be introduced into the drift region 204 of the LDMOS device designed to operate at a first breakdown voltage to increase the breakdown voltage of the LDMOS device 300 without significantly changing the manufacturing process of the LDMOS device. In some embodiments, the isolation region 302 may include a Shallow Trench Isolation (STI). In other embodiments, the isolation region 302 may include field oxide.

Fig. 4 shows a cross-sectional view of some additional embodiments of the disclosed high-voltage LDMOS device 400 with a field plate 408.

The LDMOS device 400 includes a plurality of dielectric layers 402 to 404 arranged between the field plate 408 and the gate structure 210 and/or the drift region 204. The plurality of dielectric layers 402-404 are configured to electrically isolate the field plate 408 from the gate structure 210 and/or the drift region 204. In an embodiment, the plurality of dielectric layers 402-404 may include two or more different dielectric materials. In some embodiments, the plurality of dielectric layers 402-404 may include one or more dielectric layers used during a typical CMOS fabrication process in order to limit additional fabrication steps for electrically isolating the field plate 408 from the gate structure 210 and/or the drift region 204.

For example, the plurality of dielectric layers 402-404 may include a silicide block layer 402. In some embodiments, silicide-block layer 402 may include a Resist Protective Oxide (RPO) layer configured to prevent silicide formation. A silicide block layer 402 may be disposed over portions of the gate electrode 108 and the drift region 204. In some embodiments, the silicide block layer 402 may extend continuously from over the gate electrode 108 to over the drift region 204.

In some embodiments, the plurality of dielectric layers 402-404 may also include a field plate Etch Stop Layer (ESL) 404. A field plate ESL 404 may be disposed over the silicide-block layer 402 and configured to control etching of the opening of the field plate 408. The field plate ESL 404 can account for differences in etch depth and/or differences in etch rate (e.g., due to etch loading effects) between the contact 120 and the field plate 408. In some embodiments, the field plate ESL 404 may comprise a layer of silicon nitride (SiN), for example.

In some alternative embodiments (not shown), the plurality of dielectric layers 402-404 may additionally or alternatively include a gate dielectric layer. In such embodiments, the gate dielectric layer may be disposed laterally adjacent to the gate structure 210 at a location overlying the drift region 204. In some embodiments, the dielectric layer of oxide may comprise silicon dioxide (e.g., SiO)₂) Or a high-k gate dielectric material. In other embodiments, the plurality of dielectric layers 402-404 may additionally or alternatively include an ILD layer (e.g., the first ILD layer 118).

A Contact Etch Stop Layer (CESL)406 is disposed over the semiconductor substrate 102 and the field plate ESL 404. In some embodiments, the CESL406 extends over the semiconductor substrate 102 at a location between the plurality of contacts 120 and the field plate 408 such that the CESL406 abuts a sidewall of the plurality of contacts 120 and the field plate 408. CESL406 covers the gate structure 210. In some embodiments, CESL406 may also cover the plurality of dielectric layers 402-404. In other embodiments, one or more of the plurality of dielectric layers 402-404 (e.g., field plate ESL 404) may cover CESL 406. In some embodiments, CESL406 may include a nitride layer. For example, CESL406 may include silicon nitride (SiN).

A field plate 408 is disposed within the first ILD layer 118, adjacent the CESL406 and adjacent one or more of the plurality of dielectric layers 402-404. In some embodiments, the field plate 408 extends through the CESL406 to abut one or more of the plurality of dielectric layers 402-404. In such embodiments, one or more of the plurality of dielectric layers 402-404 separates the field plate 408 from the gate structure 210 and the drift region 204.

In some embodiments, the field plate 408 may include a first metallic material 410 and a second metallic material 412. The first metallic material 410 may include a glue layer disposed along an outer edge of the field plate 408, while the second metallic material 412 is embedded within the first metallic material 410 in an interior region of the field plate 408 (i.e., the second metallic material 412 is separated from the CESL406 by the first metallic material 410). In some embodiments, a liner layer 414 may be disposed between the first ILD layer 118 and the first metal material 410.

In some embodiments, the first metallic material 410 disposed along the outer edge of the field plate 408 has a top surface that is disposed along a substantially planar surface 420 (i.e., a planar surface formed by a planarization process). The planar surface 420 may be aligned with a top surface of the plurality of contacts 120. In some embodiments, the first metallic material 410 includes the same material as the plurality of contacts 120 and the second metallic material 412 includes the same material as the first metallic wire layer 418 covering the plurality of contacts 120. For example, in some embodiments, the first metallic material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).

It should be appreciated that the disclosed field plate, due to its integration with BEOL (back end of line) metallization layers, allows for a variety of field plate bias configurations that are easily implemented for different design considerations. For example, the field plate bias can be changed by changing the metal wiring layer rather than by changing the design of the disclosed high voltage device. Furthermore, it should be appreciated that biasing the high voltage transistor devices through BEOL metal interconnect wiring allows for integration of various field plate biasing configurations on the same chip using a single fabrication process flow.

Fig. 5-6 illustrate cross-sectional views of some embodiments of field plate bias configurations for high voltage transistor devices implemented with BEOL metal interconnect wiring. Although fig. 5-6 show connection between the field plate 214 and the contact region 208 or gate electrode 108 through a first metal line layer (e.g., 504 or 604), BEOL metal interconnect wiring is not so limited. More specifically, it should be understood that the field plate 214 can be connected to a source region, a gate electrode, a drain region, or a body contact through any combination of BEOL metal interconnect layers (e.g., a first metal line layer, a first metal via layer, a second metal line layer, etc.).

Fig. 5 shows a cross-sectional view of a high-voltage LDMOS device 500 in which field plate 214 is electrically coupled to contact region 208 along conductive path 506. The field plates 214 connect to a first metal line layer 504 disposed within the second ILD layer 502. The first metal wire layer 504 is coupled to the contact 120a that abuts the contact area 208. By electrically coupling the field plate 214 to the contact region 208, the field plate 214 is biased by a source voltage. The high-voltage LDMOS device 500 is provided with low on-resistance rds (on) and low dynamic power consumption (e.g., low rds (on) Qgd and BV (i.e., breakdown voltage)) by the source voltage bias field plate 214. Low dynamic power consumption provides good performance during high frequency switching applications.

Fig. 6 shows a cross-sectional view of a high-voltage LDMOS device 600 in which the field plate 214 is electrically coupled to the gate electrode 108 along a conductive path 606. The field plates 214 connect to a first metal line layer 604 disposed within the second ILD layer 602. The first metal wire layer 604 is connected to a contact 120b that abuts the gate electrode 108. By electrically coupling the field plate 214 to the gate electrode 108, the field plate 214 is biased by the gate voltage. The high-voltage LDMOS device 600 is provided with a low rds (on) and breakdown voltage by the gate voltage bias field plate 214.

Various field plate biasing configurations allow the disclosed field plates to form a universal high voltage transistor device that can be used in different applications. For example, the on-state resistance rds (on) of a high voltage transistor device with a gate bias field plate is lower than the rds (on) of a high voltage transistor device with a source bias field plate. However, rds (on) Qgd for high voltage transistor devices with source bias field plates is lower than rds (on) Qgd for high voltage transistor devices with gate source bias field plates. Thus, a high-voltage transistor device having a gate bias field plate (e.g., the high-voltage LDMOS device 500) may be used for low frequency switching applications (e.g., below 10MHz), while a high-voltage transistor device having a source bias field plate (e.g., the high-voltage LDMOS device 600) may be used in high frequency switching applications (e.g., above 10 MHz).

Fig. 7A-7C illustrate cross-sectional views of some embodiments of high-voltage LDMOS devices 700 a-700C in different switch isolation configurations.

As shown in fig. 7A, the high-voltage LDMOS device 700a is configured as a low-side switch (e.g., a switch connected to ground in an inverter). In such a configuration, the high-voltage LDMOS device 700a has the source region 104 floating so that the voltage on the source region 104 can change during the transition period.

As shown in fig. 7B, the high-voltage LDMOS device 700B is configured as a high-side switch (e.g., a switch connected to VDD in the converter). In such a configuration, the high-voltage LDMOS device 700b has the source region 104 connected to a source voltage. The high-voltage LDMOS device 700b has a drift region 702 extending below the body region 202 to prevent the source voltage from rising above the substrate voltage by preventing charge carriers from being transported from the contact region 208 into the semiconductor substrate 102 (e.g., by tunneling).

As shown in fig. 7C, the high-voltage LDMOS device 700C is completely isolated from the substrate to allow independent biasing. The high voltage transistor device 700c includes a deep well 704 configured to provide vertical isolation and an underlying buried layer 706 of opposite doping. In some embodiments, the deep well 704 may have a first doping type (e.g., the same doping type as the body region 202), and the buried layer 706 may have a second doping type.

The high-voltage LDMOS device 700c further comprises one or more additional STI regions 206 laterally separating the drain region from the body region 708 and the buried layer 710, wherein the buried layer 710 has the second doping type. A body region 708 overlies the deep well 704 and a buried layer 710 overlies a well region 712 having the second doping type and abutting the buried layer 706. The contact 120 is configured to provide a bias voltage to the body region 708 and the buried layer 710 so as to form junction isolation between the deep well 704 and the buried layer 706 and the well region 712. Junction isolation allows the fully isolated high-voltage LDMOS device 700c to operate over a range of bias voltages.

Fig. 8 shows a cross-sectional view of a source-down high voltage transistor device 800 with a field plate 214.

The high-voltage transistor device 800 includes a substrate 802 having a first doping type (e.g., p + doping type) with a high doping concentration. Source region 804 is disposed along a back side 802b of substrate 802. In various embodiments, source region 804 may comprise a highly doped region or a metal layer. An epitaxial layer 806 having a first conductivity type is disposed on the front side surface 802f of the substrate 802. The dopant concentration of epitaxial layer 806 is less than the dopant concentration of substrate 802. The source contact region 810, the drain region 106, the body region 808, and the drift region 204 are disposed within the top surface of the epitaxial layer 806.

Conductive material 812 extends from the top surface of epitaxial layer 806 into substrate 802. Conductive material 812 may include a highly doped deep well region. The conductive material 812 allows source connections to be made from the back side of the substrate 802, thereby reducing metal routing complexity and achieving various package compatibilities. In some embodiments, the field plate 214 can be biased by a source voltage by an electrical path 818, where the electrical path 818 extends through a contact 814 abutting the conductive material 812 and the overlying metal line layer 816 coupled to the field plate 214.

Fig. 9A-9B illustrate some embodiments of the disclosed high-voltage LDMOS device with a field plate 902 in a metal line layer. Although fig. 9A-9B show the field plate on the first metal line layer, it should be understood that the disclosed field plate is not limited to the first metal line layer, but may be implemented on alternative layers of the BEOL metallization stack.

As shown in the cross-sectional view 900 of fig. 9A, the field plates 902 are disposed in a first metal line layer within a second ILD layer 904 that covers the first ILD layer 118. In some embodiments, the field plate 902 has substantially planar top and bottom surfaces to provide a planar topology for the field plate 902. The field plate 902 is vertically separated from the gate structure 210 and the drift region 204 by the first ILD layer 118. The field plate 902 covers the gate electrode 108 and a portion of the drift region 204 and is laterally separated from the source region 104 and the drain region 106. For example, the field plate 902 may be laterally separated from the drain region 106 by a distance d. In some embodiments, the field plate 902 may extend laterally from over the gate electrode 108 to over the drift region 204.

As shown in the top view 906 of fig. 9B, the field plate 902 includes a metal structure that covers the gate electrode 108 and a portion of the drift region 204. The metal structure is not connected to an underlying element or another metal structure on the first metal line layer through a contact 120. More specifically, the metal structure will be connected to an overlying via (not shown) that is configured to connect the field plate to an overlying metal line layer so that the field plate 902 can be biased.

Fig. 10 illustrates some embodiments of the disclosed high voltage LDMOS device 1000 with a self-aligned drift region 1002.

The self-aligned drift region 1002 has sidewalls 1002s, the sidewalls 1002s being substantially aligned with sidewalls of the gate electrode 108 and the gate dielectric layer 110. In some alternative embodiments, the self-aligned drift region 1002 may be formed to have sidewalls 1002s that are substantially aligned with the edges of the sidewall spacers 212. By aligning the self-aligned drift region 1002 with the sidewalls of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 and the spacing s are laterally spaced from the body region 202, thereby minimizing gate-to-drain overlap and achieving low gate-to-drain charge (Qgd) and good high frequency performance. The field plate 214 covering the self-aligned drift region 1002 can further reduce the gate-drain charge (Qgd).

Fig. 11 illustrates a flow diagram of some embodiments of a method 1100 of forming a high voltage transistor device having a field plate. The method can form the field plate using process steps already used during a standard CMOS fabrication process, and thus can provide a low cost universal field plate.

While the disclosed methods (e.g., methods 1100 and 3300) are illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and/or phases.

At act 1102, a substrate is provided having a source region and a drain region separated by a channel region. In some embodiments, the substrate may further include a drift region interposed between the source region and the drain region at a position adjacent to the channel region.

At act 1104, a gate structure is formed on the substrate at a location disposed between the source region and the drain region. The gate structure may include a gate dielectric layer and an overlying gate electrode.

At act 1106, a drift region can be formed using a self-aligned process that, in some embodiments, selectively implants a semiconductor substrate according to a gate structure to form a drift region.

At act 1108, one or more dielectric layers are selectively formed over the gate electrode and a portion of the drift region.

At act 1110, a Contact Etch Stop Layer (CESL) and a first interlayer dielectric (ILD) layer are formed over a substrate.

At act 1112, the first ILD layer is selectively etched to define contact openings and field plate openings.

At act 1114, the contact opening and the field plate opening are filled with a first metallic material.

At act 1116, a planarization process may be performed to remove excess first metal material overlying the first ILD layer.

At act 1118, a second metal material corresponding to the first metal line layer is deposited. In some embodiments, the second metallic material may further fill the field plate opening. In such an embodiment, the second metallic material is embedded within the first metallic material within the field plate opening.

At act 1120, a second inter-layer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line level structure.

Fig. 12-19 illustrate cross-sectional views of some embodiments of methods of forming MOSFET devices with field plates. While fig. 12-19 are described with respect to method 1100, it should be understood that the structures shown in fig. 12-19 are not limited to this method, but may stand alone as structures independent of the method.

Fig. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to act 1102.

As shown in cross-sectional view 1200, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be inherently doped with a first doping type. In various embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., silicon, SOI) including, but not limited to, a semiconductor die or wafer or one or more dies on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith.

The semiconductor substrate 102 may be selectively implanted using various implantation steps to form a plurality of implant regions (e.g., well regions, contact regions, etc.). For example, the semiconductor substrate 102 may be selectively implanted to form the body region 202, the drift region 204, the source region 104, the drain region 106, and the contact region 208. The plurality of implant regions may be formed by selectively masking the semiconductor substrate 102 (e.g., using a photoresist mask) and then introducing high energy dopants 1204 (e.g., p-type dopant species such as boron or n-type dopants such as phosphorous) into the exposed regions of the semiconductor substrate 102. For example, as shown in cross-sectional view 1200, masking layer 1202 is selectively patterned to expose portions of semiconductor substrate 102, into which high energy dopants 1204 are subsequently implanted to form source region 104 and drain region 106.

It should be understood that the implant region shown in cross-sectional view 1200 is one example of a possible implant region, and that the semiconductor substrate 102 may include other configurations of implant regions, such as any of the configurations shown in fig. 1-10.

Fig. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to act 1104.

As shown in cross-sectional view 1300, a gate structure 210 is formed over semiconductor substrate 102 at a location disposed between source region 104 and drain region 106. The gate structure 210 may be formed by forming a gate dielectric layer 110 over the semiconductor substrate 102 and by forming a gate electrode material 108 over the gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 and the gate electrode material 108 may be deposited by a vapor deposition technique. The gate dielectric layer 110 and gate electrode material 108 may then be patterned and etched (e.g., according to a photoresist mask) to define the gate structure 210. In some embodiments, the sidewall spacers 112 may be formed on opposite sides of the gate electrode 108 by: a nitride-based material or an oxide-based material is deposited onto the semiconductor substrate 102 and selectively etched to form the sidewall spacers 112.

Fig. 14 illustrates some embodiments of a cross-sectional diagram 1400 corresponding to act 1108.

As shown in cross-section 1400, one or more dielectric layers 124 are selectively formed over the gate electrode 108 and drift region 204. In some embodiments, the one or more dielectric layers 124 may be deposited by a vapor deposition technique and then patterned and etched (e.g., according to a photoresist mask). In some embodiments, one or more dielectric layers 124 may be etched to expose a portion of the gate electrode 108 and laterally spaced apart from the drain region 106.

In some embodiments, one or more of the dielectric layers 124 may include a silicide blocking layer, such as a Resist Protective Oxide (RPO) layer. In other embodiments, one or more of the dielectric layers 124 may further and/or optionally include a field plate Etch Stop Layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by a vapor deposition technique. In other embodiments, the one or more dielectric layers 124 may further and/or optionally include a gate dielectric layer or an inter-layer dielectric (ILD) layer.

Fig. 15 illustrates some embodiments of a cross-sectional view 1500 corresponding to act 1110.

As shown in cross-sectional view 1500, a Contact Etch Stop Layer (CESL)1502 is formed on semiconductor substrate 102. In some embodiments, CESL 1502 may be formed by a vapor deposition process. A first interlayer dielectric (ILD) layer 1504 is then formed on the CESL 1502. In some embodiments, the first ILD layer 1504 may comprise an ultra-low k dielectric material or a low k dielectric material (e.g., SiCO). In some embodiments, the first ILD layer 1504 may also be formed by a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin-on process. It should be understood that the term "interlayer dielectric (ILD) layer" as used herein may also refer to an inter-metal dielectric (IMD) layer.

FIG. 16 illustrates some embodiments of a cross-sectional view 1600 corresponding to act 1112.

As shown in cross-sectional view 1600, the first ILD layer 1504 is selectively exposed to a first etchant 1602, wherein the first etchant 1602 is configured to form a contact opening 1606 and a field plate opening 1608. In some embodiments, the contact opening 1606 may be smaller than the field plate opening 1608. In some embodiments, the first ILD layer 1504 is selectively exposed to the first etchant 1602 according to a mask layer 1604 (e.g., a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have a large etch selectivity between the first ILD layer 1504 and the field plate ESL within the one or more dielectric layers 124. In some embodiments, the first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may have a composition including oxygen (O)₂) Nitrogen (N)₂) Hydrogen (H)₂) Argon (Ar) and/or fluorine species (e.g., CF)₄、CHF₃、C₄F₈Etc.) may be used. In other embodiments, the first etchant 1602 may include a wet etchant containing diluted hydrofluoric acid (BHF).

Fig. 17 illustrates some embodiments of a cross-sectional view 1700 corresponding to acts 1114 through 1116.

As shown in cross-sectional view 1700, contact opening 1606 and field plate opening 1608 are filled with first metallic material 1702. In some embodiments, the first metallic material 1702 may be deposited by a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, the first metal material 1702 may be formed by physical vapor deposition of a seed layer followed by a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove the excess first metal material 1702 and form a planar surface along the lines 1704.

In some embodiments, the first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, a diffusion barrier layer and/or liner layer may be deposited into the contact opening 1606 and field plate opening 1608 prior to depositing the first metallic material 1702.

Fig. 18 illustrates some embodiments of a cross-sectional view 1800 corresponding to act 1118.

As shown in cross-section 1800, a second metallic material 1802 is deposited. A second metal material 1802 is formed within the remaining ones of the field plate openings and over the first ILD layer 118. In some embodiments, the second metallic material 1802 can be deposited by a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, the second metallic material 1802 may be formed by physical vapor deposition of a seed layer followed by a plating process. In some embodiments, the second metallic material 1802 may include copper (Cu) or an aluminum copper (AlCu) alloy.

After formation, the second metal material 1802 can be selectively patterned to define one or more metal structures overlying the first metal line layer 418 of the first ILD layer 118. In some embodiments, the second metal material 1802 may be selectively patterned by forming a patterned mask layer (e.g., a photoresist layer or a hard mask layer) (not shown) on the second metal material 1802 and then etching the second metal material 1802 in the areas exposed by the patterned mask layer.

FIG. 19 illustrates some embodiments of a cross-sectional diagram 1900 corresponding to act 1120.

As shown in cross-sectional view 1900, a second ILD layer 416 is formed over the first ILD layer 118 and the one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may be formed by depositing a second ILD material on the one or more metal structures of the first ILD layer 118 and the first metal line layer 418. After forming the second ILD layer 416, a planarization process (e.g., CMP) is performed to remove the excess second ILD layer 416 and expose the top surface of the one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may comprise an ultra-low k dielectric material or a low k dielectric material (e.g., SiCO) formed by a vapor deposition process or a spin-on process.

It is to be understood that the height differences of the plurality of contacts (e.g., 120) and the field plates (e.g., 122) can cause difficulties during fabrication of the disclosed transistor devices. For example, because the field plates (e.g., 122) are formed over the dielectric layer 124 (e.g., resist protection oxide), the field plates (e.g., 122) have a smaller height than the plurality of contacts (e.g., 120). However, the field plate (e.g., 122) and the plurality of contacts (e.g., 120) are formed using the same etch process. The height difference can result in over-etching of the field plate opening (e.g., 1608 in fig. 16) that can result in a short circuit between the field plate (e.g., 122) and the conductive channel of the transistor device, or under-etching of the contact opening (e.g., 1606 in fig. 16) that can result in poor connection between the plurality of contacts (e.g., 120) and the source region (e.g., 104), the drain region (e.g., 106), and/or the gate structure (e.g., 210).

To prevent over-etching of the field plate opening or under-etching of the contact opening, in some embodiments, a combination etch stop layer may be used to control the etch depth of the field plate opening. By controlling the etch depth of the field plate opening, the combination etch stop layer allows multiple contacts (e.g., 120) and field plates (e.g., 122) to be precisely formed to different heights.

Fig. 20 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device 200 with a combined etch stop layer defining a field plate.

The high voltage transistor device 2000 includes a gate structure 116 disposed over a semiconductor substrate 102. The gate structure 116 includes a gate dielectric layer 110 and an overlying gate electrode 108. In some embodiments, the gate structure 116 may have a first thickness th in a range between about 1000 angstroms and about 2000 angstroms₁. Source region 104 and drain region 106 in the same phase of gate structure 116Disposed in the semiconductor substrate 102 on the opposite side.

A Resist Protection Oxide (RPO)2002 is disposed over the gate structure 116. The RPO2002 extends laterally from directly above the gate structure 116 across the outermost sidewalls of the gate structure 116. In some embodiments, RPO2002 may extend vertically from an upper surface of the gate structure to an upper surface of semiconductor substrate 102 and laterally from directly above gate structure 116 to between gate structure 116 and drain region 106. In some embodiments, RPO2002 may comprise silicon dioxide, silicon nitride, or the like. In some embodiments, RPO2002 may have a second thickness th in a range between about 100 angstroms and about 1000 angstroms₂。

A combined etch stop layer 2004 is disposed over the RPO 2002. In some embodiments, combined etch stop layer 2044 directly contacts one or more upper surfaces of RPO 2002. A first interlayer dielectric (ILD) layer 118 and a field plate 122 are disposed over the combined etch stop layer 2004. The first ILD layer 118 surrounds a field plate 122 and a plurality of contacts 120, wherein the plurality of contacts 120 are coupled to the source region 104, the drain region 106, and the gate structure 116. In some embodiments, the field plate 122 and the plurality of contacts 120 may include a diffusion barrier layer (not shown) surrounding a conductive core comprising one or more metals.

The combined etch stop layer 2004 includes a plurality of different dielectric layer materials 2006-2008 stacked over the RPO 2002. In some embodiments, the plurality of different dielectric materials 2006-2008 can have outermost sidewalls that are substantially aligned along a line perpendicular to the upper surface of the semiconductor substrate 102. In some embodiments, the plurality of different dielectric materials 2006-2008 may have outermost sidewalls that are substantially aligned with outermost sidewalls of RPO 2002. In such embodiments, the first width of RPO2002 has a second width substantially equal to combined etch stop layer 2004. The plurality of different dielectric materials 2006-2008 have different etch properties, thereby providing respective ones of the plurality of different dielectric materials 2006-2008 having different etch selectivities relative to the etchant. The different etch selectivity allows the combination etch stop layer 2004 to slowly etch the field plate opening (e.g., the opening defining the field plate 122) and, thus, closely control the height of the field plate and enable a height difference between the plurality of contacts 120 and the field plate 122 (e.g., such that the plurality of contacts 120 have a higher height than the field plate 122).

For example, in some embodiments, the bottom of the field plate 122 contacts the combined etch stop layer 2004 along an interface vertically above a bottom surface of one or more of the plurality of contacts 120 (e.g., contacts coupled to the source region 104 and the drain region 106). In such an embodiment, the combination etch stop layer 2004 reduces the etch rate of the etchant used to form the field plate opening (i.e., the opening defining the field plate 122) during the fabrication of the high voltage transistor device 2000. The reduced etch rate results in the bottom surface of the field plate 122 being higher than the bottom surface of the one or more contacts 120.

In some embodiments, the combined etch stop layer 2004 may include a first dielectric material 2006 directly contacting an upper surface of the RPO2002 and a second dielectric material 2008 directly contacting an upper surface of the first dielectric material 2006. In some embodiments, the first dielectric material 2006 can have a third thickness th₃And the second dielectric material 2008 may have a fourth thickness th₄. In some embodiments, RPO2002 and combined etch stop layer 2004 may each have a substantially constant thickness between the outermost sidewalls. If the third thickness th₃And a fourth thickness th₄Too small (e.g., less than the minimum value set forth below), the combined etch stop layer 2004 may not effectively stop the etch that forms the field plate opening. If the third thickness th₃And a fourth thickness th₄Too large (e.g., greater than the maximum values set forth below), the effect of the field plate 122 on the high-voltage transistor device 2000 is reduced, thereby negatively impacting device performance.

In some embodiments, the first dielectric material 2006 can include silicon nitride (Si)_xN_y) And the second dielectric material 2008 may include silicon dioxide (SiO)₂). In such an embodiment, the first thickness th₁May be in a first range between about 50 angstroms and about 400 angstroms, and a second thickness th₂May be in a second range between about 150 angstroms and about 700 angstroms. In other placesIn an embodiment, the first dielectric material 2006 can include or be silicon dioxide (SiO)₂) And the second dielectric material 2008 may include or be silicon nitride (Si)_xN_y) Or silicon oxynitride (SiO)_xN_y). In such an embodiment, the first thickness th₁May be in a first range between about 600 angstroms and about 900 angstroms. In some embodiments, the second thickness th₂May be in a second range between about 100 angstroms and about 500 angstroms.

Fig. 21A-21B illustrate some additional embodiments of the disclosed high voltage transistor device with a combined etch stop layer defining a field plate.

As shown in cross-sectional view 2100 of fig. 21A, the high voltage transistor device includes a semiconductor substrate 102 having a body region 2106 disposed within a drift region 2104 over a substrate 2102. The source region 104 is disposed within the body region 2106 and the drain region 106 is disposed within the drift region 2104. In some embodiments, the source region 104, the drain region 106, and the drift region 2104 may have a first doping type (e.g., n-type), while the body region 2106 and the substrate 2102 have a second doping type (e.g., p-type) opposite the first doping type. In some embodiments, the source region 104 and the drain region 106 may include highly doped regions (i.e., n + regions) having a higher doping concentration than the doping concentration of the drift region 2104.

A gate structure 116 is disposed above the semiconductor substrate 102 between the source region 104 and the drain region 106. The RPO2002 is disposed over the gate structure 116 and extends laterally beyond the outermost sidewalls of the gate structure 116. A combined etch stop layer 2004 is disposed between the RPO2002 and the field plate 122. In some embodiments, the RPO2002 may surround (enclose) the field plate 122 (i.e., extend beyond the outermost sidewall of the field plate 122) by one or more lateral distances 2108, wherein the one or more lateral distances are in a range of about 0 microns to about 2 microns.

In some embodiments, the field plate 122 may extend to a non-zero depth 2110 in the combined etch stop layer 2004. In such embodiments, the field plate 122 contacts the sidewalls of the combined etch stop layer 2004. In various embodiments, the field plate 122 may also contact a horizontally extending surface of the combined etch stop layer 2004 or a horizontally extending surface of the RPO 2002. In some embodiments, non-zero depth 2110 may be in a range between about 400 angstroms to about 700 angstroms. Because the field plate 122 extends into the combined etch stop layer 2004, the combined etch stop layer 2004 has a first thickness 2112 directly below the field plate 122 and a second thickness outside the field plate 122, wherein the second thickness is greater than the first thickness 2112. In some embodiments, first thickness 2112 is in a range between about 0 angstroms and about 10000 angstroms. In some additional embodiments, first thickness 2112 is in a range between about 600 angstroms and about 3000 angstroms.

As shown in the cross-sectional view 2120 of fig. 21B (along the cross-sectional line a-a' of fig. 21A), the width 2114 of the field plate 122 extending in the first direction has a distance in a range between about 150 nanometers and 2000 nanometers. The field plate 122 also has a distance extending in a second direction (perpendicular to the first direction) with a length 2122 of less than about 1000 μm.

Referring again to the cross-sectional view of fig. 21A, in some embodiments, the field plate 122 may be laterally separated from the gate structure 116 by a distance 2116. For example, the field plate 122 may be laterally separated from the gate structure 116 by a distance in a range between about 0nm and about 200 nm. In other embodiments (not shown), the field plate 122 may laterally overlap the gate structure 116 (i.e., extend directly over the gate structure 116). For example, the field plate 122 laterally overlaps the gate structure 116 by a distance between about 0nm and about 200 nm.

In some embodiments, silicide layer 2118 is disposed over source region 104, drain region 106, and portions of gate structure 116 not covered by RPO 2002. In various embodiments, the silicide layer 2118 may include a compound having silicon and a metal, such as nickel, platinum, titanium, tungsten, magnesium, or the like. In some embodiments, the silicide layer 2118 has a thickness in a range between about 150 angstroms and about 400 angstroms.

Fig. 22 illustrates a cross-sectional view of some additional embodiments of the disclosed high-voltage transistor device 2200 with a combined etch stop layer defining a field plate.

The high voltage transistor device 2200 includes a semiconductor disposed on a semiconductorA gate structure 108 over the bulk substrate 102. The RPO2002 and the combined etch stop layer 2004 are located over the gate electrode 108 and the semiconductor substrate 102. A Contact Etch Stop Layer (CESL)406 is disposed over the combined etch stop layer 2004. In some embodiments, a bottom surface of combined etch stop layer 2004 may directly contact RPO2002 and a top surface of combined etch stop layer 2004 may directly contact CESL 406. The CESL406 extends laterally beyond the outermost sidewalls of the combined etch stop layer 2004 and contacts the semiconductor substrate 102. In some embodiments, CESL406 may have a thickness th in a range between about 100 angstroms and about 1000 angstroms₅. In some embodiments, CESL406 may comprise silicon nitride, silicon carbide, or the like.

A field plate 408 is disposed within the first ILD layer 118 above the CESL 406. In some embodiments, the field plate 408 may include a first metallic material 410 and a second metallic material 412. The combined etch stop layer 2004 is disposed laterally between the field plate 408 and the gate structure 116 and vertically between the field plate 122 and the semiconductor substrate 102. RPO2002 and combined etch stop layer 2004 have sidewalls that contact CESL 406. The combined etch stop layer 2004 further has a horizontally extending surface (e.g., an upper surface) that contacts the CESL 406.

In some embodiments, the field plate 122 may extend into one or more of a plurality of different dielectric materials 2006-2008 within the combined etch stop layer 2004. For example, in some embodiments, the combined etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2008 contacting an upper surface of the first dielectric material 2006. The field plate 122 may extend through the second dielectric material 2008 (e.g., silicon oxide) and have a bottom surface that contacts the first dielectric material 2006 (e.g., silicon nitride). In such embodiments, the first dielectric material 2006 can vertically separate the bottommost point of the field plate 122 from the RPO 2002. In other embodiments, field plate 122 may further extend through first dielectric material 2006 and have a bottom surface and/or sidewalls that contact RPO 2002. In some embodiments, the field plate 122 may extend vertically through the second dielectric material 2008 and also be laterally separated from the gate structure 116 by the second dielectric material 2008.

Although the disclosed combined etch stop layer 2004 is shown in fig. 20-22 as having two different dielectric materials 2006-2008 stacked over the RPO 2002. It should be understood, however, that the disclosed combination etch stop layer 2004 is not limited to this configuration. More specifically, in various embodiments, the combined etch stop layer 2004 may include additional layers of dielectric material. Fig. 23-24 show some non-limiting examples of alternative embodiments of the disclosed combined etch stop layer 2004.

Fig. 23 illustrates a cross-sectional view of some additional embodiments of the disclosed high-voltage transistor device 2300 with a combined etch stop layer defining a field plate.

The high-voltage transistor device 2300 includes a combined etch stop layer 2004 disposed over the RPO 2002. The combined etch stop layer 2004 includes a first dielectric material 2302, a second dielectric material 2304 contacting an upper surface of the first dielectric material 2302, and a third dielectric material 2306 contacting an upper surface of the second dielectric material 2304. In some embodiments, the first dielectric material 2302 can include or be silicon dioxide (SiO)₂) The second dielectric material 2304 may include or be silicon nitride (Si)_xN_y) Or silicon oxynitride (SiO)_xN_y) And the third dielectric material 2306 can comprise or be silicon dioxide (SiO)₂)。

In some embodiments, the first dielectric material 2302 can have a first thickness, the second dielectric material 2304 can have a second thickness, and the third dielectric material 2306 can have a third thickness. In some embodiments, the first thickness may be in a first range between about 300 angstroms and about 900 angstroms, the second thickness may be in a second range between about 50 angstroms and about 200 angstroms, and the third thickness may be in a third range between about 200 angstroms and about 600 angstroms.

Fig. 24 illustrates a cross-sectional view of some additional embodiments of the disclosed high-voltage transistor device 2400 with a combined etch stop layer defining a field plate.

The high-voltage transistor device 2400 includes a combined etch stop layer 2400 disposed over the RPO 2002. The combined etch stop layer 2400 includes a first dielectric material 2402, contacting the first dielectric materialA second dielectric material 2404 on the top surface of the charge 2402, a third dielectric material 2406 contacting the top surface of the second dielectric material 2404, and a fourth dielectric material 2408 contacting the top surface of the third dielectric material 2406. In some embodiments, the first dielectric material 2402 can include or be silicon dioxide (SiO)₂) The second dielectric material 2404 may include or be silicon nitride (Si)_xN_y) Or silicon oxynitride (SiO)_xN_y) And the third dielectric material 2406 can comprise or be silicon dioxide (SiO)₂) And the fourth dielectric material 2408 may include or be silicon nitride (Si)_xN_y) Or silicon oxynitride (SiO)_xN_y)。

In some embodiments, the first dielectric material 2402 may have a first thickness, the second dielectric material 2404 may have a second thickness, the third dielectric material 2406 may have a third thickness and the fourth dielectric material 2408 may have a fourth thickness. In some embodiments, the first thickness may be in a first range between about 300 angstroms and about 900 angstroms, the second thickness may be in a second range between about 50 angstroms and about 200 angstroms, the third thickness may be in a third range between about 200 angstroms and about 600 angstroms, and the fourth thickness is in a fourth range between about 50 angstroms and about 200 angstroms.

Fig. 25-32 illustrate cross-sectional views of some embodiments of methods of forming a high voltage transistor device with a combined etch stop layer defining a field plate. Although the sectional views 2500 through 3200 shown in fig. 25 through 32 are described with reference to a method, it should be understood that the structure shown in fig. 25 through 32 is not limited to the method but may exist independently of the method.

As shown in the cross-sectional view of fig. 25, the semiconductor substrate 102 is selectively implanted to form a plurality of implant regions (e.g., well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form the body region 2106, the drift region 2104, the source region 104 and the drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implant regions (e.g., such as any of the implant regions shown in fig. 1-10). In some embodiments, the plurality of implant regions may be formed by: the semiconductor substrate 102 is selectively masked (e.g., using a photoresist mask) and then a high energy dopant (e.g., a p-type dopant such as boron or an n-type dopant such as phosphorus) is introduced into the exposed regions of the semiconductor substrate 102.

A gate structure 116 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by: a gate dielectric layer 110 is deposited over the semiconductor substrate 102 and a gate electrode 108 is deposited over the gate dielectric layer 110. The gate dielectric layer 110 and gate electrode material 108 may then be patterned (etched according to a photoresist mask and/or a hard mask) to define a gate structure 116.

As shown in the cross-sectional view of fig. 26, a Resist Protective Oxide (RPO)2002 is formed over the gate structure 116. The RPO2002 extends laterally from directly above the gate structure 116 over the outermost sidewalls of the gate structure 116. RPO2002 is configured to block silicide formation on underlying layers. In some embodiments, RPO2002 may be deposited by a vapor deposition technique (e.g., CVD). In some embodiments, RPO2002 may comprise silicon dioxide (SiO)₂) Silicon nitride, and the like.

As shown in cross-section 2700 of fig. 27, a combined etch stop layer 2004 comprising a plurality of different dielectric materials 2600-2800 is selectively formed over RPO 2002. In some embodiments, a plurality of different dielectric materials 2006-2008 can be sequentially deposited by a vapor deposition technique. In some embodiments, the combined etch stop layer 2004 may include a stack layer, wherein the stack layer includes silicon nitride (Si)_xN_y) Layer, silicon oxynitride (SiO)_xN_y) Layer and/or silicon dioxide (SiO)₂) Two or more of the middle layers.

In some embodiments, the same masking layer 2702 (e.g., photoresist layer) and etching process may be used to pattern the plurality of different dielectric materials 2006-2008 and RPO 2002. Patterning the multiple different dielectric materials 2006-2008 and RPO2002 using the same masking layer 2702 reduces the cost of the combined etch stop layer 2004. In such embodiments, the plurality of different dielectric materials 2006-2008 and RPO2002 may have substantially aligned sidewalls.

As shown in the cross-sectional view of fig. 28, a Contact Etch Stop Layer (CESL)406 is formed over the semiconductor substrate 102 and the combined etch stop layer 2004. In some examples, CESL406 may be formed by a vapor deposition process. The CESL may include a nitride layer (e.g., Si)₃N₄) Carbide layer (SiC), and the like.

As shown in cross-sectional view 2900 of fig. 29, a first interlayer dielectric (ILD) is formed over CESL 406. In some embodiments, the first ILD layer 118 may comprise an oxide (e.g., SiO)₂) Ultra low k dielectric materials, low k dielectric materials (e.g., SiCO), and the like. In some embodiments, the first ILD layer 118 may be formed by a vapor deposition process.

As shown in the cross-sectional view of fig. 30, the first ILD layer 118 may be selectively exposed to an etchant 3002 (e.g., according to a masking layer 3003) to form contact openings 1606 and field plate openings 1608 in the first ILD layer 118. The contact opening 1606 and field plate opening 1608 have an etch depth offset of non-zero distance 3004. In some embodiments, non-zero distance 3004 may be in a range between about 400 angstroms and about 2000 angstroms. In some embodiments, the field plate opening 1608 extends into the combined etch stop layer 2004 such that sidewalls of the combined etch stop layer 2004 define the field plate opening 1608. In various embodiments, the combined etch stop layer 2004 or PRO 2002 may define the bottom of the field plate opening 1608.

In some embodiments, etchant 3002 may reduce the thickness of combined etch stop layer 2004 by an amount in a range between about 400 angstroms and about 700 angstroms. In some embodiments, the thickness of the combined etch stop layer 2004 directly under the field plate opening 1608 is in a range between about 0 angstroms and 1000 angstroms. In some additional embodiments, the thickness of the combined etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 300 angstroms and 900 angstroms for chlamydia moth.

The etchant 3002 used to form the contact opening 1606 and field plate opening 1608 is selected to etch through the material of CESL 406. However, because the combined etch stop layer 2004 is formed of a plurality of different materials, the combined etch stop layer 2004 is able to resist etching by the etchant 3002 to a greater degree. The combination etch stop layer 2004 thus allows the contact opening 1606 to extend to the semiconductor substrate 102 while preventing the field plate opening 1608 from extending to the semiconductor substrate 102. The combination etch stop layer 2004 also allows for a higher degree of uniformity in etch depth at different locations on the substrate with respect to the same batch of substrates and/or with respect to different batches of substrates. For example, the combination etch stop layer 2004 allows the etch depth of the field plate opening 1608 on different substrates to be within a deviation of about 2% or less. This etch depth uniformity allows for improved device uniformity and performance compared to devices without the combined etch stop layer 2004.

As shown in the cross-sectional view of fig. 31, the contact opening 1606 and field plate opening 1608 are filled with one or more conductive materials. In some embodiments, the one or more conductive materials may be deposited by way of vapor deposition techniques (e.g., CVD, PVD, PE-CVD, etc.) and/or plating processes (e.g., electroplating or non-electroplating). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess conductive material(s) and form a planar surface along line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), and/or tantalum nitride ((TaN).

As shown in the cross-sectional view of fig. 32, a second ILD layer 126 is formed above the first ILD layer 118 and a first back-end-of-line (BEOL) metal line layer 128 is formed within the second ILD layer 126. In such an embodiment, the second ILD layer 126 may be formed by depositing a second ILD layer material over the first ILD layer 118. The second ILD layer 126 is then etched to form trenches extending into the second ILD layer 126. The trenches are filled with a conductive material and a planarization process (e.g., CMP) is performed to remove excess conductive material from over the second ILD layer 126.

Fig. 33 illustrates a flow diagram of some embodiments of a method 3300 of forming a high voltage transistor device with a combined etch stop layer defining a field plate.

At act 3302, a gate structure is formed over a substrate. Fig. 25 illustrates a cross-sectional view 2500 corresponding to some embodiments of act 3302.

At act 3304, source and drain regions are formed on opposite sides of a gate structure within a substrate. In some additional embodiments, one or more additional doped regions (e.g., body regions, drift regions, etc.) may also be formed within the substrate. Figure 25 illustrates a cross-sectional view corresponding to some embodiments of act 3304.

At act 3306, a Resist Protection Oxide (RPO) is formed over the gate structure and laterally between the gate structure and the drain region. Fig. 26 illustrates cross-sectional view 2600, which corresponds to some embodiments of act 3306.

At act 3308, a combined etch stop layer is formed over the RPO. Figure 27 illustrates a cross-sectional view corresponding to some embodiments of act 3308.

At act 3310, a Contact Etch Stop Layer (CESL) is formed on the combined etch stop layer. Fig. 28 illustrates a cross-sectional view 2800 corresponding to some embodiments of act 3310.

At act 3312, a first inter-layer dielectric (ILD) layer is formed over the CESL. Figure 29 illustrates a cross-sectional view 2900 corresponding to some embodiments of act 3312.

At act 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The plurality of contact openings and the field plate opening have different depths. Fig. 30 illustrates a cross-sectional view 3000 corresponding to some embodiments of act 3314.

At act 3316, the plurality of contact openings and the field plate opening are filled with one or more conductive materials. Figure 31 illustrates a cross-sectional view 3100 that corresponds to some embodiments of act 3316.

At act 3318, conductive interconnect lines are formed within the second ILD layer above the first ILD layer. Fig. 32 illustrates a cross-sectional view 3200 corresponding with some embodiments of act 3318.

The present invention therefore relates to a high voltage transistor device having a field plate, wherein the field plate is formed at the same time as the conductive contact is formed. The device has a combined etch stop layer that is used to enable height differences of the field plate and the conductive contact.

In some embodiments, the invention relates to an integrated chip. The integrated chip includes: a gate structure disposed over the substrate between the source region and the drain region; a dielectric layer extending laterally from over the gate structure to between the gate structure and the drain region; a combination etch stop layer comprising a plurality of different dielectric materials stacked over the dielectric layer; a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer; a field plate laterally surrounded by and from a top of the first ILD layer, vertically extending through the contact etch stop layer, and into the combined etch stop layer. In some embodiments, the combined etch stop layer has a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide. In some embodiments, the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride. In some embodiments, the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material. In some embodiments, the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate. In some embodiments, the combined etch stop layer laterally contacts a sidewall of the field plate. In some embodiments, the bottom of the field plate is separated from the dielectric layer by the combined etch stop layer. In some embodiments, the dielectric layer comprises a resist protection oxide, wherein the resist protection oxide has a lower surface contacting the gate structure and an upper surface contacting the combined etch stop layer.

In an embodiment, the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.

In an embodiment, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

In an embodiment, the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.

In an embodiment, the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride.

In an embodiment, the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material.

In an embodiment, the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate.

In an embodiment, the combined etch stop layer laterally contacts a sidewall of the field plate.

In an embodiment, the bottom of the field plate is vertically separated from the dielectric layer by the combined etch stop layer.

In an embodiment, the dielectric layer comprises a resist protection oxide, wherein the resist protection oxide has a lower surface contacting the gate structure and an upper surface contacting the combined etch stop layer.

In other embodiments, the invention relates to an integrated chip. The integrated chip includes: a gate structure disposed over the substrate; a resist protection oxide extending laterally from above the gate structure through an outermost sidewall of the gate structure; a combined etch stop layer comprising a first dielectric material over the etch-resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material; a plurality of conductive contacts laterally surrounded by a first interlayer dielectric (ILD) layer over the substrate; and a field plate extending from a top of the first ILD layer to the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein the combined etch stop layer laterally contacts sidewalls of the field plate and vertically separates a bottom of the field plate from the resist protection oxide. In some embodiments, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material is an oxide and the second dielectric material is a nitride. In some embodiments, the combined etch stop layer further comprises: a third dielectric material in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material are of the same material. In some embodiments, the integrated chip further comprises: a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer. In some embodiments, the etch-resistant protective oxide has a first width that is equal to a second width of the combined etch stop layer.

In an embodiment, the first dielectric material is an oxide and the second dielectric material is a nitride.

In an embodiment, the combined etch stop layer further comprises: a third dielectric material in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material are the same material.

In an embodiment, the integrated chip further comprises: a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer.

In an embodiment, the etch-resistant protective oxide has a first width that is equal to a second width of the combined etch stop layer.

In yet another embodiment, the invention relates to a method of forming an integrated chip. The method comprises the following steps: forming a gate structure over a substrate between a source region and a drain region within the substrate; forming a dielectric layer over the gate structure and between the gate structure and the drain region; forming a combined etch stop layer over the dielectric layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials; forming a first inter-layer dielectric (ILD) layer over the combined etch stop layer; selectively etching the first ILD layer to simultaneously define a contact opening extending to the substrate and a field plate opening extending to the combined etch stop layer; and filling the contact opening and the field plate opening with one or more conductive materials. In some embodiments, the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the method further comprises: forming a masking layer over the combined etch stop layer; and etching the combined etch stop layer and the dielectric layer according to the masking layer.

In an embodiment, the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

In an embodiment, the method further comprises: forming a masking layer over the combined etch stop layer; and etching the combined etch stop layer and the dielectric layer according to the masking layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, comprising:

a gate structure disposed over the substrate between the source region and the drain region;

a dielectric layer extending laterally from over the gate structure to between the gate structure and the drain region;

a combination etch stop layer comprising a plurality of different dielectric materials stacked over the dielectric layer;

a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer; and

a field plate laterally surrounded by a first interlayer dielectric (ILD) layer and extending vertically through the contact etch stop layer from a top of the first interlayer dielectric layer and into the combined etch stop layer.

2. The integrated chip of claim 1, wherein the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.

3. The integrated chip of claim 2, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

4. The integrated chip of claim 2, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.

5. The integrated chip of claim 2, wherein the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride.

6. The integrated chip of claim 2, wherein the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material.

7. The integrated chip of claim 1, wherein the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate.

8. The integrated chip of claim 1, wherein the combined etch stop layer laterally contacts a sidewall of the field plate.

9. An integrated chip, comprising:

a gate structure disposed over the substrate;

a resist protection oxide extending laterally from above the gate structure over an outermost sidewall of the gate structure;

a combined etch stop layer comprising a first dielectric material over the etch-resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material;

a plurality of conductive contacts laterally surrounded by a first interlayer dielectric (ILD) layer over the substrate; and

a field plate extending from a top of the first interlayer dielectric layer to the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein the combined etch stop layer laterally contacts a sidewall of the field plate and vertically separates the field plate from the etch-resistant protective oxide.

10. A method of forming an integrated chip, comprising:

forming a gate structure over a substrate between a source region and a drain region within the substrate;

forming a dielectric layer over the gate structure and between the gate structure and the drain region;

forming a combined etch stop layer over the dielectric layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials;

forming a first inter-layer dielectric (ILD) layer over the combined etch stop layer;

selectively etching the first interlayer dielectric layer to simultaneously define a contact opening extending to the substrate and a field plate opening extending to the combined etch stop layer; and

the contact opening and the field plate opening are filled with one or more conductive materials.