TWI762253B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TWI762253B
TWI762253B TW110110894A TW110110894A TWI762253B TW I762253 B TWI762253 B TW I762253B TW 110110894 A TW110110894 A TW 110110894A TW 110110894 A TW110110894 A TW 110110894A TW I762253 B TWI762253 B TW I762253B
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gate
metal layer
semiconductor device
region
substrate
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TW110110894A
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TW202239002A (en
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浦士杰
藤卷浩和
彭德金
戴執中
艾世強
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力晶積成電子製造股份有限公司
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Priority to CN202110458050.4A priority patent/CN115132821A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device including a substrate, a source region, a drain region, and a gate structure is provided. The source region and the drain region are respectively located in the substrate. The gate structure is located on the substrate and between the source region and the drain region. The gate structure includes a first gate and at least one second gate. The second gate is located between the first gate and the drain region. The first gate is separated from the second gate, and the second gate is electrically connected to the source region.

Description

半導體裝置semiconductor device

本發明是有關於一種裝置，且特別是有關於一種半導體裝置。The present invention relates to a device, and more particularly, to a semiconductor device.

一般而言，在半導體裝置中的崩潰電壓(breakdown voltage, BV)與閘極-汲極電荷(Qgd)之間會具有折衷(trade-off)關係，舉例而言，在半導體裝置中常會藉由縮小通道(channel)長度的設計以降低閘極-汲極電荷，提升切換(switch)速度，然而，在此設計下會導致崩潰電壓的下降，如此一來，對半導體裝置的整體可靠度與性能會產生不良影響。因此，如何改善崩潰電壓與閘極-汲極電荷之間的折衷問題，以提升半導體裝置的整體可靠度與性能實為亟欲解決的重要課題。Generally speaking, there is a trade-off relationship between the breakdown voltage (BV) and the gate-drain charge (Qgd) in a semiconductor device. The design of reducing the length of the channel reduces the gate-drain charge and increases the switching speed. However, this design will result in a drop in breakdown voltage, which will affect the overall reliability and performance of the semiconductor device. will have adverse effects. Therefore, how to improve the trade-off between the breakdown voltage and the gate-drain charge to improve the overall reliability and performance of the semiconductor device is an important issue to be solved urgently.

本發明提供一種半導體裝置，可以提升其整體可靠度與性能。The present invention provides a semiconductor device which can improve its overall reliability and performance.

本發明的一種半導體裝置，包括基底、源極區、汲極區以及閘極結構。源極區與汲極區分別位於基底內。閘極結構位於基底上且位於源極區與汲極區之間。閘極結構包括第一閘極以及至少一第二閘極。第二閘極位於第一閘極與汲極區之間。第一閘極與第二閘極分隔開，且第二閘極與源極區電性連接。A semiconductor device of the present invention includes a substrate, a source region, a drain region and a gate structure. The source region and the drain region are respectively located in the substrate. The gate structure is located on the substrate and between the source region and the drain region. The gate structure includes a first gate and at least one second gate. The second gate is located between the first gate and the drain region. The first gate is separated from the second gate, and the second gate is electrically connected to the source region.

在本發明的一實施例中，上述的第一閘極的材料與第二閘極的材料相同。In an embodiment of the present invention, the above-mentioned material of the first gate electrode is the same as that of the second gate electrode.

在本發明的一實施例中，上述的第一閘極的功能不同於第二閘極的功能。In an embodiment of the present invention, the function of the first gate is different from the function of the second gate.

在本發明的一實施例中，上述的半導體裝置更包括位於第二閘極上的第一金屬層。第一金屬層相對於第二閘極朝汲極區偏移第一距離，且第二閘極藉由第一金屬層與源極區電性連接。In an embodiment of the present invention, the above-mentioned semiconductor device further includes a first metal layer on the second gate electrode. The first metal layer is offset by a first distance relative to the second gate electrode toward the drain region, and the second gate electrode is electrically connected to the source region through the first metal layer.

在本發明的一實施例中，上述的第一金屬層的尺寸大於第二閘極。In an embodiment of the present invention, the size of the first metal layer is larger than that of the second gate electrode.

在本發明的一實施例中，上述的半導體裝置更包括位於第一金屬層上的第二金屬層。第二金屬層相對於第一金屬層朝汲極區偏移第二距離，且第二閘極藉由第一金屬層以及第二金屬層與源極區電性連接。In an embodiment of the present invention, the above-mentioned semiconductor device further includes a second metal layer on the first metal layer. The second metal layer is offset toward the drain region by a second distance relative to the first metal layer, and the second gate electrode is electrically connected to the source region through the first metal layer and the second metal layer.

在本發明的一實施例中，上述的半導體裝置包括橫向擴散金屬氧化物半導體場效電晶體。In an embodiment of the present invention, the above-mentioned semiconductor device includes a laterally diffused metal oxide semiconductor field effect transistor.

在本發明的一實施例中，上述的半導體裝置更包括位於基底上且位於源極區與所述汲極區之間的絕緣層。第二閘極位於絕緣層的頂面上。In an embodiment of the present invention, the above-mentioned semiconductor device further includes an insulating layer on the substrate and between the source region and the drain region. The second gate is located on the top surface of the insulating layer.

在本發明的一實施例中，上述的第一閘極與汲極區之間具有漂移區域，且第二閘極與漂移區域藉由絕緣層分隔開。In an embodiment of the present invention, there is a drift region between the first gate and the drain region, and the second gate and the drift region are separated by an insulating layer.

在本發明的一實施例中，上述的半導體裝置更包括位於所述基底內且位於所述源極區與所述汲極區之間的隔離結構。第二閘極位於隔離結構的頂面上。In an embodiment of the present invention, the above-mentioned semiconductor device further includes an isolation structure located in the substrate and between the source region and the drain region. The second gate is located on the top surface of the isolation structure.

基於上述，本發明的半導體裝置的閘極結構藉由分隔開第一閘極與第二閘極且第二閘極與源極區電性連接的設計，可以調整裝置內的電場分布達到修補作用，因此可以改善崩潰電壓與閘極-汲極電荷之間的折衷問題，進而可以提升半導體裝置的整體可靠度與性能。Based on the above, the gate structure of the semiconductor device of the present invention can adjust the electric field distribution in the device to achieve repair by separating the first gate and the second gate and electrically connecting the second gate and the source region. Therefore, the trade-off problem between the breakdown voltage and the gate-drain charge can be improved, thereby improving the overall reliability and performance of the semiconductor device.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。Directional terms (eg, up, down, right, left, front, back, top, bottom) as used herein are used for reference only to the drawings and are not intended to imply absolute orientation.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。The present invention is more fully described with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the repeated descriptions will not be repeated in the following paragraphs.

圖1A、圖2、圖3、圖4、圖5、圖6是依據本發明一些實施例之半導體裝置的部分剖面示意圖。圖1B是圖1A的半導體裝置的電流與電壓關係圖。應說明的是，圖式中僅繪示出半導體裝置的部分剖面示意圖，其他未繪示的區域可以視實際設計上的需求而定。1A , FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , and FIG. 6 are partial cross-sectional views of semiconductor devices according to some embodiments of the present invention. FIG. 1B is a graph of current versus voltage for the semiconductor device of FIG. 1A . It should be noted that only a partial cross-sectional schematic diagram of the semiconductor device is shown in the drawings, and other regions not shown may be determined according to actual design requirements.

請參考圖1A與圖1B，本實施例的半導體裝置100包括基底110以及位於基底110內的多個摻雜區。舉例而言，基底110可以是P型基底，對基底110進行部分摻雜會形成N-型輕摻雜區域111，對N-型輕摻雜區域111進行部分摻雜從而形成之P+型高摻雜區域112，對P+型高摻雜區域112進行部分摻雜從而形成之N+型高摻雜區域(即源極區113)，對N-型輕摻雜區域111進行部分摻雜從而形成之N+型高摻雜區域(即汲極區114)，對P+型高摻雜區域112進行部分摻雜從而形成之P+型高摻雜區域115以及對該N-型輕摻雜區域111進行部分摻雜從而形成之N型摻雜區域116，而N型摻雜區域116圍繞汲極區114，其中該N-型輕摻雜區域111可以作為N型阱(N-well)，P+型高摻雜區域112可以作為P型基區(p-Body)。應說明的是，本發明不限制於上述基底110內摻雜區的佈局方式，基底110內可以是實際設計上的需求進行摻雜區的佈局，只要基底110內至少具有源極區113與汲極區114皆屬於本發明的保護範圍。Please refer to FIG. 1A and FIG. 1B , the semiconductor device 100 of this embodiment includes a substrate 110 and a plurality of doped regions in the substrate 110 . For example, the substrate 110 may be a P-type substrate. Partial doping of the substrate 110 will form an N-type lightly doped region 111, and a partial doping of the N-type lightly doped region 111 will form a P+ type highly doped region. The impurity region 112 is an N+ type highly doped region (ie, source region 113 ) formed by partially doping the P+ type highly doped region 112 , and the N+ type lightly doped region 111 is partially doped by doping Type highly doped region (ie drain region 114 ), partially doped P+ type highly doped region 112 to form P+ type highly doped region 115 and partially doped N- type lightly doped region 111 Thereby, an N-type doped region 116 is formed, and the N-type doped region 116 surrounds the drain region 114, wherein the N-type lightly doped region 111 can be used as an N-well (N-well) and a P+ type highly doped region. 112 can serve as a p-type base (p-Body). It should be noted that the present invention is not limited to the above-mentioned layout of the doped regions in the substrate 110 , the substrate 110 may be arranged in accordance with the actual design requirements, as long as the substrate 110 has at least the source region 113 and the drain region. The pole regions 114 all belong to the protection scope of the present invention.

在一些實施例中，P+型高摻雜區域115可緊靠源極區113，即P+型高摻雜區域115與源極區113之間無任何空隙，兩者相連接，此時，施加於P+型高摻雜區域115上之電壓與施加於源極區113上之源極電壓一致。然而，本發明不限於此，在未繪示的實施例中，P+型高摻雜區域115與源極區113之間也可存於一定之間隔，此時，施加於該P+型高摻雜區域115上之電壓可與施加於源極區113之源極電壓不一致。In some embodiments, the P+ type highly doped region 115 may be close to the source region 113, that is, there is no gap between the P+ type highly doped region 115 and the source region 113, and the two are connected. The voltage on the P+ type highly doped region 115 is the same as the source voltage applied on the source region 113 . However, the present invention is not limited to this. In the embodiment not shown, there may also be a certain interval between the P+ type highly doped region 115 and the source region 113. In this case, the P+ type highly doped region 115 is applied to the The voltage on region 115 may not be the same as the source voltage applied to source region 113 .

在本實施例中，半導體裝置100還包括閘極結構120，其中閘極結構120位於基底110上且位於源極區113與汲極區114之間。進一步而言，閘極結構120可以包括第一閘極122以及至少一第二閘極124(圖1中示意地繪示出一個)，其中第二閘極124位於第一閘極122與汲極區114之間，換句話說，第二閘極124較第一閘極122靠近汲極區114，反過來說，第一閘極122較第二閘極124靠近源極區113。In this embodiment, the semiconductor device 100 further includes a gate structure 120 , wherein the gate structure 120 is located on the substrate 110 and located between the source region 113 and the drain region 114 . Further, the gate structure 120 may include a first gate 122 and at least one second gate 124 (one is schematically shown in FIG. 1 ), wherein the second gate 124 is located between the first gate 122 and the drain Between the regions 114 , in other words, the second gate 124 is closer to the drain region 114 than the first gate 122 , and conversely, the first gate 122 is closer to the source region 113 than the second gate 124 .

此外，第一閘極122與第二閘極124可以分隔開，換句話說，第一閘極122與第二閘極124之間可以具有一距離，且第二閘極124與源極區113電性連接，如圖1A中的電性連接路徑P1。據此，本實施例的半導體裝置100的閘極結構120藉由分隔開第一閘極122與第二閘極124且第二閘極124與源極區113電性連接的設計，可以調整裝置內的電場分布達到修補作用，因此可以改善崩潰電壓與閘極-汲極電荷之間的折衷問題，進而可以提升半導體裝置的整體可靠度與性能。進一步而言，在前述設計下會避免電場過度集中在角落處或閘極-汲極電荷聚集在同一環境下，如此一來，可以導致較高的崩潰電壓及較低的閘極-汲極電荷，換句話說，在上述設計下可以在崩潰電壓維持在較高水平的同時降低閘極-汲極電荷，因此可以改善崩潰電壓與閘極-汲極電荷之間的折衷問題，進而可以提升半導體裝置100的整體可靠度與性能。舉例而言，如圖1B所示，半導體裝置100相較於習知半導體裝置而言可以明顯地降低閘極-汲極電荷。在此，習知半導體裝置例如未設計有第二閘極的半導體裝置。In addition, the first gate 122 and the second gate 124 may be separated, in other words, there may be a distance between the first gate 122 and the second gate 124, and the second gate 124 and the source region 113 is electrically connected, such as the electrical connection path P1 in FIG. 1A . Accordingly, the gate structure 120 of the semiconductor device 100 of the present embodiment can be adjusted by separating the first gate 122 from the second gate 124 and electrically connecting the second gate 124 and the source region 113 The electric field distribution in the device achieves a repairing effect, thereby improving the trade-off between the breakdown voltage and the gate-drain charge, thereby improving the overall reliability and performance of the semiconductor device. Furthermore, the above-mentioned design avoids excessive electric field concentration at corners or gate-drain charge accumulation in the same environment, which can result in higher breakdown voltage and lower gate-drain charge. , in other words, under the above design, the gate-drain charge can be reduced while the breakdown voltage is maintained at a high level, so the trade-off between the breakdown voltage and the gate-drain charge can be improved, and the semiconductor can be improved Overall reliability and performance of the device 100 . For example, as shown in FIG. 1B , the semiconductor device 100 can significantly reduce the gate-drain charge compared to the conventional semiconductor device. Here, the conventional semiconductor device, for example, is not designed with a second gate.

此外，如下方表1所示，根據半導體裝置100與習知半導體裝置的性能參數可知，一方面半導體裝置100可以維持在較高的崩潰電壓，另一方面半導體裝置100可以降低約1/3的閘極-汲極電荷，因此本實施例的半導體裝置100可以改善崩潰電壓與閘極-汲極電荷之間的折衷問題，進而可以提升半導體裝置100的整體可靠度與性能。在此，實施例1至實施例4的操作條件分別為對應給定半導體裝置100的第二閘極124的電壓為0伏特(V)、5伏特、10伏特、20伏特，而比較例1為習知半導體裝置(不包括第二閘極)。In addition, as shown in Table 1 below, according to the performance parameters of the semiconductor device 100 and conventional semiconductor devices, on the one hand, the semiconductor device 100 can maintain a higher breakdown voltage, and on the other hand, the semiconductor device 100 can reduce the breakdown voltage by about 1/3. Therefore, the semiconductor device 100 of this embodiment can improve the trade-off problem between the breakdown voltage and the gate-drain charge, thereby improving the overall reliability and performance of the semiconductor device 100 . Here, the operating conditions of Examples 1 to 4 are that the voltage of the second gate 124 of the given semiconductor device 100 is 0 volts (V), 5 volts, 10 volts, and 20 volts, respectively, while the comparative example 1 is A conventional semiconductor device (excluding the second gate).

表1    參數     裝置 崩潰電壓(BV) (V) 源極電阻(Rdson) (mΩmm 2) 崩潰電壓/源極電阻 (V/(mΩmm 2) 閘極-汲極電荷(Qgd) (nC/mm 2) 效率指數(Figure OF Merit) (mΩ・nC) 實施例1 79.8 45.2 1.765 1.03 46.6 實施例2 80.8 42.9 1.883 1.05 45.0 實施例3 80.4 41.1 1.956 1.08 44.4 實施例4 75.5 38.0 1.986 1.11 42.2 比較例1 79.8 42.9 1.86 3.35 143.7 Table 1 parameter device Breakdown Voltage (BV) (V) Source Resistance (Rdson) (mΩmm 2 ) Breakdown voltage/source resistance (V/(mΩmm 2 ) Gate-Drain Charge (Qgd) (nC/mm 2 ) Efficiency Index (Figure OF Merit) (mΩ・nC) Example 1 79.8 45.2 1.765 1.03 46.6 Example 2 80.8 42.9 1.883 1.05 45.0 Example 3 80.4 41.1 1.956 1.08 44.4 Example 4 75.5 38.0 1.986 1.11 42.2 Comparative Example 1 79.8 42.9 1.86 3.35 143.7

在一些實施例中，可以藉由切斷閘極的方式來形成分隔開的第一閘極122與第二閘極124，換句話說，第一閘極122與第二閘極124可以是於同一道製程所形成，因此第一閘極122的材料與第二閘極124的材料可以實質上相同，如皆為多晶矽，但本發明不限於此。In some embodiments, the separated first gate 122 and the second gate 124 may be formed by cutting off the gate. In other words, the first gate 122 and the second gate 124 may be Formed in the same process, the material of the first gate electrode 122 and the material of the second gate electrode 124 can be substantially the same, for example, both are polysilicon, but the invention is not limited thereto.

在一些實施例中，第一閘極122的功能可以不同於第二閘極124的功能，舉例而言，第一閘極122藉由閘介電層122a與基底110分隔開且與源極區113與汲極區114可以構成電晶體達到產生電場的功能，而第二閘極124可以與源極區113電性連接達到調整電場分布的功能。In some embodiments, the function of the first gate 122 may be different from the function of the second gate 124. For example, the first gate 122 is separated from the substrate 110 and the source by the gate dielectric layer 122a. The region 113 and the drain region 114 can constitute a transistor to achieve the function of generating an electric field, and the second gate 124 can be electrically connected to the source region 113 to achieve the function of adjusting the electric field distribution.

在一些實施例中，半導體裝置100可以包括橫向擴散金屬氧化物半導體場效電晶體(Laterally Diffused Metal Oxide Semiconductor, LDMOS)，其中半導體裝置100中可以包括高壓元件、低壓元件或其組合，但本發明不限於此。In some embodiments, the semiconductor device 100 may include a Laterally Diffused Metal Oxide Semiconductor (LDMOS), wherein the semiconductor device 100 may include a high voltage element, a low voltage element or a combination thereof, but the present invention Not limited to this.

在一些實施例中，第二閘極124可以是塊狀結構，且可以為多個第二閘極124，但本發明不限於此，第二閘極124的數量可以視實際設計上的需求調整。In some embodiments, the second gate electrode 124 may be a block structure, and may be a plurality of second gate electrodes 124, but the invention is not limited thereto, and the number of the second gate electrode 124 may be adjusted according to actual design requirements .

在一些實施例中，第二閘極124於基底110上的正投影可以位於第一閘極122於基底110上的正投影與汲極區114之間，換句話說，第一閘極122與第二閘極124可以由源極區113朝汲極區114的方向依序排列，但本發明不限於此。In some embodiments, the orthographic projection of the second gate 124 on the substrate 110 may be located between the orthographic projection of the first gate 122 on the substrate 110 and the drain region 114 , in other words, the first gate 122 and the The second gate electrodes 124 may be sequentially arranged from the source region 113 to the drain region 114 , but the invention is not limited thereto.

在一些實施例中，閘極結構120可以更包括覆蓋第一閘極122的側壁以及第二閘極124的側壁的間隙壁126。進一步而言，間隙壁126可以是單層結構(如圖1A所示)，且間隙壁126的材料例如是氮化矽，但本發明不限於此，在未繪示的實施例中，間隙壁126可以是多層結構，且間隙壁126的材料例如是氧化矽、氮化矽或其組合，但本發明不限於此。In some embodiments, the gate structure 120 may further include a spacer 126 covering the sidewall of the first gate 122 and the sidewall of the second gate 124 . Further, the spacer 126 can be a single-layer structure (as shown in FIG. 1A ), and the material of the spacer 126 is, for example, silicon nitride, but the invention is not limited thereto. The spacer 126 can be a multi-layer structure, and the material of the spacer 126 is, for example, silicon oxide, silicon nitride, or a combination thereof, but the invention is not limited thereto.

在本實施例中，半導體裝置100可以更包括配置於基底110上且位於源極區113與汲極區114之間的絕緣層130，其中第二閘極124位於絕緣層130的頂面130t上，換句話說，第二閘極124與基底110之間被絕緣層130分隔開，第二閘極124不與基底110直接接觸，而絕緣層130與基底110直接接觸，但本發明不限於此。在此，絕緣層130可以是任何適宜的氧化物。In this embodiment, the semiconductor device 100 may further include an insulating layer 130 disposed on the substrate 110 and located between the source region 113 and the drain region 114 , wherein the second gate 124 is located on the top surface 130t of the insulating layer 130 In other words, the second gate electrode 124 is separated from the substrate 110 by the insulating layer 130, the second gate electrode 124 is not in direct contact with the substrate 110, and the insulating layer 130 is in direct contact with the substrate 110, but the present invention is not limited to this. Here, the insulating layer 130 may be any suitable oxide.

在一些實施例中，第一閘極122與汲極區114之間可以具有漂移區域(drift region)，且第二閘極124與漂移區域藉由絕緣層130分隔開。另一方面，第一閘極122可以由基底110的頂面沿著絕緣層130向上延伸並形成於絕緣層130的頂面130t上，因此，第一閘極122還可以作為朝向源極區113延伸的一電場板(field plate)，但本發明不限於此。In some embodiments, there may be a drift region between the first gate 122 and the drain region 114 , and the second gate 124 and the drift region are separated by the insulating layer 130 . On the other hand, the first gate electrode 122 may extend upward along the insulating layer 130 from the top surface of the substrate 110 and be formed on the top surface 130t of the insulating layer 130 . Therefore, the first gate electrode 122 may also serve as a surface facing the source region 113 . An extended field plate, but the invention is not limited thereto.

在一些實施例中，第一閘極122相對於基底110的高度與第二閘極124相對於基底110的高度可以相同，但本發明不限於此，在另一些實施例中，第一閘極122相對於基底110的高度與第二閘極124相對於基底110的高度可以不同。In some embodiments, the height of the first gate electrode 122 relative to the substrate 110 and the height of the second gate electrode 124 relative to the substrate 110 may be the same, but the invention is not limited thereto. The height of 122 relative to the substrate 110 and the height of the second gate 124 relative to the substrate 110 may be different.

在一些實施例中，第二閘極124的尺寸可以小於絕緣層130的尺寸，換句話說，第二閘極124於基底110上的正投影面積小於絕緣層130於基底110上的正投影面積，但本發明不限於此。In some embodiments, the size of the second gate electrode 124 may be smaller than the size of the insulating layer 130 . In other words, the orthographic projection area of the second gate electrode 124 on the substrate 110 is smaller than the orthographic projection area of the insulating layer 130 on the substrate 110 , but the present invention is not limited to this.

在一些實施例中，第二閘極124可以與絕緣層130直接接觸，換句話說，第二閘極124可以是直接形成於絕緣層130上，但本發明不限於此。In some embodiments, the second gate electrode 124 may be in direct contact with the insulating layer 130 , in other words, the second gate electrode 124 may be directly formed on the insulating layer 130 , but the invention is not limited thereto.

在一些實施例中，以剖面觀之，絕緣層130可以具有梯形輪廓，但本發明不限於此，絕緣層130可以依實際設計上的需求而有不同的剖面輪廓。In some embodiments, the insulating layer 130 may have a trapezoidal profile in a cross-sectional view, but the invention is not limited thereto, and the insulating layer 130 may have different cross-sectional profiles according to actual design requirements.

在此必須說明的是，以下實施例沿用上述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明，關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。It must be noted here that the following embodiments use the element numbers and parts of the above-mentioned embodiments, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted, and the description of the omitted part is omitted. Reference may be made to the foregoing embodiments, and detailed descriptions in the following embodiments will not be repeated.

請參考圖2，半導體裝置200與圖1A中的半導體裝置100相似，不同之處在於：半導體裝置200更包括位於第二閘極124上的第一金屬層240。進一步而言，第一金屬層240相對於第二閘極124朝汲極區114偏移第一距離d1，且第二閘極124藉由第一金屬層240與源極區113電性連接，如圖2中的電性連接路徑P2，因此藉由第二閘極124與第一金屬層240搭配的設計可以進一步提升調整電場分布的能力具有更佳的修補作用，但本發明不限於此。Referring to FIG. 2 , the semiconductor device 200 is similar to the semiconductor device 100 in FIG. 1A , except that the semiconductor device 200 further includes a first metal layer 240 on the second gate electrode 124 . Further, the first metal layer 240 is offset by a first distance d1 relative to the second gate electrode 124 toward the drain region 114 , and the second gate electrode 124 is electrically connected to the source region 113 through the first metal layer 240 , As shown in the electrical connection path P2 in FIG. 2 , the ability to adjust the electric field distribution can be further improved by the design of the second gate 124 and the first metal layer 240 , but the invention is not limited to this.

在一些實施例中，第一金屬層240相對於第二閘極124進行水平偏移，使部分第一金屬層240凸出於第二閘極124的邊緣124e以靠近汲極區114，換句話說，第一金屬層240於基底110上的正投影僅部分重疊於第二閘極124於基底110上的正投影，但本發明不限於此。In some embodiments, the first metal layer 240 is horizontally offset with respect to the second gate electrode 124 , so that part of the first metal layer 240 protrudes from the edge 124 e of the second gate electrode 124 to be close to the drain region 114 , in other words In other words, the orthographic projection of the first metal layer 240 on the substrate 110 only partially overlaps the orthographic projection of the second gate electrode 124 on the substrate 110 , but the invention is not limited thereto.

在一些實施例中，第一金屬層240的尺寸大於第二閘極124的尺寸，其中第一金屬層240的尺寸例如是第一金屬層240的寬度240w，而第二閘極124的尺寸例如是第二閘極124的寬度124w，但本發明不限於此。In some embodiments, the size of the first metal layer 240 is larger than that of the second gate electrode 124 , wherein the size of the first metal layer 240 is, for example, the width 240w of the first metal layer 240 , and the size of the second gate electrode 124 is, for example, is the width 124w of the second gate electrode 124, but the present invention is not limited thereto.

在一些實施例中，第一金屬層240與第二閘極124沒有直接接觸，舉例而言，第一金屬層240與第二閘極124之間可以藉由導電連接件242進行垂直電性連接，其中導電連接件242例如是接觸窗(contact)，但本發明不限於此。In some embodiments, the first metal layer 240 and the second gate electrode 124 are not in direct contact. For example, the first metal layer 240 and the second gate electrode 124 may be electrically connected vertically through the conductive connection member 242 . , wherein the conductive connection member 242 is, for example, a contact window (contact), but the present invention is not limited thereto.

請參考圖3，半導體裝置300與圖2中的半導體裝置200相似，不同之處在於：半導體裝置300更包括位於第一金屬層240上的第二金屬層350。進一步而言，第二金屬層350相對於第一金屬層240朝汲極區114偏移第二距離d2，且第二閘極124藉由第一金屬層240以及第二金屬層350與源極區113電性連接，如圖3中的電性連接路徑P3，因此藉由第二閘極124、第一金屬層240與第二金屬層350搭配的設計可以進一步提升調整電場分布的能力具有更佳的修補作用，但本發明不限於此。Referring to FIG. 3 , the semiconductor device 300 is similar to the semiconductor device 200 in FIG. 2 , except that the semiconductor device 300 further includes a second metal layer 350 on the first metal layer 240 . Further, the second metal layer 350 is offset toward the drain region 114 by a second distance d2 relative to the first metal layer 240 , and the second gate 124 is connected to the source through the first metal layer 240 and the second metal layer 350 The region 113 is electrically connected, as shown in the electrical connection path P3 in FIG. 3 . Therefore, through the design of the second gate 124 , the first metal layer 240 and the second metal layer 350 , the ability to adjust the electric field distribution can be further improved. good repairing effect, but the present invention is not limited to this.

在一些實施例中，第二金屬層350相對於第一金屬層240進行水平偏移，使部分第二金屬層350凸出於第一金屬層240的的邊緣124e以靠近汲極區114，換句話說，第二金屬層350與第一金屬層240可以呈現階梯狀，但本發明不限於此。In some embodiments, the second metal layer 350 is horizontally offset relative to the first metal layer 240 , so that part of the second metal layer 350 protrudes from the edge 124 e of the first metal layer 240 to be close to the drain region 114 . In other words, the second metal layer 350 and the first metal layer 240 may be stepped, but the invention is not limited thereto.

在一些實施例中，第二距離d2大於第一距離d1，但本發明不限於此，第二距離d2與第一距離d1可以依照實際設計上的需求而定。In some embodiments, the second distance d2 is greater than the first distance d1, but the invention is not limited thereto, and the second distance d2 and the first distance d1 may be determined according to actual design requirements.

在一些實施例中，第二金屬層350相對於第二閘極124朝汲極區114偏移的距離為第一距離d1與第二距離d2的總和，但本發明不限於此。In some embodiments, the offset distance of the second metal layer 350 relative to the second gate electrode 124 toward the drain region 114 is the sum of the first distance d1 and the second distance d2 , but the invention is not limited thereto.

在一些實施例中，第二金屬層350與第一金屬層240沒有直接接觸，舉例而言，第二金屬層350與第一金屬層240之間可以藉由導電連接件352進行垂直電性連接，其中導電連接件352例如是接觸窗，但本發明不限於此。In some embodiments, the second metal layer 350 is not in direct contact with the first metal layer 240 . For example, the second metal layer 350 and the first metal layer 240 may be electrically connected vertically through conductive connectors 352 . , wherein the conductive connection member 352 is, for example, a contact window, but the present invention is not limited thereto.

請參考圖4，半導體裝置400與圖1中的半導體裝置100相似，不同之處在於：半導體裝置400的閘極結構420可以配置在不同於絕緣層130的絕緣結構上，且半導體裝置400的閘極結構420的類型不同於半導體裝置100的閘極結構120。進一步而言，在本實施例中，基底110內可以更包括位於源極區113與汲極區114之間的隔離結構430，且閘極結構420的部分第一閘極422與第二閘極424位於隔離結構430的頂面430t上，因此由於第二閘極424與源極區113電性連接，如圖4中的電性連接路徑P4可以調整電場分布的能力具有修補作用，進而可以提升半導體裝置400的整體可靠度與性能。但本發明不限於此。在此，隔離結構430可以是淺溝槽隔離結構(STI)或其他適宜的隔離結構。Referring to FIG. 4 , the semiconductor device 400 is similar to the semiconductor device 100 in FIG. 1 , except that the gate structure 420 of the semiconductor device 400 may be disposed on an insulating structure different from the insulating layer 130 , and the gate structure of the semiconductor device 400 The type of the pole structure 420 is different from that of the gate structure 120 of the semiconductor device 100 . Further, in this embodiment, the substrate 110 may further include an isolation structure 430 between the source region 113 and the drain region 114 , and part of the first gate 422 and the second gate of the gate structure 420 424 is located on the top surface 430t of the isolation structure 430. Therefore, since the second gate electrode 424 is electrically connected to the source region 113, the ability to adjust the electric field distribution as shown in the electrical connection path P4 in FIG. Overall reliability and performance of the semiconductor device 400 . However, the present invention is not limited to this. Here, the isolation structures 430 may be shallow trench isolation structures (STI) or other suitable isolation structures.

在一些實施例中，第一閘極422沒有向上延伸的結構，第一閘極422藉由閘介電層422a與基底110分隔開，而閘介電層422a可以與隔離結構430直接接觸。另一方面，第二閘極424沒有被抬升一高度，換句話說，第二閘極424與隔離結構430直接接觸，亦即沒有絕緣層隔開第二閘極424與漂移區域，但本發明不限於此。In some embodiments, the first gate electrode 422 does not have an upwardly extending structure, and the first gate electrode 422 is separated from the substrate 110 by a gate dielectric layer 422a, and the gate dielectric layer 422a may be in direct contact with the isolation structure 430 . On the other hand, the second gate 424 is not raised by a height, in other words, the second gate 424 is in direct contact with the isolation structure 430, that is, there is no insulating layer separating the second gate 424 and the drift region, but the present invention Not limited to this.

在一些實施例中，閘極結構420可以更包括覆蓋第一閘極422的側壁以及第二閘極424的側壁的間隙壁426。進一步而言，間隙壁426可以是單層結構(如圖1A所示)，且間隙壁426的材料例如是氮化矽，但本發明不限於此，在未繪示的實施例中，間隙壁426可以是多層結構，且間隙壁426的材料例如是氧化矽、氮化矽或其組合，但本發明不限於此。In some embodiments, the gate structure 420 may further include a spacer 426 covering the sidewall of the first gate 422 and the sidewall of the second gate 424 . Further, the spacer 426 may be a single-layer structure (as shown in FIG. 1A ), and the material of the spacer 426 is, for example, silicon nitride, but the invention is not limited thereto. The spacer 426 can be a multi-layer structure, and the material of the spacer 426 is, for example, silicon oxide, silicon nitride, or a combination thereof, but the invention is not limited thereto.

請參考圖5，半導體裝置500與圖4中的半導體裝置400相似，不同之處在於：半導體裝置500更包括位於第二閘極424上的第一金屬層540。進一步而言，第一金屬層540相對於第二閘極424朝汲極區114偏移第一距離d11，且第二閘極424藉由第一金屬層540與源極區113電性連接，如圖5中的電性連接路徑P5，因此藉由第二閘極424與第一金屬層540搭配的設計可以進一步提升調整電場分布的能力具有更佳的修補作用，但本發明不限於此。Referring to FIG. 5 , the semiconductor device 500 is similar to the semiconductor device 400 in FIG. 4 , except that the semiconductor device 500 further includes a first metal layer 540 on the second gate electrode 424 . Further, the first metal layer 540 is offset by a first distance d11 relative to the second gate electrode 424 toward the drain region 114 , and the second gate electrode 424 is electrically connected to the source region 113 through the first metal layer 540 , As shown in the electrical connection path P5 in FIG. 5 , the design of the second gate 424 and the first metal layer 540 can further improve the ability to adjust the electric field distribution and have a better repairing effect, but the invention is not limited to this.

在一些實施例中，第一金屬層540相對於第二閘極424進行水平偏移，使部分第一金屬層540凸出於第二閘極424的邊緣424e以靠近汲極區114，換句話說，第一金屬層540於基底110上的正投影僅部分重疊於第二閘極424於基底110上的正投影，但本發明不限於此。In some embodiments, the first metal layer 540 is horizontally offset relative to the second gate electrode 424 , so that part of the first metal layer 540 protrudes from the edge 424e of the second gate electrode 424 to be close to the drain region 114 , in other words In other words, the orthographic projection of the first metal layer 540 on the substrate 110 only partially overlaps the orthographic projection of the second gate electrode 424 on the substrate 110 , but the invention is not limited thereto.

在一些實施例中，第一金屬層540與第二閘極424沒有直接接觸，舉例而言，第一金屬層540與第二閘極424之間可以藉由導電連接件542進行垂直電性連接，其中導電連接件542例如是接觸窗，但本發明不限於此。In some embodiments, the first metal layer 540 and the second gate electrode 424 are not in direct contact. For example, the first metal layer 540 and the second gate electrode 424 may be electrically connected vertically through the conductive connector 542 . , wherein the conductive connection member 542 is, for example, a contact window, but the present invention is not limited thereto.

請參考圖6，半導體裝置600與圖5中的半導體裝置500相似，不同之處在於：半導體裝置600更包括位於第一金屬層540上的第二金屬層650。進一步而言，第二金屬層650相對於第一金屬層540朝汲極區114偏移第二距離d21，且第二閘極424藉由第一金屬層540以及第二金屬層650與源極區113電性連接，如圖6中的電性連接路徑P6，因此藉由第二閘極424、第一金屬層540與第二金屬層650搭配的設計可以進一步提升調整電場分布的能力具有更佳的修補作用，但本發明不限於此。Referring to FIG. 6 , the semiconductor device 600 is similar to the semiconductor device 500 in FIG. 5 , except that the semiconductor device 600 further includes a second metal layer 650 on the first metal layer 540 . Further, the second metal layer 650 is offset by a second distance d21 relative to the first metal layer 540 toward the drain region 114 , and the second gate 424 is connected to the source through the first metal layer 540 and the second metal layer 650 The region 113 is electrically connected, such as the electrical connection path P6 in FIG. 6 . Therefore, through the design of the second gate 424, the first metal layer 540 and the second metal layer 650, the ability to adjust the electric field distribution can be further improved. good repairing effect, but the present invention is not limited to this.

在一些實施例中，第二金屬層650相對於第一金屬層540進行水平偏移，使部分第二金屬層650凸出於第一金屬層540的的邊緣524e以靠近汲極區114，換句話說，第二金屬層650與第一金屬層540可以呈現階梯狀，但本發明不限於此。In some embodiments, the second metal layer 650 is horizontally offset relative to the first metal layer 540 , so that part of the second metal layer 650 protrudes from the edge 524e of the first metal layer 540 to be close to the drain region 114 . In other words, the second metal layer 650 and the first metal layer 540 may be stepped, but the present invention is not limited thereto.

在一些實施例中，第二距離d21大於第一距離d11，但本發明不限於此，第二距離d21與第一距離d11可以依照實際設計上的需求而定。In some embodiments, the second distance d21 is greater than the first distance d11, but the invention is not limited thereto, and the second distance d21 and the first distance d11 may be determined according to actual design requirements.

在一些實施例中，第二金屬層650相對於第二閘極424朝汲極區114偏移的距離為第一距離d11與第二距離d21的總和，但本發明不限於此。In some embodiments, the offset distance of the second metal layer 650 relative to the second gate electrode 424 toward the drain region 114 is the sum of the first distance d11 and the second distance d21 , but the invention is not limited thereto.

在一些實施例中，第二金屬層650與第一金屬層540沒有直接接觸，舉例而言，第二金屬層650與第一金屬層540之間可以藉由導電連接件652進行垂直電性連接，其中導電連接件652例如是接觸窗，但本發明不限於此。In some embodiments, the second metal layer 650 is not in direct contact with the first metal layer 540 . For example, the second metal layer 650 and the first metal layer 540 may be electrically connected vertically through conductive connectors 652 . , wherein the conductive connection member 652 is, for example, a contact window, but the present invention is not limited thereto.

應說明的是，本發明不限制金屬層的數量，且金屬層的配置為可選的，只要半導體裝置中設置有第二閘極皆屬於本發明的保護範圍。It should be noted that the present invention does not limit the number of metal layers, and the configuration of the metal layers is optional, as long as the semiconductor device is provided with a second gate, it falls within the protection scope of the present invention.

綜上所述，本發明的半導體裝置的閘極結構藉由分隔開第一閘極與第二閘極且第二閘極與源極區電性連接的設計，可以調整裝置內的電場分布達到修補作用，因此可以改善崩潰電壓與閘極-汲極電荷之間的折衷問題，進而可以提升半導體裝置的整體可靠度與性能。進一步而言，在前述設計下會避免電場過度集中在角落處或閘極-汲極電荷聚集在同一環境下，如此一來，可以導致較高的崩潰電壓及較低的閘極-汲極電荷，換句話說，在上述設計下可以在崩潰電壓維持在較高水平的同時降低閘極-汲極電荷，因此可以改善崩潰電壓與閘極-汲極電荷之間的折衷問題，進而可以提升半導體裝置的整體可靠度與性能。To sum up, the gate structure of the semiconductor device of the present invention can adjust the electric field distribution in the device by separating the first gate and the second gate, and the second gate and the source region are electrically connected The repairing effect is achieved, so the trade-off problem between the breakdown voltage and the gate-drain charge can be improved, thereby improving the overall reliability and performance of the semiconductor device. Furthermore, the above-mentioned design avoids excessive electric field concentration at corners or gate-drain charge accumulation in the same environment, which can result in higher breakdown voltage and lower gate-drain charge. , in other words, under the above design, the gate-drain charge can be reduced while the breakdown voltage is maintained at a high level, so the trade-off between the breakdown voltage and the gate-drain charge can be improved, and the semiconductor can be improved The overall reliability and performance of the device.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100、200、300、400、500、600:半導體裝置 110:基底 111、112、115、116:摻雜區域 113:源極區 114:汲極區 120、420:閘極結構 122、422:第一閘極 122a、422a:閘介電層 124、424:第二閘極 124w、240w:寬度 126、426:間隙壁 130:絕緣層 130t:頂面 240、540:第一金屬層 242、352、542、652:導電連接件 350、650:第二金屬層 d1、d11:第一距離 d2、d21:第二距離 P1、P2、P3、P4、P5、P6:電性連接路徑 100, 200, 300, 400, 500, 600: Semiconductor devices 110: Base 111, 112, 115, 116: doped regions 113: source region 114: drain region 120, 420: gate structure 122, 422: the first gate 122a, 422a: gate dielectric layer 124, 424: the second gate 124w, 240w: width 126, 426: Spacer 130: Insulation layer 130t: top surface 240, 540: the first metal layer 242, 352, 542, 652: Conductive connectors 350, 650: second metal layer d1, d11: the first distance d2, d21: the second distance P1, P2, P3, P4, P5, P6: electrical connection paths

圖1A、圖2、圖3、圖4、圖5、圖6是依據本發明一些實施例之半導體裝置的部分剖面示意圖。 圖1B是圖1A的半導體裝置的電荷與電壓關係圖。 1A , FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , and FIG. 6 are partial cross-sectional views of semiconductor devices according to some embodiments of the present invention. FIG. 1B is a graph of charge versus voltage for the semiconductor device of FIG. 1A .

100:半導體裝置 100: Semiconductor Devices

110:基底 110: Base

111、112、115、116:摻雜區域 111, 112, 115, 116: doped regions

113:源極區 113: source region

114:汲極區 114: drain region

120:閘極結構 120: Gate structure

122:第一閘極 122: first gate

122a:閘介電層 122a: gate dielectric layer

124:第二閘極 124: The second gate

126:間隙壁 126: Spacer

130:絕緣層 130: Insulation layer

130t:頂面 130t: top surface

P1:電性連接路徑 P1: Electrical connection path

Claims (10)

一種半導體裝置，包括：基底；源極區、汲極區與摻雜區域，分別位於所述基底內，其中所述摻雜區域鄰近所述源極區，且所述摻雜區域與所述源極區電性連接；以及閘極結構，位於所述基底上且位於所述源極區與所述汲極區之間，其中所述閘極結構包括：第一閘極；以及至少一第二閘極，位於所述第一閘極與所述汲極區之間，其中所述第一閘極與所述至少一第二閘極分隔開，且所述至少一第二閘極與所述源極區電性連接。 A semiconductor device, comprising: a substrate; a source region, a drain region and a doping region, respectively located in the substrate, wherein the doping region is adjacent to the source region, and the doping region and the source a gate region is electrically connected; and a gate structure is located on the substrate and between the source region and the drain region, wherein the gate structure comprises: a first gate; and at least one second gate a gate, located between the first gate and the drain region, wherein the first gate is separated from the at least one second gate, and the at least one second gate is connected to the The source region is electrically connected. 如請求項1所述的半導體裝置，其中所述第一閘極的材料與所述至少一第二閘極的材料相同。 The semiconductor device of claim 1, wherein the material of the first gate is the same as the material of the at least one second gate. 如請求項1所述的半導體裝置，其中所述第一閘極的功能不同於所述至少一第二閘極的功能。 The semiconductor device of claim 1, wherein the function of the first gate is different from the function of the at least one second gate. 如請求項1所述的半導體裝置，更包括第一金屬層，位於所述至少一第二閘極上，其中所述第一金屬層相對於所述至少一第二閘極朝所述汲極區偏移第一距離，且所述至少一第二閘極藉由所述第一金屬層與所述源極區電性連接。 The semiconductor device of claim 1, further comprising a first metal layer on the at least one second gate electrode, wherein the first metal layer faces the drain region relative to the at least one second gate electrode The at least one second gate is offset by a first distance, and the at least one second gate is electrically connected to the source region through the first metal layer. 如請求項4所述的半導體裝置，其中所述第一金屬層的尺寸大於所述至少一第二閘極。 The semiconductor device of claim 4, wherein the size of the first metal layer is larger than that of the at least one second gate. 如請求項4所述的半導體裝置，更包括第二金屬層，位於所述第一金屬層上，其中所述第二金屬層相對於所述第一金屬層朝所述汲極區偏移第二距離，且所述至少一第二閘極藉由所述第一金屬層以及所述第二金屬層與所述源極區電性連接。 The semiconductor device of claim 4, further comprising a second metal layer on the first metal layer, wherein the second metal layer is offset relative to the first metal layer toward the drain region by a third two distances, and the at least one second gate electrode is electrically connected to the source region through the first metal layer and the second metal layer. 如請求項1所述的半導體裝置，其中半導體裝置包括橫向擴散金屬氧化物半導體場效電晶體。 The semiconductor device of claim 1, wherein the semiconductor device comprises a laterally diffused metal oxide semiconductor field effect transistor. 如請求項1至請求項7中任一項所述的半導體裝置，更包括絕緣層，所述絕緣層位於所述基底上且位於所述源極區與所述汲極區之間，其中所述至少一第二閘極位於所述絕緣層的頂面上。 The semiconductor device according to any one of claim 1 to claim 7, further comprising an insulating layer, the insulating layer is located on the substrate and between the source region and the drain region, wherein the insulating layer is The at least one second gate electrode is located on the top surface of the insulating layer. 如請求項8所述的半導體裝置，其中所述第一閘極與所述汲極區之間具有漂移區域，且所述至少一第二閘極與所述漂移區域藉由所述絕緣層分隔開。 The semiconductor device of claim 8, wherein there is a drift region between the first gate and the drain region, and the at least one second gate and the drift region are separated by the insulating layer separated. 如請求項1至請求項7中任一項所述的半導體裝置，更包括隔離結構，所述隔離結構位於所述基底內且位於所述源極區與所述汲極區之間，其中所述至少一第二閘極位於所述隔離結構的頂面上。 The semiconductor device according to any one of claim 1 to claim 7, further comprising an isolation structure, the isolation structure is located in the substrate and between the source region and the drain region, wherein the isolation structure The at least one second gate electrode is located on the top surface of the isolation structure.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201322446A (en) * 2011-11-30 2013-06-01 Taiwan Semiconductor Mfg Power MOSFET and methods for manufacturing the same
US20170194491A1 (en) * 2015-12-31 2017-07-06 Globalfoundries Singapore Pte. Ltd. High voltage device with low rdson
TW201740564A (en) * 2016-02-05 2017-11-16 台灣積體電路製造股份有限公司 Semiconductor structure and associated fabricating method
TW201941428A (en) * 2018-03-21 2019-10-16 台灣積體電路製造股份有限公司 Integrated chip and method of forming the same
US20200212188A1 (en) * 2017-09-29 2020-07-02 Texas Instruments Incorporated Ldmos with high-k drain sti dielectric

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201322446A (en) * 2011-11-30 2013-06-01 Taiwan Semiconductor Mfg Power MOSFET and methods for manufacturing the same
US20170194491A1 (en) * 2015-12-31 2017-07-06 Globalfoundries Singapore Pte. Ltd. High voltage device with low rdson
TW201740564A (en) * 2016-02-05 2017-11-16 台灣積體電路製造股份有限公司 Semiconductor structure and associated fabricating method
US20200212188A1 (en) * 2017-09-29 2020-07-02 Texas Instruments Incorporated Ldmos with high-k drain sti dielectric
TW201941428A (en) * 2018-03-21 2019-10-16 台灣積體電路製造股份有限公司 Integrated chip and method of forming the same

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