TWI802321B - Laterally double diffused metal oxide semiconductor device - Google Patents

Abstract

A laterally double diffused metal oxide semiconductor device includes a substrate with a well region, a body doped region in the well region, a body pick-up region in the body doped region, source regions at two sides of the body pickup region in the body doped region, drain regions, a thick oxide layer between the drain region and the body doped region, finger gates, conductive structures, and a gate insulating layer. The thick oxide layer defines the active region. The finger gates are respectively disposed outside the source regions on the active region, wherein each of the finger gates includes branch parts, and the branch parts are arranged parallel to each other and extend above the thick oxide layer. The conductive structures are between the branches and across the active region and the thick oxide layer, wherein the conductor structures are electrically insulated from the finger gates. The gate insulating layer is disposed between the finger gate and the active region and between the conductor structure and the active region.

Description

Lateral double diffused metal oxide semiconductor device

The present invention relates to a semiconductor device, and more particularly to a lateral double diffused metal oxide semiconductor (LDMOS) device.

Lateral double-diffused MOS devices are widely used in switching regulators because of their performance in a balance between specific on-resistance (Ron_sp) and drain-to-source breakdown voltage (BVdss). Generally, the design of the lateral double-diffused metal oxide semiconductor device used in high voltage needs to have a relatively high breakdown voltage, and at the same time, it must have a low on-resistance during operation.

In addition, besides the direct current (DC) characteristic, the alternating current (AC) characteristic of the lateral double diffused metal oxide semiconductor device is also important in high frequency operation, namely its gate drain charge (Qgd). When designing components, the specific on-resistance (Ron_sp) × gate drain charge (Qgd) is usually used as the evaluation index (Figure of Merit, FOM), and this value represents the power consumption of the component.

Therefore, all circles are currently focusing on how to design a lateral double-diffused metal oxide semiconductor device with good AC characteristics and DC characteristics.

The present invention provides a lateral double-diffused metal oxide semiconductor device, which can achieve good AC characteristics and DC characteristics according to power requirements, that is, the present invention can adjust FOM according to power requirements without adjusting process conditions.

The lateral double-diffused metal oxide semiconductor device of the present invention includes a substrate, a body doped region, a body pick-up region, several source regions, several drain regions, a thick oxide layer, several finger gates, and several conductor structures and gate insulation. The substrate has a well region, a body-doped region is disposed in the well region, and a body pickup region is disposed in the body-doped region. The source regions are respectively arranged in the body doping regions on both sides of the body pickup region. The drain regions are respectively arranged in the well regions separated from the body doped regions by a first distance. The thick oxide layer is disposed between the drain region and the body-doped region to define the active region, and the thick oxide layer is separated from the body-doped region by a second distance. Finger-shaped gates are respectively arranged on the outer active regions of several source regions, wherein each finger-shaped gate includes several branch parts, and the branch parts are arranged in parallel and extend to the thick oxide layer. The conductor structure is disposed between the branches and straddles the active region and the thick oxide layer, wherein the conductor structure is electrically insulated from the finger gate. The gate insulating layer is located between the gate fingers and the active area and between the conductor structure and the active area.

In an embodiment of the present invention, the number of the above-mentioned conductor structures disposed between the two branch portions is one or several.

In an embodiment of the present invention, the above conductor structure is connected to the source electrode.

In an embodiment of the present invention, the above conductor structure is electrically floating.

In an embodiment of the present invention, the above-mentioned thick oxide layer may be composed of several separated blocks, and the well area between the blocks is defined as a Reduced Surface Field (RESURF) region, and the reduced surface electric field The regions are arranged in parallel between the branch portion and the conductor structure and extend to the drain region.

In an embodiment of the present invention, the conductor structure and the gate finger are made of the same material.

In an embodiment of the present invention, the above-mentioned conductor structure may be n-type polysilicon, p-type polysilicon or undoped polysilicon.

In an embodiment of the present invention, the source region and the drain region are doped regions of the first conductivity type, and the body doped region and the body pickup region are doped regions of the second conductivity type.

In an embodiment of the present invention, the substrate is a substrate of the second conductivity type, and the well region is a well region of the first conductivity type.

In an embodiment of the present invention, the first conductivity type is n-type, and the second conductivity type is p-type.

Based on the above, the lateral double-diffused metal oxide semiconductor device of the present invention includes a finger gate and a conductor structure disposed between the branch portions of the finger gate. Since the conductor structure is electrically insulated from the finger gate, the finger gate It can maintain the low specific on-resistance (Ron_sp) of the device, and the conductor structure can accelerate the charging time (charging time). Therefore, according to the operating voltage range, the number of conductor structures can be changed to obtain a suitable FOM value. Since the conductor structure and finger gates can be formed by the same process, the lateral double-diffused metal oxide semiconductor device of the present invention can be fabricated only by changing the layout design without adjusting process conditions or adding steps.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

The attached drawings in the following embodiments are for more complete description of the embodiments of the present invention, however, the present invention can still be implemented in many different forms, not limited to the described embodiments. In addition, the relative thicknesses, distances and positions of various regions or layers may be reduced or exaggerated for clarity. In addition, the use of similar or identical reference numerals in the drawings indicates the existence of similar or identical parts or features.

FIG. 1 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a lateral double-diffused metal oxide semiconductor device along line II-II' in Fig. 1 . Fig. 3 is a schematic cross-sectional view of the lateral double-diffused metal oxide semiconductor device along line III-III' in Fig. 1 .

Please refer to FIG. 1 to FIG. 3 at the same time. The lateral double-diffused metal oxide semiconductor device of the first embodiment includes a substrate 100, a body doped region 102, a body pick-up (pick-up) region 104, several source regions 106, several Drain region 108 , thick oxide layer 110 , gate fingers 112 , conductor structures 114 and gate insulating layer 116 . The substrate 100 has a well region 101. If the well region 101 is a well region of the first conductivity type, the substrate 100 is a substrate of the second conductivity type. The body doped region 102 is disposed in the well region 101, and the body pickup region 104 is disposed in the body doped region 102, wherein the body doped region 102 and the body pickup region 104 are doped regions of the second conductivity type, and the body pickup region 104 is disposed in the body doped region 102. The doping concentration of region 104 is greater than the doping concentration of bulk doped region 102 . The source region 106 is respectively disposed in the body doped region 102 on both sides of the body pickup region 104, and the source region 106 and the drain region 108 are doped regions of the first conductivity type, and the source region 106 is connected to the source electrodes (not shown). In one embodiment, the first conductivity type is n-type, and the second conductivity type is p-type; in another embodiment, the first conductivity type is p-type, and the second conductivity type is n-type.

Referring to FIG. 1 , the drain regions 108 are respectively disposed in the well regions 101 separated by a first distance d1 from the body doped regions 102 , and the drain regions 108 are connected to a drain electrode (not shown). The thick oxide layer 110 is disposed between the drain region 108 and the body-doped region 102 to define the active region AA; that is, the active region AA includes the body-doped region 102, the body pickup region 104, and the source region 106. , the region where the drain region 108 and part of the well region 101 are located. The thick oxide layer 110 is also called a drift oxide layer (DOX), representing the oxide layer between the drain region 108 and the gate electrode 112, wherein the thick oxide layer 110 is, for example, a local oxidation of silicon (LOCOS) structure, It may also be a shallow trench isolation (STI) structure. In the first embodiment, the thick oxide layer 110 is separated from the body doped region 102 by a second distance d2, that is, the second distance d2 is smaller than the first distance d1, and the first distance d1 is approximately equal to the second distance d2 plus the thickness The sum of the widths of the oxide layer 110 , wherein the width of the thick oxide layer 110 refers to the size of the thick oxide layer 110 in a lateral direction (eg, a direction perpendicular to the extending direction of the body pickup region 104 ). The gate fingers 112 are respectively disposed on the active region AA outside the source region 106 , wherein each gate finger 112 includes a plurality of branch portions 112a, and these branch portions 112a are arranged in parallel and extend to the thick oxide layer 110 .

Referring to FIG. 3, since the finger gate 112 (the branch portion 112a) extends from the outside of the source region 106 to the thick oxide layer 110, the existence of the finger gate 112 can make the overall device have a low specific on-resistance ( Ron_sp), and the range of the branch portion 112a covering the thick oxide layer 110 can be increased or decreased according to requirements, and is not limited to the drawing of this embodiment.

Please continue to refer to FIG. 1 , the conductive structure 114 is disposed between the two branch portions 112 a and straddles the active area AA and the thick oxide layer 110 , and the conductive structure 114 is electrically insulated from the finger gate 112 . Therefore, observing the conductor structure 114 from the cross-sectional view of FIG. 2, a structure similar to a field plate can be obtained, and in this embodiment, the conductor structure 114 is connected to the source electrode (not shown), but the present invention is not limited to Here; in another embodiment, the conductor structure 114 can be electrically floating (floating). From the viewpoint of shortening the charging time, the conductive structure 114 is preferably connected to the source electrode, that is, is at the same potential as the source region 106 . Table 1 below shows various performances of the lateral double-diffused metal oxide semiconductor device of the present invention.

Table 1 Finger gate performance Conductor Structure Properties this invention Drain Current (Ids) 1 ↓↓ ↓ charging time 1 ↓↓↓ ↓↓ Ron_sp 1 ↑↑ ↑ FOM 1 ↓↓ adjustable "1" in the table means the same performance as a whole continuous gate; "↑" means increase, the more arrows there are, the greater the increase; "↓" means decrease, the more arrows, the greater the decrease.

It can be seen from Table 1 that the conductor structure 114 can greatly reduce the charging time, and the charging time and Ron_sp can be adjusted by changing the number ratio of the finger gate 112 (the branch portion 112 a ) to the conductor structure 114 . Therefore, the lateral double-diffused MOS device of the present invention has an adjustable FOM, which will be described in detail in the second embodiment.

In addition, FIG. 1 shows that the conductor structure 114 is aligned with the same side of the branch portion 112a, but the present invention is not limited thereto; in another embodiment, the length of the conductor structure 114 may be longer or shorter, such as the conductor structure 114 is closer to the drain region 108 than the branch portion 112 a ; or, the branch portion 112 a is closer to the drain region 108 than the conductor structure 114 .

From the point of view of simplifying the process, the conductor structure 114 and the finger gate 112 can be made of the same material, and the same photomask and etching process can be used. For example, the conductor structure 114 can be n-type polysilicon, p-type polysilicon or undoped polysilicon, wherein if the gate finger 112 is n-type polysilicon, then the conductor structure 114 can also be n-type polysilicon, which can be compatible with the fingers Formed gate 112 together. On the contrary, if the conductor structure 114 is p-type polysilicon or undoped polysilicon, it may need to be fabricated separately.

Please refer to FIG. 1 and FIG. 2 at the same time, the gate insulating layer 116 is located between the finger gate 112 and the active area AA and between the conductor structure 114 and the active area AA; that is, the gate insulating layer 116 is located between the finger gate Between the electrode 112 and the well region 101 , and the gate insulating layer 116 is located between the conductor structure 114 and the well region 101 . The gate insulating layer 116 is, for example, a silicon oxide layer.

4 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a second embodiment of the present invention, in which the same parts and components are represented by the same element symbols as those in the first embodiment, and the same parts and components are For relevant content, reference may also be made to the content of the first embodiment, and details are not repeated here.

Referring to FIG. 4 , the difference between this embodiment and the first embodiment is that the number of conductor structures 400 , 402 disposed between the two branch portions 112 a is more than one. Since the definition of FOM is Ron_sp × gate-drain charge (Qgd), where Qgd is related to the gate-drain capacitance (Cgd), and Ron_sp is related to the number of branches 112a of the finger gate 112, so the number of conductor structures 402 is increased Cgd can be changed, thereby changing Qgd, and at the same time, reducing the number of branches 112a of the finger gate 112 will increase Ron_sp, thereby achieving the effect of adjusting FOM.

5 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a third embodiment of the present invention, wherein the same parts and components are represented by the same element symbols as in the first embodiment, and the same parts and components are For relevant content, reference may also be made to the content of the first embodiment, and details are not repeated here.

Please refer to FIG. 5 , the difference between this embodiment and the first embodiment is that the thick oxide layer can be composed of several separated blocks 500, and the well region 101 between the blocks 500 is defined as a Reduced Surface Field (Reduced Surface Field) , RESURF) District 502. The RESURF region 502 can further reduce Ron_sp of the lateral double-diffused MOS device of the third embodiment. The RESURF region 502 is arranged in parallel between the branch portion 112 a and the conductor structure 114 , and the RESURF region 502 also extends to the drain region 108 . The length of each block 500 may be slightly longer than the length of the conductive structure 114 , wherein the aforementioned length refers to the size of the block 500 and the conductive structure 114 in the longitudinal direction.

In summary, in the lateral double-diffused metal oxide semiconductor device of the present invention, the gate finger can maintain the low specific on-resistance of the device, and at least one conductor structure arranged between the branches of the gate finger can accelerate charging Therefore, the FOM can be adjusted according to the operating voltage range, by the number of conductor structures or by the ratio of the number of branches to conductor structures. In addition, if the conductor structure and the gate fingers are fabricated by the same process, there is no need to adjust process conditions or add steps, which has the advantage of saving manufacturing cost and time.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: base 101: well area 102: Body doped region 104: volume pickup area 106: source region 108: Drain area 110: thick oxide layer 112: finger gate 112a: branch 114, 400, 402: conductor structure 116: gate insulating layer 500: block 502: Reduced surface electric field area AA: active area d1: first distance d2: the second distance

FIG. 1 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a lateral double-diffused metal oxide semiconductor device along line II-II' in Fig. 1 . Fig. 3 is a schematic cross-sectional view of the lateral double-diffused metal oxide semiconductor device along line III-III' in Fig. 1 . FIG. 4 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a second embodiment of the present invention. FIG. 5 is a schematic top view of a lateral double-diffused metal oxide semiconductor device according to a third embodiment of the present invention.

101: well area

102: Body doped region

104: volume pickup area

106: source region

108: Drain area

110: thick oxide layer

112: finger gate

112a: branch

114: Conductor structure

AA: active area

d1: first distance

d2: the second distance

Claims (10)

A lateral double diffused metal oxide semiconductor device, comprising: a substrate having a well region; a body doped region disposed in the well region; a body pickup region disposed within the body doped region; Several source regions are respectively arranged in the body doped region on both sides of the body pickup region; A plurality of drain regions are respectively arranged in the well region separated from the body-doped region by a first distance; a thick oxide layer disposed between the plurality of drain regions and the body-doped region to define an active region, and the thick oxide layer is separated from the body-doped region by a second distance; A plurality of finger-shaped gates are respectively arranged on the active region outside the plurality of source regions, wherein each of the finger-shaped gates includes several branch parts, and the several branch parts are arranged in parallel and extending onto said thick oxide layer; a plurality of conductor structures disposed between the plurality of branches and across the active region and the thick oxide layer, wherein the plurality of conductor structures are electrically insulated from the plurality of finger gates; and The gate insulating layer is located between the gate fingers and the active area and between the conductor structure and the active area. The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein the number of the conductor structures disposed between the two branch portions is one or several. The lateral double diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures are connected to the source electrode. The lateral double diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures are electrically floating. The lateral double-diffused metal oxide semiconductor device as claimed in claim 1, wherein the thick oxide layer is composed of several separated blocks, and the well region between the several blocks is defined as several lower surface An electric field (RESURF) region, the plurality of RESURF regions are arranged in parallel between the branch portion and the conductor structure, and extend to the plurality of drain regions. The lateral double-diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures and the gate fingers are made of the same material. The lateral double-diffused metal oxide semiconductor device as claimed in claim 1, wherein the plurality of conductor structures are n-type, p-type or undoped polysilicon. The lateral double-diffused metal oxide semiconductor device according to claim 1, wherein the source region and the drain region are doped regions of the first conductivity type, and the body doped region and the body pick-up region are The doped region of the second conductivity type. The lateral double-diffused metal oxide semiconductor device according to claim 8, wherein the substrate is a substrate of the second conductivity type, and the well region is a well region of the first conductivity type. The lateral double-diffused metal oxide semiconductor device according to claim 8, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

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