CN111129123B - Combined etch stop layer for contact field plate etching, integrated chip and forming method thereof - Google Patents

Combined etch stop layer for contact field plate etching, integrated chip and forming method thereof Download PDF

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Publication number
CN111129123B
CN111129123B CN201910454866.2A CN201910454866A CN111129123B CN 111129123 B CN111129123 B CN 111129123B CN 201910454866 A CN201910454866 A CN 201910454866A CN 111129123 B CN111129123 B CN 111129123B
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field plate
layer
etch stop
stop layer
dielectric material
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CN111129123A (en
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卢卉庭
王培伦
钟于彰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to integrated chips. In some embodiments, the integrated chip has a gate structure disposed over the substrate between the source region and the drain region and a dielectric layer extending laterally from over the gate structure to between the gate structure and the drain region. A combined etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. The contact etch stop layer directly contacts the upper surface and sidewalls of the combined etch stop layer. The field plate is laterally surrounded by a first inter-layer dielectric (ILD) layer, and extends from the top of the first ILD layer, through the contact etch stop layer, and into the combined etch stop layer. The embodiment of the invention also provides a method for forming the combined etching stop layer and the integrated chip by etching the contact field plate.

Description

Combined etch stop layer for contact field plate etching, integrated chip and forming method thereof
Technical Field
Embodiments of the invention relate generally to the field of semiconductor technology and, more particularly, to a combined etch stop layer for contact field plate etching, an integrated chip, and methods of forming the same.
Background
Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). An Integrated Chip (IC) may use many different types of transistor devices depending on the application of the IC. In recent years, the growing market for cellular and RF (radio frequency) devices has led to a significant increase in the use of high voltage transistor devices. For example, high voltage transistor devices are commonly used for power amplifiers in RF transmit/receive chains due to their ability to handle high breakdown voltages (e.g., greater than about 50V) and high frequencies.
Disclosure of Invention
According to an aspect of the present invention, there is provided an integrated chip including: a gate structure disposed between the source region and the drain region over the substrate; a dielectric layer extending laterally from above the gate structure to between the gate structure and the drain region; combining an etch stop layer comprising a plurality of different dielectric materials stacked over the dielectric layer; a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer; and a field plate laterally surrounded by and extending from a top of a first inter-layer dielectric (ILD) layer, vertically through the contact etch stop layer, and into the combined etch stop layer.
According to another aspect of the present invention, there is provided an integrated chip including: a gate structure disposed over the substrate; a resist protection oxide extending laterally from above the gate structure beyond an outermost sidewall of the gate structure; a combined etch stop layer comprising a first dielectric material over the etch resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material; a plurality of conductive contacts laterally surrounded by a first interlayer dielectric (ILD) layer over the substrate; and a field plate extending from a top of the first interlayer dielectric layer to the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein the combined etch stop layer laterally contacts sidewalls of the field plate and vertically separates the field plate from the resist protection oxide.
According to yet another aspect of the present invention, there is provided a method of forming an integrated chip, comprising: forming a gate structure over a substrate between a source region and a drain region within the substrate; forming a dielectric layer over the gate structure and between the gate structure and the drain region; forming a combined etch stop layer over the dielectric layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials; forming a first inter-layer dielectric (ILD) layer over the combined etch stop layer; selectively etching the first interlayer dielectric layer to simultaneously define a contact opening extending to the substrate and a field plate opening extending to the combined etch stop layer; and filling the contact opening and the field plate opening with one or more conductive materials.
Drawings
Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale according to standard practice in the industry. Indeed, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device with a field plate.
Fig. 2-4 illustrate cross-sectional views of some additional embodiments of the disclosed high voltage Lateral Diffusion MOSFET (LDMOS) device with a field plate.
Fig. 5-6 illustrate cross-sectional views of some embodiments of field plate biasing arrangements of high voltage LDMOS devices implemented by metal interconnect wiring.
Fig. 7A-7C illustrate cross-sectional views of some embodiments of high-voltage LDMOS devices in different switch-isolation configurations.
Fig. 8 shows a cross-sectional view of a high voltage transistor device with a field plate with the source down (i.e., source below).
Fig. 9A-9B illustrate some embodiments of the disclosed high voltage LDMOS with a field plate on the metal line layer.
Fig. 10 illustrates some embodiments of a high voltage LDMOS device with a self-aligned drift region.
Fig. 11 illustrates a flow chart of some embodiments of a method of forming a high voltage transistor device having a field plate.
Fig. 12-19 illustrate cross-sectional views of some embodiments of a method of forming a high voltage transistor device having a field plate.
Fig. 20-24 illustrate some embodiments of the disclosed high voltage transistor device with a combined etch stop layer defining a field plate.
Fig. 25-32 illustrate cross-sectional views of some embodiments of methods of forming a high voltage transistor device having a combined etch stop layer defining a field plate.
Fig. 33 illustrates a flow chart of some embodiments of a method of forming a high voltage transistor device having a combined etch stop layer defining a field plate.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not limiting. For example, forming a first component over or on a second component in the following description may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components such that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as "below" …, "" below "…," "lower," "above" …, "upper," and the like, may be used herein to facilitate description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatially relative descriptors used herein interpreted accordingly as well.
High voltage transistor devices are typically constructed with field plates. A field plate is a conductive element that is placed over the channel region to enhance the performance of the high voltage transistor device by controlling the electric field generated by the gate electrode (e.g., reducing the peak electric field). By controlling the electric field generated by the gate electrode, a higher breakdown voltage can be achieved for the high voltage transistor device. For example, LDMOS (laterally diffused metal oxide semiconductor) transistor devices typically include a field plate that extends from a channel region to an adjacent drift region disposed between the channel region and a drain region.
The field plates may be formed in a number of different ways. For example, the field plate may be formed by a conductive gate material (e.g., polysilicon) extending from the gate electrode toward the drift region. However, in this configuration, the field plate remains consistent with the gate bias (bias), which increases the gate-to-drain capacitance (Cgd) and deteriorates the switching losses of the device. Alternatively, the conductive gate material may be patterned to form individual field plates. This configuration reduces the gate-to-drain capacitance (Cgd), but the placement of the field plates is typically limited by design rules. In yet another alternative embodiment, non-gate materials may be used for the field plate formation. However, this solution uses additional processing steps, which increase the manufacturing costs of the resulting integrated chip.
Accordingly, the present invention relates to a high voltage transistor device having a field plate made of non-gate material, wherein the field plate is formed simultaneously with the formation of back-end-of-line (BEOL) metal layers to enable a low cost manufacturing method. In some embodiments, the high voltage transistor device has a gate electrode disposed on the substrate between a source region and a drain region within the substrate. The dielectric layer extends laterally from above the gate electrode to a drift region disposed between the gate electrode and the drain region. The field plate is located within a first inter-layer dielectric (ILD) layer overlying the substrate. The field plate extends laterally from above the gate electrode to above the drift region and vertically from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts having the same material as the field plate extend vertically from a bottom surface of the first ILD layer to a top surface of the first ILD layer.
Fig. 1 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device 100 having a field plate 122.
The high voltage transistor device 100 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate. The semiconductor substrate 102 has a first doping type and the source region 104 and the drain region 106 have a second doping type with a higher doping concentration than the semiconductor substrate 102. In some embodiments, the first doping type is n-type doping and the second doping is p-type doping.
A gate structure 116 is disposed over the semiconductor substrate 102 at a location laterally disposed between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. Upon receiving a bias voltage, the gate electrode 108 is configured to generate an electric field to control movement of charge carriers within the channel region 112 laterally disposed between the source region 104 and the drain region 106. For example, during operation, the gate-source voltage (V GS ) May be selectively applied to the gate electrode 108 opposite the source region 104 to form a conductive channel in the channel region 112. At the application of V GS To form a conductive channel, a drain-source voltage (V DS ) To move charge carriers (e.g., as indicated by arrows 105) between the source region 104 and the drain region 106.
The channel region 112 extends laterally from the source region 104 to an adjacent drift region 114 (e.g., drain extension region). The drift region 114 includes a second doping type having a relatively low doping concentration to provide a higher resistance at high operating voltages. A gate structure 116 is disposed over the channel region 112. In some embodiments, the gate structure 116 may extend from above the channel region 112 to a position above a portion of the drift region 114.
A first interlayer dielectric (ILD) layer 118 is disposed over the semiconductor substrate 102. One or more conductive metal structures are disposed within ILD layer 118. In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 configured to provide a vertical connection between the source region 104, the drain region 106, or the gate electrode 108 and a first back-end-of-line (BEOL) metal line layer 128, wherein the first BEOL metal line layer 128 is disposed within the second ILD layer 126 above the first ILD layer 118.
The one or more conductive metal structures may further include a field plate 122 disposed within the first ILD layer 118 at a location above portions of the gate electrode 108 and the drift region 114. The field plate 122 comprises the same conductive material as the plurality of contacts 120. The field plate 122 may be disposed over a dielectric layer 124, wherein the dielectric layer 124 is configured to separate the field plate 122 from the drift region 114 and the gate electrode 108. In some embodiments, dielectric layer 124 extends laterally across field plate 122 in one or more directions.
During operation, field plate 122 is configured to act on an electric field generated by gate electrode 108. The field plate 122 may be configured to alter the distribution of the electric field generated by the gate electrode 108 in the drift region 114, thereby enhancing the internal electric field of the drift region 114 and increasing the drift doping concentration of the drift region 114, thereby enhancing the breakdown voltage capability of the high voltage transistor device 100.
Fig. 2 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device, wherein the high voltage transistor device includes a high voltage Laterally Diffused MOSFET (LDMOS) device 200 having a field plate 214.
The LDMOS device 200 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 include highly doped regions of a second doping type different from the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type. In some embodiments, the doping concentration of the source region 104 and the drain region 106 may be about 10 19 cm -3 And about 10 20 cm -3 Within a range between.
A contact region 208 (e.g., P-type tap or n-type tap) having a first doping type (e.g., P + doping) laterally adjoins the source region 104. The contact region 208 provides an ohmic connection with the semiconductor substrate 102. In some embodiments, the doping concentration of the contact region 208 may be about 10 18 cm -3 And about 10 20 cm -3 Within a range between. The contact region 208 and the source region 104 are disposed within the body region 202. The body region 202 has a first doping type and a doping concentration higher than that of the semiconductor substrate 102. For example, the doping concentration of the semiconductor substrate 102 may be about 10 14 cm -3 And about 10 16 cm -3 Within a range between, and the doping concentration of the body region 202 may be largeAbout 10 16 cm -3 And about 10 18 cm -3 Within the range between.
The drain region 106 is disposed within the drift region 204, wherein the drift region is disposed within the semiconductor substrate 102 at a location laterally adjacent to the body region 202. The drift region 204 includes a second doping type having a relatively low doping concentration, wherein the drift region 204 provides a higher resistance when the LDMOS device 200 is operated at high voltage. In some embodiments, the doping concentration of the drift region 204 may be about 10 15 cm -3 And about 10 17 cm -3 Within the range between.
The gate structure 210 is disposed over the semiconductor substrate 102 at a location laterally disposed between the source region 104 and the drain region 106. In some embodiments, the gate structure 210 may extend laterally from above the body region 202 to a position above a portion of the drift region 204. The gate structure 210 includes a gate electrode 108, the gate electrode 108 being separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may include silicon dioxide (SiO 2 ) Or a high-k gate dielectric material, and the gate electrode 108 may comprise polysilicon or a metal gate material (e.g., aluminum). In some embodiments, the gate structure 210 may further include sidewall spacers 212 disposed on opposite sides of the gate electrode 108. In some embodiments, sidewall spacers 212 may include nitride-based sidewall spacers (e.g., comprising SiN) or oxide-based sidewall spacers (e.g., siO 2 SiOC, etc.).
One or more dielectric layers 124 are disposed over the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 extend continuously from over a portion of the gate electrode 108 to over a portion of the drift region 204. In some embodiments, one or more dielectric layers 124 may be conformally disposed on the drift region 204, the gate electrode 108, and the sidewall spacers 212.
The field plate 214 is disposed over the one or more dielectric layers 124 and is laterally surrounded by the first ILD layer 118. The field plate 214 extends from above the gate electrode 108 to above the drift region 204. The dimensions of field plate 214 may vary depending on the dimensions and characteristics of LDMOS device 200. In some embodiments, field plate 214 may have a size between about 50 nanometers and about 1 micrometer. In other embodiments, the field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may comprise a dielectric material having a relatively low dielectric constant (e.g., less than or equal to about 3.9), which provides electrical isolation between the plurality of contacts 120 and/or the field plates 122. In some embodiments, the first ILD layer 118 may comprise an ultra low k dielectric material or a low k dielectric material (e.g., siCO).
The field plate 214 extends vertically from the dielectric layer 124 to the top surface of the first ILD layer 118. In some embodiments, the field plate 214 may extend vertically to a height greater than or equal to the height of the contacts 120 and the top surface of the first ILD layer 118. The field plate 122 has a non-planar surface adjacent to one or more dielectric layers 124. The non-planar surface causes the field plate 122 to have a first thickness t in the region above the gate electrode 108 1 And has a thickness t greater than the first thickness t in the region covering the drift region 204 1 Is t of the second thickness t of (2) 2 。
The plurality of contacts 120 are also surrounded by the first ILD layer 118. The plurality of contacts 120 may include a first contact 120a coupled to the contact region 208, a second contact 120b coupled to the drain region 106, and a third contact 120c coupled to the gate electrode 108. In some embodiments, the first contact 120a may include a mating contact (not shown) that contacts the contact region 208 and the source region 104. In some embodiments, the plurality of contacts 120 and the field plate 122 may comprise the same metallic material. For example, the plurality of contacts 120 and the field plate 122 may include one or more of tungsten (W), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), aluminum copper (AlCu), copper (Cu), and/or other similar conductive materials.
Fig. 3 illustrates a cross-sectional view of some additional embodiments of the disclosed high-voltage LDMOS device 300 with a field plate 214.
The LDMOS device 300 includes an isolation region 302, the isolation region 302 being disposed within the drift region 204 at a location laterally disposed between the gate structure 214 and the drain region 106. Isolation region 302 improves isolation between gate structure 210 and drain region 106 to prevent dielectric breakdown between gate structure 210 and drift region 204 when LDMOS device 300 is operated at a large operating voltage. For example, isolation region 302 may be introduced into drift region 204 of an LDMOS device designed to operate at a first breakdown voltage to increase the breakdown voltage of LDMOS device 300 without significantly altering the fabrication process of the LDMOS device. In some embodiments, isolation region 302 may include a Shallow Trench Isolation (STI). In other embodiments, isolation region 302 may comprise field oxide.
Fig. 4 illustrates a cross-sectional view of some additional embodiments of the disclosed high-voltage LDMOS device 400 with a field plate 408.
The LDMOS device 400 comprises a plurality of dielectric layers 402 to 404 arranged between a field plate 408 and the gate structure 210 and/or the drift region 204. The plurality of dielectric layers 402-404 are configured to electrically isolate the field plate 408 from the gate structure 210 and/or the drift region 204. In an embodiment, the plurality of dielectric layers 402-404 may include two or more different dielectric materials. In some embodiments, the plurality of dielectric layers 402-404 may include one or more dielectric layers used during a typical CMOS fabrication process in order to limit additional fabrication steps for electrically isolating the field plate 408 from the gate structure 210 and/or the drift region 204.
For example, the plurality of dielectric layers 402-404 may include a silicide block layer 402. In some embodiments, the silicide blocking layer 402 may include a Resist Protection Oxide (RPO) layer configured to prevent silicide formation. A silicide blocking layer 402 may be disposed over portions of the gate electrode 108 and the drift region 204. In some embodiments, the silicide blocking layer 402 may extend continuously from above the gate electrode 108 to above the drift region 204.
In some embodiments, the plurality of dielectric layers 402-404 may also include a field plate Etch Stop Layer (ESL) 404. The field plate ESL 404 may be disposed over the silicide blocking layer 402 and configured to control etching of the opening of the field plate 408. The field plate ESL 404 may account for differences in etch depth and/or differences in etch rate (e.g., due to etch loading effects) between the contacts 120 and the field plate 408. In some embodiments, field plate ESL 404 may comprise, for example, a silicon nitride (SiN) layer.
In some alternative embodiments (not shown), the plurality of dielectric layers 402-404 may additionally or alternatively include a gate dielectric layer. In such an embodiment, the gate dielectric layer may be disposed laterally adjacent to the gate structure 210 at a location overlying the drift region 204. In some embodiments, the dielectric layer of oxide may comprise silicon dioxide (e.g., siO 2 ) Or a high-k gate dielectric material. In other embodiments, the plurality of dielectric layers 402-404 may additionally or alternatively include an ILD layer (e.g., the first ILD layer 118).
A Contact Etch Stop Layer (CESL) 406 is disposed over the semiconductor substrate 102 and the field plate ESL 404. In some embodiments, CESL406 extends over semiconductor substrate 102 at a location between the plurality of contacts 120 and field plate 408 such that CESL406 abuts sidewalls of the plurality of contacts 120 and field plate 408. CESL406 overlies gate structure 210. In some embodiments, CESL406 may also cover multiple dielectric layers 402-404. In other embodiments, one or more of the plurality of dielectric layers 402-404 (e.g., field plate ESL 404) may cover CESL 406. In some embodiments, CESL406 may include a nitride layer. For example, CESL406 may include silicon nitride (SiN).
A field plate 408 is disposed within the first ILD layer 118 adjacent to the CESL406 and adjacent to one or more of the plurality of dielectric layers 402-404. In some embodiments, field plate 408 extends through CESL406 to abut one or more of the plurality of dielectric layers 402-404. In such an embodiment, one or more of the plurality of dielectric layers 402-404 separates the field plate 408 from the gate structure 210 and the drift region 204.
In some embodiments, field plate 408 may include a first metallic material 410 and a second metallic material 412. The first metal material 410 may include a glue layer disposed along an outer edge of the field plate 408, while the second metal material 412 is embedded within the first metal material 410 in an inner region of the field plate 408 (i.e., the second metal material 412 is separated from the CESL 406 by the first metal material 410). In some embodiments, a liner layer 414 may be disposed between the first ILD layer 118 and the first metal material 410.
In some embodiments, the first metal material 410 disposed along the outer edge of the field plate 408 has a top surface disposed along a substantially planar surface 420 (i.e., a planar surface formed by a planarization process). The planar surface 420 may be aligned with the top surfaces of the plurality of contacts 120. In some embodiments, the first metallic material 410 comprises the same material as the plurality of contacts 120 and the second metallic material 412 comprises the same material as the first metallic line layer 418 that covers the plurality of contacts 120. For example, in some embodiments, the first metal material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).
It should be appreciated that the disclosed field plate allows for a variety of field plate bias configurations that are easily implemented for different design considerations due to its integration with BEOL (back end of line) metallization layers. For example, the field plate bias may be changed by changing the metal wiring layer rather than by changing the design of the disclosed high voltage device. Furthermore, it should be appreciated that biasing the high voltage transistor devices through BEOL metal interconnect wiring allows for the integration of various field plate bias configurations on the same chip using a single manufacturing process flow.
Fig. 5-6 illustrate cross-sectional views of some embodiments of field plate biasing arrangements of high voltage transistor devices implemented with BEOL metal interconnect wiring. Although fig. 5-6 illustrate connection between the field plate 214 and the contact region 208 or gate electrode 108 through a first metal line layer (e.g., 504 or 604), BEOL metal interconnect wiring is not limited thereto. More specifically, it should be appreciated that the field plate 214 may be connected to the source region, gate electrode, drain region, or body contact by any combination of BEOL metal interconnect layers (e.g., first metal line layer, first metal via layer, second metal line layer, etc.).
Fig. 5 illustrates a cross-sectional view of high-voltage LDMOS device 500, wherein field plate 214 is electrically coupled to contact region 208 along conductive path 506. The field plate 214 is connected to a first metal line layer 504 disposed within a second ILD layer 502. The first metal line layer 504 is coupled to the contact 120a adjacent to the contact region 208. By electrically coupling the field plate 214 to the contact region 208, the field plate 214 is biased by a source voltage (source voltage). The low on-resistance Rds (on) and low dynamic power consumption (e.g., low Rds (on) Qgd and BV (i.e., breakdown voltage)) are provided to the high voltage LDMOS device 500 by the source voltage bias field plate 214. Low dynamic power consumption provides good performance during high frequency switching applications.
Fig. 6 illustrates a cross-sectional view of a high-voltage LDMOS device 600 in which field plate 214 is electrically coupled to gate electrode 108 along conductive path 606. The field plate 214 is connected to a first metal line layer 604 disposed within the second ILD layer 602. The first metal line layer 604 is connected to the contact 120b adjacent to the gate electrode 108. By electrically coupling the field plate 214 to the gate electrode 108, the field plate 214 is biased by a gate voltage. The field plate 214 is biased by the gate voltage to provide a low Rds (on) and breakdown voltage for the high voltage LDMOS device 600.
Various field plate bias configurations allow the disclosed field plates to form a versatile high voltage transistor device that can be used for different applications. For example, the on-state resistance Rds (on) of a high voltage transistor device with a gate bias field plate is lower than the Rds (on) of a high voltage transistor device with a source bias field plate. However, rds (on) Qgd of the high voltage transistor device with the source bias field plate is lower than Rds (on) Qgd of the high voltage transistor device with the gate source bias field plate. Thus, a high voltage transistor device having a gate bias field plate (e.g., high voltage LDMOS device 500) may be used in a low frequency switching application (e.g., below 10 MHz), while a high voltage transistor device having a source bias field plate (e.g., high voltage LDMOS device 600) may be used in a high frequency switching application (e.g., above 10 MHz).
Fig. 7A-7C illustrate cross-sectional views of some embodiments of high-voltage LDMOS devices 700 a-700C in different switch-isolation configurations.
As shown in fig. 7A, high-voltage LDMOS device 700a is configured as a low-side switch (e.g., a switch connected to ground in an inverter). In such a configuration, high voltage LDMOS device 700a has source region 104 that is floating such that the voltage on source region 104 may change during the transition period.
As shown in fig. 7B, high-voltage LDMOS device 700B is configured as a high-side switch (e.g., a switch connected to VDD in an inverter). In such a configuration, high-voltage LDMOS device 700b has source region 104 connected to a source voltage. High-voltage LDMOS device 700b has a drift region 702 extending below body region 202 to prevent the source voltage from increasing above the substrate voltage by preventing charge carriers from being transferred from contact region 208 into semiconductor substrate 102 (e.g., by tunneling).
As shown in fig. 7C, high voltage LDMOS device 700C is fully isolated from the substrate to allow for independent biasing. The high voltage transistor device 700c includes a deep well 704 configured to provide vertical isolation and an oppositely doped underlying buried layer 706. In some embodiments, the deep well 704 may have a first doping type (e.g., the same doping type as the body region 202), and the buried layer 706 may have a second doping type.
The high voltage LDMOS device 700c further comprises one or more additional STI regions 206 laterally separating the drain region from the body region 708 and the buried layer 710, wherein the buried layer 710 has the second doping type. Body region 708 overlies deep well 704 and buried layer 710 overlies well region 712 having the second doping type and abutting buried layer 706. The contact 120 is configured to provide a bias voltage to the body region 708 and the buried layer 710 to form junction isolation between the deep well 704 and the buried layer 706 and the well region 712. Junction isolation allows the fully isolated high voltage LDMOS device 700c to operate at a range of bias voltages.
Fig. 8 shows a cross-sectional view of a source down high voltage transistor device 800 with a field plate 214.
The high voltage transistor device 800 includes a substrate 802 having a first doping type (e.g., p+ doping type) with a high doping concentration. Source region 804 is disposed along back side 802b of substrate 802. In various embodiments, the source region 804 may include a highly doped region or a metal layer. An epitaxial layer 806 having a first conductivity type is provided on the front side surface 802f of the substrate 802. The dopant concentration of epitaxial layer 806 is less than the dopant concentration of substrate 802. Source contact region 810, drain region 106, body region 808, and drift region 204 are disposed within the top surface of epitaxial layer 806.
Conductive material 812 extends from the top surface of epitaxial layer 806 into substrate 802. Conductive material 812 may include a highly doped deep well region. The conductive material 812 allows source connection from the backside of the substrate 802, thereby reducing metal routing complexity and achieving various package compatibility. In some embodiments, the field plate 214 may be biased by a source voltage through an electrical path 818, wherein the electrical path 818 extends through a contact 814 adjoining the conductive material 812 and a metal line layer 816 coupled to an upper side of the field plate 214.
Fig. 9A-9B illustrate some embodiments of the disclosed high voltage LDMOS device with a field plate 902 in the metal line layer. While fig. 9A-9B show the field plate on the first metal line layer, it should be understood that the disclosed field plate is not limited to the first metal line layer, but may be implemented on an alternative layer of the BEOL metallization stack.
As shown in the cross-sectional view 900 of fig. 9A, a field plate 902 is disposed in a first metal line layer within a second ILD layer 904 that overlies the first ILD layer 118. In some embodiments, field plate 902 has substantially planar top and bottom surfaces to provide a planar topology for field plate 902. The field plate 902 is vertically separated from the gate structure 210 and the drift region 204 by the first ILD layer 118. The field plate 902 covers portions of the gate electrode 108 and the drift region 204 and is laterally separated from the source region 104 and the drain region 106. For example, the field plate 902 may be laterally separated from the drain region 106 by a distance d. In some embodiments, the field plate 902 may extend laterally from above the gate electrode 108 to above the drift region 204.
As shown in top view 906 of fig. 9B, field plate 902 includes a metal structure that covers gate electrode 108 and portions of drift region 204. The metal structure is not connected to the underlying element by contact 120 or to another metal structure on the first metal line layer. More specifically, the metal structure will be connected to an overlying via (not shown) configured to connect the field plate to the overlying metal line layer so that the field plate 902 can be biased.
Fig. 10 illustrates some embodiments of a disclosed high voltage LDMOS device 1000 with a self-aligned drift region 1002.
The self-aligned drift region 1002 has a sidewall 1002s that is substantially aligned with the sidewalls of the gate electrode 108 and the gate dielectric layer 110. In some alternative embodiments, the self-aligned drift region 1002 may be formed with sidewalls 1002s substantially aligned with the edges of the sidewall spacers 212. By aligning the self-aligned drift region 1002 with the sidewalls of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 and the space s are laterally spaced from the body region 202, thereby minimizing gate-to-drain overlap and achieving low gate-to-drain charge (Qgd) and good high frequency performance. The field plate 214 covering the self-aligned drift region 1002 may further reduce the gate-drain charge (Qgd).
Fig. 11 illustrates a flow chart of some embodiments of a method 1100 of forming a high voltage transistor device having a field plate. The method can form the field plate using process steps already used during standard CMOS fabrication processes, thus providing a low cost universal field plate.
While the disclosed methods (e.g., methods 1100 and 3300) are illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Additionally, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more actions depicted herein may be performed in one or more separate actions and/or phases.
At act 1102, a substrate is provided having a source region and a drain region separated by a channel region. In some embodiments, the substrate may further include a drift region between the source region and the drain region at a location adjacent to the channel region.
At act 1104, a gate structure is formed on the substrate at a location disposed between the source region and the drain region. The gate structure may include a gate dielectric layer and an overlying gate electrode.
At act 1106, a drift region may be formed using a self-aligned process that, in some embodiments, selectively implants the semiconductor substrate according to the gate structure to form the drift region.
At act 1108, one or more dielectric layers are selectively formed over the gate electrode and a portion of the drift region.
At act 1110, a Contact Etch Stop Layer (CESL) and a first interlayer dielectric (ILD) layer are formed over a substrate.
At act 1112, the first ILD layer is selectively etched to define a contact opening and a field plate opening.
At act 1114, the contact opening and the field plate opening are filled with a first metallic material.
At act 1116, a planarization process may be performed to remove excess first metal material overlying the first ILD layer.
At act 1118, a second metal material is deposited corresponding to the first metal line layer. In some embodiments, the second metal material may further fill the field plate opening. In such an embodiment, the second metallic material is embedded within the first metallic material within the field plate opening.
At act 1120, a second interlayer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line layer structure.
Fig. 12-19 illustrate cross-sectional views of some embodiments of methods of forming MOSFET devices with field plates. Although fig. 12-19 are described with respect to method 1100, it should be understood that the structure shown in fig. 12-19 is not limited to such a method, but may be used alone as a structure independent of the method.
FIG. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to act 1102.
As shown in cross-section 1200, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be inherently doped with a first doping type. In various embodiments, semiconductor substrate 102 may comprise any type of semiconductor body (e.g., silicon, SOI) including, but not limited to, a semiconductor die or one or more dies on a wafer or wafer, and any other type of semiconductor and/or epitaxial layer formed thereon and/or otherwise associated therewith.
The semiconductor substrate 102 may be selectively implanted using various implantation steps to form a plurality of implantation regions (e.g., well regions, contact regions, etc.). For example, the semiconductor substrate 102 may be selectively implanted to form the body region 202, the drift region 204, the source region 104, the drain region 106, and the contact region 208. The plurality of implanted regions may be formed by selectively masking the semiconductor substrate 102 (e.g., using a photoresist mask) and then introducing a high energy dopant 1204 (e.g., a p-type dopant species such as boron or an n-type dopant such as phosphorus) into the exposed regions of the semiconductor substrate 102. For example, as shown in cross-section 1200, mask layer 1202 is selectively patterned to expose portions of semiconductor substrate 102, followed by implantation of high energy dopants 1204 therein to form source region 104 and drain region 106.
It should be appreciated that the implant region shown in cross-sectional view 1200 is one example of a possible implant region, and that semiconductor substrate 102 may include other configurations of implant regions, such as any of the configurations shown in fig. 1-10.
Fig. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to act 1104.
As shown in cross-section 1300, a gate structure 210 is formed over the semiconductor substrate 102 at a location disposed between the source region 104 and the drain region 106. The gate structure 210 may be formed by forming a gate dielectric layer 110 over the semiconductor substrate 102, and by forming a gate electrode material 108 over the gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 and the gate electrode material 108 may be deposited by vapor deposition techniques. The gate dielectric layer 110 and the gate electrode material 108 may then be patterned and etched (e.g., in accordance with a photoresist mask) to define the gate structure 210. In some embodiments, sidewall spacers 112 may be formed on opposite sides of gate electrode 108 by: a nitride-based material or an oxide-based material is deposited onto the semiconductor substrate 102 and selectively etched to form the sidewall spacers 112.
FIG. 14 illustrates some embodiments of a cross-sectional view 1400 corresponding to act 1108.
As shown in cross-section 1400, one or more dielectric layers 124 are selectively formed over the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 may be deposited by vapor deposition techniques and subsequently patterned and etched (e.g., according to a photoresist mask). In some embodiments, one or more dielectric layers 124 may be etched to expose a portion of the gate electrode 108 and laterally spaced from the drain region 106.
In some embodiments, the one or more dielectric layers 124 may include a silicide blocking layer, such as a Resist Protection Oxide (RPO) layer. In other embodiments, the one or more dielectric layers 124 may further and/or alternatively include a field plate Etch Stop Layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by vapor deposition techniques. In other embodiments, the one or more dielectric layers 124 may further and/or alternatively include a gate dielectric layer or an inter-layer dielectric (ILD) layer.
FIG. 15 illustrates some embodiments of a cross-sectional view 1500 corresponding to act 1110.
As shown in cross-section 1500, a Contact Etch Stop Layer (CESL) 1502 is formed over a semiconductor substrate 102. In some embodiments, CESL 1502 may be formed by a vapor deposition process. A first interlayer dielectric (ILD) layer 1504 is then formed over the CESL 1502. In some embodiments, the first ILD layer 1504 may comprise an ultra low k dielectric material or a low k dielectric material (e.g., siCO). In some embodiments, the first ILD layer 1504 may also be formed by a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin-on process. It should be understood that the term "inter-layer dielectric (ILD) layer" as used herein may also refer to an inter-metal dielectric (IMD) layer.
FIG. 16 illustrates some embodiments of a cross-sectional view 1600 corresponding to act 1112.
As shown in cross-section 1600, first ILD layer 1504 is selectively exposed to a first etchant 1602, wherein first etchant 1602 is configured to form contact openings 1606 and field plate openings 1608. In some embodiments, the contactThe component opening 1606 may be smaller than the field plate opening 1608. In some embodiments, the first ILD layer 1504 is selectively exposed to a first etchant 1602 according to a mask layer 1604 (e.g., a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have a large etch selectivity between the first ILD layer 1504 and the field plate ESL within the one or more dielectric layers 124. In some embodiments, the first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may have a composition including oxygen (O 2 ) Nitrogen (N) 2 ) Hydrogen (H) 2 ) Argon (Ar) and/or fluorine species (e.g., CF) 4 、CHF 3 、C 4 F 8 Etc.) and one or more etching chemistries. In other embodiments, the first etchant 1602 may include a wet etchant that contains dilute hydrofluoric acid (BHF).
FIG. 17 illustrates some embodiments of a cross-sectional view 1700 corresponding to acts 1114 through 1116.
As shown in cross-section 1700, contact opening 1606 and field plate opening 1608 are filled with a first metallic material 1702. In some embodiments, the first metallic material 1702 may be deposited by a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, the first metallic material 1702 may be formed by physical vapor deposition of a seed layer followed by a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove the excess first metal material 1702 and form a planar surface along the lines 1704.
In some embodiments, the first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, a diffusion barrier layer and/or liner layer may be deposited into contact opening 1606 and field plate opening 1608 prior to depositing first metallic material 1702.
FIG. 18 illustrates some embodiments of a cross-sectional view 1800 corresponding to act 1118.
As shown in cross-section 1800, a second metallic material 1802 is deposited. A second metal material 1802 is formed within the remaining openings in the field plate openings and over the first ILD layer 118. In some embodiments, the second metallic material 1802 may be deposited by a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, the second metallic material 1802 may be formed by physical vapor deposition of a seed layer followed by a plating process. In some embodiments, the second metallic material 1802 may include copper (Cu) or an aluminum copper (AlCu) alloy.
After formation, the second metal material 1802 may be selectively patterned to define one or more metal structures that cover the first metal line layer 418 of the first ILD layer 118. In some embodiments, the second metal material 1802 may be selectively patterned by forming a patterned mask layer (e.g., a photoresist layer or a hard mask layer) (not shown) over the second metal material 1802 and then etching the second metal material 1802 in the areas exposed by the patterned mask layer.
FIG. 19 illustrates some embodiments of a cross-sectional view 1900 corresponding to act 1120.
As shown in cross-section 1900, a second ILD layer 416 is formed over the one or more metal structures of first ILD layer 118 and first metal line layer 418. In various embodiments, second ILD layer 416 may be formed by depositing a second ILD material on one or more metal structures of first ILD layer 118 and first metal line layer 418. After forming the second ILD layer 416, a planarization process (e.g., CMP) is performed to remove excess second ILD layer 416 and expose top surfaces of the one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may comprise an ultra low k dielectric material or a low k dielectric material (e.g., siCO) formed by a vapor deposition process or a spin-on process.
It should be appreciated that the difference in height of the plurality of contacts (e.g., 120) and the field plate (e.g., 122) may cause difficulties during fabrication of the disclosed transistor device. For example, because the field plate (e.g., 122) is formed over the dielectric layer 124 (e.g., resist protection oxide), the field plate (e.g., 122) has a smaller height than the plurality of contacts (e.g., 120). However, the field plate (e.g., 122) and the plurality of contacts (e.g., 120) are formed using the same etching process. The height differences may result in overetching of the field plate opening (e.g., 1608 in fig. 16) or underetching of the contact opening (e.g., 1606 in fig. 16), wherein overetching of the field plate opening may result in shorting between the field plate (e.g., 122) and the conductive channel of the transistor device, and underetching of the contact opening may result in poor connection between the plurality of contacts (e.g., 120) and the source region (e.g., 104), drain region (e.g., 106), and/or gate structure (e.g., 210).
To prevent overetching of the field plate opening or underetching of the contact opening, in some embodiments, a combined etch stop layer may be used to control the etch depth of the field plate opening. By controlling the etch depth of the field plate opening, the combined etch stop layer allows multiple contacts (e.g., 120) and field plates (e.g., 122) to be precisely formed to different heights.
Fig. 20 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device 200 with a combined etch stop layer defining a field plate.
The high voltage transistor device 2000 includes a gate structure 116 disposed over the semiconductor substrate 102. The gate structure 116 includes a gate dielectric layer 110 and an overlying gate electrode 108. In some embodiments, gate structure 116 may have a first thickness th in a range between about 1000 angstroms and about 2000 angstroms 1 . Source region 104 and drain region 106 are disposed in semiconductor substrate 102 on opposite sides of gate structure 116.
A Resist Protection Oxide (RPO) 2002 is disposed over the gate structure 116. RPO 2002 extends laterally from directly above gate structure 116 past the outermost sidewalls of gate structure 116. In some embodiments, RPO 2002 may extend vertically from the upper surface of the gate structure to the upper surface of semiconductor substrate 102 and laterally from directly above gate structure 116 between gate structure 116 and drain region 106. In some embodiments, RPO 2002 may comprise silicon dioxide, silicon nitride, or the like. In some embodiments, RPO 2002 may have a second thickness th in a range between about 100 angstroms and about 1000 angstroms 2 。
A combined etch stop layer 2004 is disposed over RPO 2002. In some embodiments, combined etch stop layer 2044 directly contacts one or more upper surfaces of RPO 2002. A first interlayer dielectric (ILD) layer 118 and a field plate 122 are disposed over the combined etch stop layer 2004. The first ILD layer 118 surrounds the field plate 122 and the plurality of contacts 120, wherein the plurality of contacts 120 are coupled to the source region 104, the drain region 106, and the gate structure 116. In some embodiments, the field plate 122 and the plurality of contacts 120 may include a diffusion barrier (not shown) surrounding a conductive core comprising one or more metals.
The combined etch stop layer 2004 includes a plurality of different dielectric layer materials 2006-2008 stacked over the RPO 2002. In some embodiments, the plurality of different dielectric materials 2006-2008 may have outermost sidewalls that are substantially aligned along a line perpendicular to the upper surface of the semiconductor substrate 102. In some embodiments, the plurality of different dielectric materials 2006-2008 may have outermost sidewalls that are substantially aligned with the outermost sidewalls of RPO 2002. In such an embodiment, the first width of RPO2002 has a second width substantially equal to combined etch stop layer 2004. The plurality of different dielectric materials 2006-2008 have different etching properties, thereby providing respective ones of the plurality of different dielectric materials 2006-2008 having different etching selectivities relative to the etchant. The different etch selectivities allow the combined etch stop layer 2004 to slowly etch the field plate openings (e.g., define the openings of the field plates 122) and thus, tightly control the height of the field plates and enable height differences between the plurality of contacts 120 and the field plates 122 (e.g., such that the plurality of contacts 120 have a higher height than the field plates 122).
For example, in some embodiments, the bottom of field plate 122 contacts combined etch stop layer 2004 along an interface that is located vertically above the bottom surface of one or more of plurality of contacts 120 (e.g., contacts coupled to source region 104 and drain region 106). In such an embodiment, during fabrication of the high voltage transistor device 2000, the combined etch stop layer 2004 reduces the etch rate of the etchant used to form the field plate openings (i.e., define the openings of the field plate 122). The reduced etch rate results in the bottom surface of field plate 122 being higher than the bottom surface of one or more contacts 120.
In some embodiments, the etch stop layer 2004 is combinedMay include a first dielectric material 2006 directly contacting an upper surface of RPO 2002 and a second dielectric material 2008 directly contacting an upper surface of first dielectric material 2006. In some embodiments, the first dielectric material 2006 may have a third thickness th 3 And the second dielectric material 2008 may have a fourth thickness th 4 . In some embodiments, RPO 2002 and combined etch stop layer 2004 may each have a substantially constant thickness between outermost sidewalls. If the third thickness th 3 And a fourth thickness th 4 Too small (e.g., less than the minimum set forth below), the combined etch stop layer 2004 does not effectively stop the etching that forms the field plate opening. If the third thickness th 3 And a fourth thickness th 4 Too large (e.g., greater than the maximum value set forth below), the effect of field plate 122 on high voltage transistor device 2000 is reduced, thereby negatively impacting device performance.
In some embodiments, the first dielectric material 2006 may include silicon nitride (Si x N y ) And the second dielectric material 2008 may include silicon dioxide (SiO 2 ). In such an embodiment, a first thickness th 1 May be in a first range of between about 50 angstroms and about 400 angstroms, and a second thickness th 2 May be in a second range between about 150 angstroms and about 700 angstroms. In other embodiments, the first dielectric material 2006 may include or be silicon dioxide (SiO 2 ) And the second dielectric material 2008 may include or be silicon nitride (Si x N y ) Or silicon oxynitride (SiO) x N y ). In such an embodiment, a first thickness th 1 May be in a first range between about 600 angstroms and about 900 angstroms. In some embodiments, a second thickness th 2 May be in a second range between about 100 angstroms and about 500 angstroms.
Fig. 21A-21B illustrate some additional embodiments of the disclosed high voltage transistor device with a combined etch stop layer defining a field plate.
As shown in cross-sectional view 2100 of fig. 21A, the high voltage transistor device includes a semiconductor substrate 102 having a body region 2106 disposed within a drift region 2104 above a substrate 2102. The source region 104 is disposed within the body region 2106 and the drain region 106 is disposed within the drift region 2104. In some embodiments, the source region 104, the drain region 106, and the drift region 2104 may have a first doping type (e.g., n-type), while the body region 2106 and the substrate 2102 have a second doping type (e.g., p-type) opposite the first doping type. In some embodiments, the source region 104 and the drain region 106 may include highly doped regions (i.e., n+ regions) having a doping concentration that is higher than the doping concentration of the drift region 2104.
A gate structure 116 is disposed over the semiconductor substrate 102 between the source region 104 and the drain region 106. RPO 2002 is disposed above gate structure 116 and extends laterally beyond the outermost sidewalls of gate structure 116. A combined etch stop layer 2004 is disposed between RPO 2002 and field plate 122. In some embodiments, RPO 2002 may surround (close) field plate 122 (i.e., extend beyond the outermost sidewalls of field plate 122) by one or more lateral distances 2108, wherein the one or more lateral distances are in the range of about 0 microns to about 2 microns.
In some embodiments, the field plate 122 may extend to a non-zero depth 2110 in the combined etch stop layer 2004. In such an embodiment, field plate 122 contacts the sidewalls of combined etch stop layer 2004. In various embodiments, field plate 122 may also contact a horizontally extending surface of combined etch stop layer 2004 or a horizontally extending surface of RPO 2002. In some embodiments, the non-zero depth 2110 may be in a range between about 400 angstroms and about 700 angstroms. Because field plate 122 extends into combined etch stop layer 2004, combined etch stop layer 2004 has a first thickness 2112 directly below field plate 122 and a second thickness located outside field plate 122, wherein the second thickness is greater than first thickness 2112. In some embodiments, first thickness 2112 is in a range between about 0 angstroms and about 10000 angstroms. In some additional embodiments, first thickness 2112 is in a range between about 600 angstroms and about 3000 angstroms.
As shown in cross-sectional view 2120 of fig. 21B (along cross-sectional line A-A' of fig. 21A), the width 2114 of the field plate 122 extending in the first direction has a distance in the range between about 150 nanometers and 2000 nanometers. The field plate 122 also has a length 2122 extending in a second direction (perpendicular to the first direction) a distance of less than about 1000 μm.
Referring again to the cross-sectional view of fig. 21A, in some embodiments, the field plate 122 may be laterally separated from the gate structure 116 by a distance 2116. For example, the field plate 122 may be laterally separated from the gate structure 116 by a distance in a range between about 0nm and about 200 nm. In other embodiments (not shown), the field plate 122 may laterally overlap the gate structure 116 (i.e., extend directly above the gate structure 116). For example, the field plate 122 laterally overlaps the gate structure 116 by a distance between about 0nm and about 200 nm.
In some embodiments, silicide layer 2118 is disposed over source region 104, drain region 106, and portions of gate structure 116 not covered by RPO 2002. In various embodiments, silicide layer 2118 may comprise a compound having silicon and a metal, such as nickel, platinum, titanium, tungsten, magnesium, and the like. In some embodiments, silicide layer 2118 has a thickness in a range between about 150 angstroms and about 400 angstroms.
Fig. 22 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device 2200 with a combined etch stop layer defining a field plate.
The high voltage transistor device 2200 includes a gate structure 108 disposed over the semiconductor substrate 102. RPO 2002 and combined etch stop layer 2004 are located over gate electrode 108 and semiconductor substrate 102. A Contact Etch Stop Layer (CESL) 406 is disposed over the combined etch stop layer 2004. In some embodiments, the bottom surface of combined etch stop layer 2004 may directly contact RPO 2002 and the top surface of combined etch stop layer 2004 may directly contact CESL 406.CESL 406 extends laterally beyond the outermost sidewalls of combined etch stop layer 2004 and contacts semiconductor substrate 102. In some embodiments, CESL 406 may have a thickness th in a range between about 100 angstroms and about 1000 angstroms 5 . In some embodiments, CESL 406 may include silicon nitride, silicon carbide, or the like.
The field plate 408 is disposed within the first ILD layer 118 above the CESL 406. In some embodiments, field plate 408 may include a first metallic material 410 and a second metallic material 412. The combined etch stop layer 2004 is disposed laterally between the field plate 408 and the gate structure 116 and vertically between the field plate 122 and the semiconductor substrate 102. RPO 2002 and combined etch stop layer 2004 have sidewalls that contact CESL 406. The combined etch stop layer 2004 further has a horizontally extending surface (e.g., an upper surface) that contacts the CESL 406.
In some embodiments, the field plate 122 may extend into one or more of a plurality of different dielectric materials 2006-2008 within the combined etch stop layer 2004. For example, in some embodiments, the combined etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2008 that contacts an upper surface of the first dielectric material 2006. The field plate 122 may extend through a second dielectric material 2008 (e.g., silicon oxide) and have a bottom surface that contacts a first dielectric material 2006 (e.g., silicon nitride). In such an embodiment, the first dielectric material 2006 may separate the bottommost point of the field plate 122 perpendicularly from the RPO 2002. In other embodiments, field plate 122 may further extend through first dielectric material 2006 and have bottom and/or sidewalls that contact RPO 2002. In some embodiments, the field plate 122 may extend vertically through the second dielectric material 2008 and also be laterally separated from the gate structure 116 by the second dielectric material 2008.
Although the disclosed combined etch stop layer 2004 is shown in fig. 20-22 as having two different dielectric materials 2006-2008 stacked over RPO 2002. It should be understood that the disclosed combined etch stop layer 2004 is not limited to this configuration. More specifically, in various embodiments, the combined etch stop layer 2004 may include additional layers of dielectric material. Fig. 23-24 illustrate some non-limiting examples of alternative embodiments of the disclosed combined etch stop layer 2004.
Fig. 23 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device 2300 having a combined etch stop layer defining a field plate.
The high voltage transistor device 2300 includes a combined etch stop layer 2004 disposed over the RPO 2002. The combined etch stop layer 2004 includes a first dielectric material 2302, contactsA second dielectric material 2304 on an upper surface of the first dielectric material 2302, and a third dielectric material 2306 contacting an upper surface of the second dielectric material 2304. In some embodiments, the first dielectric material 2302 may include or be silicon dioxide (SiO 2 ) The second dielectric material 2304 may include or be silicon nitride (Si x N y ) Or silicon oxynitride (SiO) x N y ) And the third dielectric material 2306 may include either silicon dioxide (SiO 2 )。
In some embodiments, the first dielectric material 2302 may have a first thickness, the second dielectric material 2304 may have a second thickness, and the third dielectric material 2306 may have a third thickness. In some embodiments, the first thickness may be in a first range between about 300 angstroms and about 900 angstroms, the second thickness may be in a second range between about 50 angstroms and about 200 angstroms, and the third thickness may be in a third range between about 200 angstroms and about 600 angstroms.
Fig. 24 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device 2400 having a combined etch stop layer defining a field plate.
The high voltage transistor device 2400 includes a combined etch stop layer 2400 disposed over an RPO 2002. The combined etch stop layer 2400 includes a first dielectric material 2402, a second dielectric material 2404 contacting an upper surface of the first dielectric material 2402, a third dielectric material 2406 contacting an upper surface of the second dielectric material 2404, and a fourth dielectric material 2408 contacting an upper surface of the third dielectric material 2406. In some embodiments, the first dielectric material 2402 may include or be silicon dioxide (SiO 2 ) The second dielectric material 2404 may include or be silicon nitride (Si x N y ) Or silicon oxynitride (SiO) x N y ) And third dielectric material 2406 may include either silicon dioxide (SiO 2 ) And fourth dielectric material 2408 may include or be silicon nitride (Si x N y ) Or silicon oxynitride (SiO) x N y )。
In some embodiments, the first dielectric material 2402 may have a first thickness, the second dielectric material 2404 may have a second thickness, the third dielectric material 2406 may have a third thickness and the fourth dielectric material 2408 may have a fourth thickness. In some embodiments, the first thickness may be in a first range between about 300 angstroms and about 900 angstroms, the second thickness may be in a second range between about 50 angstroms and about 200 angstroms, the third thickness may be in a third range between about 200 angstroms and about 600 angstroms, and the fourth thickness may be in a fourth range between about 50 angstroms and about 200 angstroms.
Fig. 25-32 illustrate cross-sectional views of some embodiments of methods of forming a high voltage transistor device having a combined etch stop layer defining a field plate. Although the cross-sectional views 2500 to 3200 shown in fig. 25 to 32 are described with reference to the method, it should be understood that the structures shown in fig. 25 to 32 are not limited to the method but may exist independently of the method.
As shown in the cross-sectional view of fig. 25, the semiconductor substrate 102 is selectively implanted to form a plurality of implanted regions (e.g., well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form the body region 2106, the drift region 2104, the source region 104, and the drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implant regions (e.g., such as any of the implant regions shown in fig. 1-10). In some embodiments, the plurality of implant regions may be formed by: the semiconductor substrate 102 is selectively masked (e.g., using a photoresist mask) and then a high energy dopant (e.g., a p-type dopant such as boron or an n-type dopant such as phosphorus) is introduced into the exposed regions of the semiconductor substrate 102.
A gate structure 116 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by: a gate dielectric layer 110 is deposited over the semiconductor substrate 102 and a gate electrode 108 is deposited over the gate dielectric layer 110. The gate dielectric layer 110 and gate electrode material 108 may then be patterned (etched in accordance with a photoresist mask and/or hard mask) to define the gate structure 116.
As shown in the cross-sectional view of fig. 26, a resist protection oxide (R) is formed over the gate structure 116PO) 2002.RPO 2002 extends laterally from directly above gate structure 116 past the outermost sidewalls of gate structure 116. RPO 2002 is configured to block silicide formation on underlying layers. In some embodiments, RPO 2002 may be deposited by vapor deposition techniques (e.g., CVD). In some embodiments, RPO 2002 may comprise silicon dioxide (SiO 2 ) Silicon nitride, and the like.
As shown in cross-sectional view 2700 of fig. 27, a combined etch stop layer 2004 comprising a plurality of different dielectric materials 2600 through 2800 is selectively formed over RPO 2002. In some embodiments, a plurality of different dielectric materials 2006-2008 may be sequentially deposited by vapor deposition techniques. In some embodiments, the combined etch stop layer 2004 may comprise a stacked layer, wherein the stacked layer comprises silicon nitride (Si x N y ) Layer, silicon oxynitride (SiO) x N y ) Layers and/or silicon dioxide (SiO) 2 ) Two or more of the middle layers.
In some embodiments, the same masking layer 2702 (e.g., photoresist layer) and etching process may be used to pattern a plurality of different dielectric materials 2006-2008 and RPO 2002. Patterning multiple different dielectric materials 2006-2008 and RPO 2002 using the same masking layer 2702 reduces the cost of combining the etch stop layers 2004. In such an embodiment, the plurality of different dielectric materials 2006-2008 and RPO 2002 may have substantially aligned sidewalls.
As shown in the cross-sectional view of fig. 28, a Contact Etch Stop Layer (CESL) 406 is formed over the semiconductor substrate 102 and the combined etch stop layer 2004. In some examples, CESL 406 may be formed by a vapor deposition process. CESL may include a nitride layer (e.g., si 3 N 4 ) Carbide layer (SiC), etc.
As shown in cross-sectional view 2900 of fig. 29, a first interlayer dielectric (ILD) is formed over CESL 406. In some embodiments, the first ILD layer 118 may comprise an oxide (e.g., siO 2 ) An ultra low k dielectric material, a low k dielectric material (e.g., siCO), etc. In some embodiments, the first ILD layer 118 may be formed by a vapor deposition process.
As shown in the cross-sectional view of fig. 30, the first ILD layer 118 may be selectively exposed to an etchant 3002 (e.g., according to masking layer 3003) to form contact openings 1606 and field plate openings 1608 in the first ILD layer 118. Contact opening 1606 and field plate opening 1608 have etch depth offsets of non-zero distance 3004. In some embodiments, non-zero distance 3004 may be in a range between about 400 angstroms and about 2000 angstroms. In some embodiments, field plate opening 1608 extends into combined etch stop layer 2004 such that sidewalls of combined etch stop layer 2004 define field plate opening 1608. In various embodiments, the combined etch stop layer 2004 or PRO 2002 may define the bottom of the field plate opening 1608.
In some embodiments, etchant 3002 may reduce the thickness of combined etch stop layer 2004 by an amount ranging between about 400 angstroms and about 700 angstroms. In some embodiments, the thickness of the combined etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 0 angstroms and 1000 angstroms. In some additional embodiments, the thickness of the combined etch stop layer 2004 directly below the field plate opening 1608 is in the range between about 300 angstroms and about 900 angstroms of clothe moth.
The etchant 3002 used to form the contact openings 1606 and field plate openings 1608 is selected to etch through the material of the CESL 406. However, because the combined etch stop layer 2004 is formed from a plurality of different materials, the combined etch stop layer 2004 is resistant to the etching of the etchant 3002 to a greater extent. The combination etch stop layer 2004 thus allows the contact opening 1606 to extend to the semiconductor substrate 102 while preventing the field plate opening 1608 from extending to the semiconductor substrate 102. The combination etch stop layer 2004 also allows for a higher degree of uniformity in etch depth between substrates with respect to the same lot and/or at different locations on substrates with respect to different lots of substrates. For example, the combination etch stop layer 2004 allows the etch depth of the field plate opening 1608 on different substrates to be within a deviation of about 2% or less. This etch depth uniformity allows for improved device uniformity and performance compared to devices without the combination etch stop layer 2004.
As shown in the cross-sectional view of fig. 31, contact opening 1606 and field plate opening 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials may be deposited by vapor deposition techniques (e.g., CVD, PVD, PE-CVD, etc.) and/or plating processes (e.g., electroplating or electroless plating). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess conductive material or materials and form a planar surface along line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), and/or tantalum nitride ((TaN). In some embodiments, different barrier and/or liner layers may be deposited in contact opening 1606 and field plate opening 1608 prior to depositing the one or more conductive materials.
As shown in the cross-sectional view of fig. 32, a second ILD layer 126 is formed over the first ILD layer 118 and a first back end of line (BEOL) metal line layer 128 is formed within the second ILD layer 126. In such an embodiment, second ILD layer 126 may be formed by depositing a second ILD layer material over first ILD layer 118. The second ILD layer 126 is then etched to form trenches that extend into the second ILD layer 126. The trenches are filled with conductive material and a planarization process (e.g., CMP) is performed to remove excess conductive material from over the second ILD layer 126.
Fig. 33 illustrates a flow chart of some embodiments of a method 3300 of forming a high voltage transistor device having a combined etch stop layer defining a field plate.
At act 3302, a gate structure is formed over a substrate. Fig. 25 illustrates a cross-sectional view 2500 corresponding to some embodiments of action 3302.
At act 3304, source and drain regions are formed on opposite sides of a gate structure within a substrate. In some additional embodiments, one or more additional doped regions (e.g., body regions, drift regions, etc.) may also be formed within the substrate. FIG. 25 illustrates a cross-sectional view corresponding to some embodiments of act 3304.
At act 3306, a Resist Protection Oxide (RPO) is formed over the gate structure and laterally between the gate structure and the drain region. FIG. 26 illustrates a cross-sectional view 2600 corresponding to some embodiments of act 3306.
At act 3308, a combined etch stop layer is formed over the RPO. FIG. 27 illustrates a cross-sectional view corresponding to some embodiments of act 3308.
At act 3310, a Contact Etch Stop Layer (CESL) is formed over the combined etch stop layer. Fig. 28 illustrates a cross-sectional view 2800 corresponding to some embodiments of act 3310.
At act 3312, a first interlayer dielectric (ILD) layer is formed over the CESL. FIG. 29 illustrates a cross-sectional view 2900 corresponding to some embodiments of act 3312.
At act 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The plurality of contact openings and the field plate opening have different depths. Fig. 30 illustrates a cross-sectional view 3000 corresponding to some embodiments of act 3314.
At act 3316, the plurality of contact openings and the field plate opening are filled with one or more conductive materials. Fig. 31 illustrates a cross-sectional view 3100 corresponding to some embodiments of act 3316.
At act 3318, conductive interconnect lines are formed within the second ILD layer over the first ILD layer. Fig. 32 illustrates a cross-sectional view 3200 corresponding to some embodiments of act 3318.
The invention thus relates to a high voltage transistor device having a field plate, wherein the field plate is formed simultaneously with the formation of the conductive contact. The device has a combined etch stop layer for enabling height differences of the field plate and the conductive contact.
In some embodiments, the present invention relates to integrated chips. The integrated chip includes: a gate structure disposed between the source region and the drain region over the substrate; a dielectric layer extending laterally from above the gate structure to between the gate structure and the drain region; combining an etch stop layer comprising a plurality of different dielectric materials stacked over the dielectric layer; a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer; a field plate laterally surrounded by and from the top of the first ILD layer, extending vertically through the contact etch stop layer, and into the combined etch stop layer. In some embodiments, the combined etch stop layer has a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide. In some embodiments, the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride. In some embodiments, the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material. In some embodiments, the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate. In some embodiments, the combined etch stop layer is in lateral contact with the sidewalls of the field plate. In some embodiments, the bottom of the field plate is separated from the dielectric layer by the combined etch stop layer. In some embodiments, the dielectric layer includes a resist protection oxide, wherein the resist protection oxide has a lower surface that contacts the gate structure and an upper surface that contacts the combined etch stop layer.
In an embodiment, the combined etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.
In an embodiment, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.
In an embodiment, the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.
In an embodiment, the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride.
In an embodiment, the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material.
In an embodiment, the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate.
In an embodiment, the combined etch stop layer is in lateral contact with the sidewalls of the field plate.
In an embodiment, the bottom of the field plate is vertically separated from the dielectric layer by the combined etch stop layer.
In an embodiment, the dielectric layer comprises a resist protection oxide, wherein the resist protection oxide has a lower surface contacting the gate structure and an upper surface contacting the combined etch stop layer.
In other embodiments, the invention relates to integrated chips. The integrated chip includes: a gate structure disposed over the substrate; a resist protection oxide extending laterally from over the gate structure through outermost sidewalls of the gate structure; a combined etch stop layer comprising a first dielectric material over the etch resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material; a plurality of conductive contacts laterally surrounded by a first interlayer dielectric (ILD) layer over the substrate; and a field plate extending from a top of the first ILD layer to the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein the combined etch stop layer laterally contacts sidewalls of the field plate and vertically separates a bottom of the field plate from the resist protection oxide. In some embodiments, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material is an oxide and the second dielectric material is a nitride. In some embodiments, the combined etch stop layer further comprises: and a third dielectric material in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material have the same material. In some embodiments, the integrated chip further comprises: a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer. In some embodiments, the etch-resistant protective oxide has a first width that is equal to a second width of the combined etch stop layer.
In an embodiment, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.
In an embodiment, the first dielectric material is an oxide and the second dielectric material is a nitride.
In an embodiment, the combined etch stop layer further comprises: and a third dielectric material in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material are the same material.
In an embodiment, the integrated chip further comprises: a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer.
In an embodiment, the etch resistant protective oxide has a first width equal to a second width of the combined etch stop layer.
In yet another embodiment, the invention relates to a method of forming an integrated chip. The method comprises the following steps: forming a gate structure over a substrate between a source region and a drain region within the substrate; forming a dielectric layer over the gate structure and between the gate structure and the drain region; forming a combined etch stop layer over the dielectric layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials; forming a first inter-layer dielectric (ILD) layer over the combined etch stop layer; selectively etching the first ILD layer to define both contact openings extending to the substrate and field plate openings extending to the combined etch stop layer; and filling the contact opening and the field plate opening with one or more conductive materials. In some embodiments, the combined etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the method further comprises: forming a masking layer over the combined etch stop layer; and etching the combined etch stop layer and the dielectric layer according to the masking layer.
In an embodiment, the combined etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.
In an embodiment, the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.
In an embodiment, the method further comprises: forming a masking layer over the combined etch stop layer; and etching the combined etch stop layer and the dielectric layer according to the masking layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims (20)

1. An integrated chip, comprising:
A gate structure disposed between the source region and the drain region over the substrate;
a resist protective oxide layer extending laterally from above the gate structure to between the gate structure and the drain region;
combining an etch stop layer comprising a plurality of dielectric materials stacked over the etch resistant protective oxide layer having different etch selectivities to an etchant;
a conductive contact laterally surrounded by a first interlayer dielectric layer over the substrate; and
a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer; and
a field plate laterally surrounded by and extending from the top of the first interlayer dielectric layer, vertically through the contact etch stop layer, and into the combined etch stop layer, the height of the field plate below the top surface of the first interlayer dielectric layer being less than the height of the conductive contact, the combined etch stop layer laterally contacting the side wall of the field plate and vertically separating the field plate from the resist protective oxide layer.
2. The integrated chip of claim 1, wherein the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.
3. The integrated chip of claim 2, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.
4. The integrated chip of claim 2, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.
5. The integrated chip of claim 2, wherein the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride.
6. The integrated chip of claim 2, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the first dielectric material.
7. The integrated chip of claim 1, wherein the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate.
8. The integrated chip of claim 1, wherein the combined etch stop layer is in lateral contact with a sidewall of the field plate.
9. The integrated chip of claim 1, wherein a bottom of the field plate is separated from the resist protection oxide layer vertically by the combined etch stop layer.
10. The integrated chip of claim 1, wherein the resist protection oxide layer has a lower surface that contacts the gate structure and an upper surface that contacts the combined etch stop layer.
11. An integrated chip, comprising:
a gate structure disposed over the substrate;
a resist protection oxide extending laterally from above the gate structure beyond an outermost sidewall of the gate structure;
a combined etch stop layer comprising a first dielectric material over the etch-resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material, the first dielectric material and the second dielectric material having different etch selectivities to an etchant;
a plurality of conductive contacts laterally surrounded by a first interlayer dielectric layer over the substrate; and
a field plate extending from a top of the first interlayer dielectric layer into the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein a height of the field plate below a top surface of the first interlayer dielectric layer is less than a height of at least one of the conductive contacts, the combined etch stop layer laterally contacting sidewalls of the field plate and vertically separating the field plate from the resist protection oxide.
12. The integrated chip of claim 11, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.
13. The integrated chip of claim 11, wherein the first dielectric material is an oxide and the second dielectric material is a nitride.
14. The integrated chip of claim 11, wherein the combined etch stop layer further comprises:
and a third dielectric material in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material are the same material.
15. The integrated chip of claim 11, further comprising:
a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer.
16. The integrated chip of claim 11, wherein the resist protection oxide has a first width equal to a second width of the combined etch stop layer.
17. A method of forming an integrated chip, comprising:
forming a gate structure over a substrate between a source region and a drain region within the substrate;
Forming a resist protection oxide layer over the gate structure and between the gate structure and the drain region;
forming a combined etch stop layer over the etch resistant protective oxide layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials, the plurality of dielectric materials having different etch selectivities to etchants;
forming a first interlayer dielectric layer over the combined etch stop layer;
selectively etching the first interlayer dielectric layer to simultaneously define a contact opening extending to the substrate and a field plate opening extending into the combined etch stop layer, the field plate opening having a height less than a height of the contact opening, and the combined etch stop layer vertically separating the field plate opening from the resist protection oxide layer; and
the contact openings and the field plate openings are filled with one or more conductive materials.
18. The method of claim 17, wherein the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.
19. The method of claim 18, wherein the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.
20. The method of claim 17, further comprising:
forming a masking layer over the combined etch stop layer; and
the combined etch stop layer and the etch resistant protective oxide layer are etched in accordance with the masking layer.
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