CN115148689A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN115148689A
CN115148689A CN202110339425.5A CN202110339425A CN115148689A CN 115148689 A CN115148689 A CN 115148689A CN 202110339425 A CN202110339425 A CN 202110339425A CN 115148689 A CN115148689 A CN 115148689A
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dielectric layer
layer
etch stop
bit line
stop layer
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林育祈
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An embodiment of the present invention provides a semiconductor device and a method for forming the same, the semiconductor device including: a substrate, a gate, source/drain regions, a first dielectric layer, an etch stop layer, a second dielectric layer, an additional dielectric layer, a conductive contact, and a bit line. The gate is located on the substrate. The source/drain region is located at the side of the gate in the substrate. The first dielectric layer is located above the grid electrode. The etching stop layer is located on the first dielectric layer. The second dielectric layer is located on the etching stop layer. The additional dielectric layer is located in the second dielectric layer and the etch stop layer. The conductive contact passes through the first dielectric layer and is electrically connected to the source/drain region. The bit line passes through the second dielectric layer, the etching stop layer and the additional dielectric layer and is electrically connected with the conductive contact.

Description

Semiconductor device and method of forming the same
Technical Field
Embodiments of the invention relate to a semiconductor device and a method of forming the same
Background
The flash memory device has a bit line overlying and electrically coupled to the source/drain region of the select gate through a conductive contact and a conductive contact. Generally, the width of the top surface of the conductive contact is formed to be greater than the width of the bottom surface of the bit line to facilitate alignment and contact of the bit line to the conductive contact. However, as flash memory designs continue to shrink in size, short circuits between conductive contacts and adjacent bit lines to their overlying bit lines are prone to occur. Therefore, how to avoid or reduce the short circuit between the conductive contact and the bit line is an urgent problem to be solved in the art.
Disclosure of Invention
Embodiments of the present invention provide a flash memory device and a method of forming the same, which can prevent a short circuit from occurring between a conductive contact and a bit line.
An embodiment of the present invention provides a semiconductor device, including: a substrate, a gate, a source/drain region, a first dielectric layer, an etch stop layer, a second dielectric layer, an additional dielectric layer, a conductive contact, and a bit line. The gate is located on the substrate. The source/drain region is located at the side of the gate in the substrate. The first dielectric layer is located above the grid electrode. The etching stop layer is located on the first dielectric layer. The second dielectric layer is located on the etching stop layer. The additional dielectric layer is located in the second dielectric layer and the etch stop layer. The conductive contact passes through the first dielectric layer and is electrically connected to the source/drain region. The bit line passes through the second dielectric layer, the etching stop layer and the additional dielectric layer and is electrically connected with the conductive contact.
An embodiment of the present invention provides a method for forming a semiconductor device, including: forming a first dielectric layer; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer and the etch stop layer to form openings in the second dielectric layer and the etch stop layer; forming an additional dielectric layer in the opening; forming a patterned mask layer on the second dielectric layer and the additional dielectric layer; performing an etching process according to the patterned mask layer to remove the second dielectric layer, the additional dielectric layer, the etch stop layer and portions of the first dielectric layer, and form bit line trenches and via holes; removing the patterned mask layer; and filling the bit line trench and the via hole with a conductive material to form a bit line in the bit line trench and a conductive contact in the via hole.
In summary, the present invention forms an opening in an etching stop layer sandwiched in a dielectric layer and fills the opening with a dielectric material, and then forms a bit line trench and a via hole in the dielectric layer and the etching stop layer simultaneously by using a single etching process. Then, a conductive material is formed in the bit line trench and the via hole to simultaneously form a bit line and a conductive contact. The conductive contact formed by this method is self-aligned to the bit line and has a top surface width that is no greater than a bottom surface width of the bit line. Thus, shorting problems between the conductive contact and other bit lines adjacent to its overlying bit line can be avoided.
Drawings
Fig. 1 illustrates a semiconductor device according to some embodiments of the invention;
FIG. 2A illustrates a cross-sectional view of the semiconductor device taken along line I-I' of FIG. 1, in accordance with some embodiments of the present invention;
fig. 2B illustrates a cross-sectional view of the semiconductor device taken along line II-II' of fig. 1, in accordance with some embodiments of the present invention;
fig. 3-8A, 8B illustrate cross-sectional and corresponding plan or top views of various intermediate steps of a method of fabricating a bit line and a conductive contact of a semiconductor device according to some embodiments;
fig. 4B, 5B, 7B, 8B are plan views taken along linebase:Sub>A-base:Sub>A 'of fig. 4A, 5A, 7A, 8A, respectively, and fig. 4A, 5A, 7A, 8A are sectional views taken along line B-B' of fig. 4B, 5B, 7B, 8B, respectively;
fig. 6B is a top view of fig. 6A, and fig. 6A is a sectional view taken along line B-B' of fig. 6B.
Detailed Description
Fig. 1 illustrates a semiconductor device 500 according to some embodiments of the inventions. Fig. 2A illustrates a cross-sectional view of a semiconductor device 500 taken along line I-I' of fig. 1, according to some embodiments of the invention. Fig. 2B illustrates a cross-sectional view of the semiconductor device 500 taken along line II-II' of fig. 1, in accordance with some embodiments of the present invention.
Referring to fig. 1, 2A, and 2B, in some embodiments, the semiconductor device 500 may be or may include a memory device, such as a flash memory device. As shown in fig. 2A and 2B, the semiconductor device 500 includes a substrate 10. The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound, or a semiconductor alloy. For example, the semiconductor substrate may comprise a silicon substrate. The silicon substrate may be an undoped silicon substrate or a doped silicon substrate. The doped silicon substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate.
The substrate 10 includes a plurality of isolation structures 8 (shown in fig. 2B) and an active region 9 defined by the isolation structures 8. The material of the isolation structure 8 comprises an insulating material, such as silicon oxide. In some embodiments, the isolation structures 8 may comprise Shallow Trench Isolation (STI).
In some embodiments, as shown in fig. 2A, a plurality of gate structures 15 and 18 are disposed on the active region 9 of the substrate 10. The gate structure 15 may include a tunneling dielectric layer 11, a floating gate 12, an inter-gate dielectric layer 13, and a control gate 14. The gate structure 18 includes, for example, a gate dielectric layer 16 and a select gate 17. Gate structure 18 may also be referred to as a select gate structure. In some embodiments, gate structure 18 includes gate structures 18a and 18b, and multiple gate structures 15 may be located between gate structures 18a and 18 b. The materials of floating gate 12, control gate 14, and select gate 17 may each comprise polysilicon, a metal, or a metal alloy, such as copper, aluminum, tungsten, or alloys thereof. The materials of tunnel dielectric layer 11, inter-gate dielectric layer 13, and gate dielectric layer 16 may each comprise a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.
A plurality of source/drain regions 19 are disposed in the substrate 10 and are located at the sides of the plurality of gate structures 15 and 18. Some of the source/drain regions 19 may be located between select gate structures 15 and gate structures 18 and act as common source/drain regions for gate structures 15 and 18. The source/drain regions 19 may be doped regions in the substrate 10 and may include P-type dopants or N-type dopants. The P-type dopant includes, for example, boron, and the N-type dopant includes, for example, phosphorus or arsenic.
In some embodiments, a dielectric layer 100 is disposed on the substrate 10. The dielectric layer 100 is made of a material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The dielectric layer 100 covers sidewalls and top surfaces of the gate structures 15 and 18, and may be a single-layer or multi-layer structure. Conductive contacts 101 and 22 are embedded in dielectric layer 100 and electrically connected to source/drain regions 19 of gate structures 18a and 18b, respectively. The conductive contacts 101 and 22 may also be referred to as source/drain contacts. In some embodiments, the source line SL is disposed on the conductive contact 22 and electrically connected to the source/drain region 19 of the gate structure 18b through the conductive contact 22.
The dielectric layer 102, the etch stop layer 103, the dielectric layer 104, and the dielectric layer 106 (fig. 2B) are disposed on the dielectric layer 100. The bit line BL and the conductive contact 112 are embedded in the dielectric layer, the etch stop layer 103, the dielectric layer 104, and the dielectric layer 106 and electrically connected to the conductive contact 101. In the embodiment of the present invention, the bit line BL is integrally formed with the conductive contact 112, and there is no interface between the bit line BL and the conductive contact 112. The formation method and structural features regarding the bit line BL and the conductive contact 112 will be described in detail below.
In some embodiments, control gate 14 serves as a word line WL and select gate 17 serves as a select gate line SG. The select gate lines SG may include select gate lines SGD and SGs. For example, select gate 17 in gate structure 18a may serve as select gate line SGD, and select gate 17 in gate structure 18b may serve as select gate line SGS.
Referring to fig. 1 and 2A, in some embodiments, a plurality of select gate lines SGS and SGD and a plurality of word lines WL are disposed side by side and may extend parallel to each other along a direction D1. A plurality of word lines WL may be located between the select gate lines SGS and SGD. The source line SL is connected to the source/drain region 19 at the side of the select gate line SGS, and may extend in the direction D1. In some embodiments, the bit line BL is located above the select gate line SG and the word line WL, and extends in the direction D2. The direction D1 and the direction D2 are, for example, parallel to the top surface of the substrate 10, and the direction D2 may be perpendicular to the direction D1. The conductive contact 112 is located below the bit line BL and extends from the bottom of the bit line BL to the conductive contact 101 along the direction D3. The direction D3 is, for example, perpendicular to the top surface of the substrate 10.
Fig. 3, 4A, 4B-8A, 8B are cross-sectional and corresponding plan or top views of various intermediate steps of a method of fabricating the bit line BL and the conductive contact 112 in a semiconductor device 500 according to some embodiments of the present invention. For simplicity and clarity, fig. 3-8A/8B only show a portion of the semiconductor device 500, and some components (e.g., the substrate 10, the gate structures 15/18, etc.) are omitted in fig. 3-8A/8B.
Referring to fig. 3, in some embodiments, a dielectric layer 100 is formed on the substrate 10 (fig. 2A). The dielectric layer 100 may be formed by a suitable deposition process, such as Chemical Vapor Deposition (CVD). Conductive contacts 101 are formed in the dielectric layer 100. Conductive contacts 101 pass through the dielectric layer 100 to electrically connect to source/drain regions 19 (fig. 2A) in the substrate below the dielectric layer 100. The material of the conductive contact 101 may include a metal or metal alloy, such as copper, tungsten, aluminum, alloys thereof, or combinations thereof. In some embodiments, the formation of the conductive contacts 101 may include the following processes: the dielectric layer 100 is patterned by a photolithography and etching process to form a via in the dielectric layer 100, and then a metal material is formed on the dielectric layer 100 by a suitable deposition process (e.g., CVD, physical Vapor Deposition (PVD)) to fill the via. Thereafter, the excess metal material over the top surface of the dielectric layer 100 is removed using a planarization process. The metal material remaining in the via forms the conductive contact 101. In some embodiments, the top surface of the conductive contact 101 is substantially flush with the top surface of the dielectric layer 100.
Still referring to fig. 3, in some embodiments, a dielectric layer 102, an etch stop layer 103, and a dielectric layer 104 are sequentially formed on the dielectric layer 100 and the conductive contact 101, respectively, using a suitable deposition process (e.g., CVD). The materials of the dielectric layers 102 and 104 are similar to the material of the dielectric layer 100 and may be the same as or different from each other. The etch stop layer 103 is of a different material than the dielectric layers 102, 104. For example, the etch stop layer 103 comprises a dielectric material, such as silicon nitride, silicon oxynitride, or the like. In some embodiments, the material of the dielectric layers 102 and 104 comprises silicon oxide, and the material of the etch stop layer 103 comprises silicon nitride.
In some embodiments, a patterned masking layer 105 is formed on dielectric layer 104. Patterned masking layer 105 comprises, for example, a patterned photoresist. The patterned mask layer 105 has a plurality of mask openings 105a, exposing a portion of the top surface of the dielectric layer 104. In some embodiments, the plurality of mask openings 105a are respectively located at corresponding positions directly above the conductive contacts 101, and the dimensions (e.g., width, area) of the mask openings 105a are greater than the top dimensions of the corresponding conductive contacts 101.
Referring to fig. 4A, the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102 are patterned to form an opening OP. The patterning includes performing an etching process using the patterned mask layer 105 as an etching mask to remove portions of the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102 exposed by the mask opening 105a and to form an opening OP in the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102. In other words, the opening 105a of the patterned mask layer 105 is transferred into the dielectric layer 104, the etch stop layer 103 and/or the dielectric layer 102 to form the opening OP.
The opening OP extends at least through the dielectric layer 104 and the etch stop layer 103, and may in some embodiments further extend into the dielectric layer 102. In some embodiments, the etching process is stopped in the dielectric layer 102, such that the bottom surface of the opening OP exposes the dielectric layer 102 and is lower than the topmost surface of the dielectric layer 102. In some other embodiments, the etching process is stopped when the etch stop layer 103 is removed and the top surface of the dielectric layer 102 is just exposed, i.e., the etching process may not remove the dielectric layer 102 and the bottom surface of the opening OP may be substantially flush with the bottom surface of the etch stop layer 103. In other words, the sidewall of the opening OP exposes the dielectric layer 104, the etch stop layer 103 and/or the dielectric layer 102. The bottom surface of the opening OP exposes the dielectric layer 102. In some embodiments, the opening OP has a sloped sidewall and a size (e.g., width) gradually decreasing from top to bottom, but the invention is not limited thereto. In alternative embodiments, the opening OP may have substantially vertical sidewalls, i.e., the opening OP may have a uniform size (e.g., width) from top to bottom.
Fig. 4B showsbase:Sub>A plan view along linebase:Sub>A-base:Sub>A' of fig. 4A, that is,base:Sub>A top view of the etch stop layer 103. Fig. 4A is a sectional view taken along line B-B' of fig. 4B. As shown in fig. 4B, a plurality of openings 103a are located in the etch stop layer 103. The opening 103a is a portion of the opening OP defined by the sidewall of the etch stop layer 103. In some embodiments, the plurality of openings 103a may be arranged in an array, and the openings 103a of two adjacent rows may be staggered with respect to each other. In other words, the etch stop layer 103 is opened and has a plurality of openings 103a defined by its sidewalls.
Referring to fig. 4A and 5A, the patterned mask layer 105 is removed, and then the opening OP is filled with the dielectric layer 106. The dielectric layer 106 may also be referred to as an additional dielectric layer. The material of the dielectric layer 106 is similar to the material of the dielectric layers 104, 102, and may be the same as or different from the material of the dielectric layers 104/102, and different from the material of the etch stop layer 103. In some embodiments, the dielectric layer 106 comprises silicon oxide. The formation of the dielectric layer 106 may include the following processes: after removing the patterned mask layer 105, a dielectric material is formed using a suitable deposition process (e.g., CVD), which may be formed to fill the opening OP and cover the top surface of the dielectric layer 104. In some embodiments, a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process) is then performed to remove the dielectric material on the top surface of the dielectric layer 104, and the dielectric material remaining in the opening OP forms the dielectric layer 106. In some embodiments, the top surface of the dielectric layer 106 is substantially flush with the top surface of the dielectric layer 104. However, the invention is not limited thereto. In some alternative embodiments, the planarization process does not completely remove the dielectric material on the top surface of the dielectric layer 104, such that the dielectric layer 106 fills the opening OP and extends to cover the top surface of the dielectric layer 104.
Fig. 5B showsbase:Sub>A plan view along linebase:Sub>A-base:Sub>A' of fig. 5A, i.e.,base:Sub>A top view of the etch stop layer 103 andbase:Sub>A portion of the dielectric layer 106. Fig. 5A is a sectional view taken along line B-B' of fig. 5B. Referring to fig. 5A and 5B, the dielectric layer 106 is disposed on the dielectric layer 102 and is laterally surrounded by the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102. The sidewalls of the dielectric layer 106 are in contact with the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102, and the bottom surface of the dielectric layer 106 is in contact with the dielectric layer 102. In other words, the opened opening 103a of the etch stop layer 103 is filled with the dielectric layer 106.
Referring to fig. 6A, a mask layer 108 is formed on the dielectric layers 104 and 106. In some embodiments, the mask layer 108 may be formed by a multi-patterning process, such as a self-aligned double patterning (SADP) process. For example, the formation of the mask layer 108 includes the following processes: a plurality of photoresist patterns are formed on the dielectric layers 104 and 106 through a photolithography process. A hard mask layer is then formed on the dielectric layers 104/106 to cover the plurality of photoresist patterns. And finally, carrying out an etch-back process to remove part of the hard mask layer, and forming a gap wall of the photoresist pattern by the remaining hard mask layer covering the side wall of the photoresist pattern. The photoresist pattern is then removed, and the spacers constitute the mask layer 108.
Fig. 6B is a top view of fig. 6A according to some embodiments. Fig. 6B is a sectional view taken along line B-B' of fig. 6A.
Referring to fig. 6A and 6B, the mask layer 108 has a plurality of mask openings 108a. In some embodiments, the plurality of openings 108a are, for example, a plurality of trenches extending in parallel along the direction D2. Each opening 108a exposes a portion of the top surface of the dielectric layer 106 and a portion of the top surface of the dielectric layer 104, and a portion of the opening 108a is located directly above the conductive contact 101 and the opening 103a of the etch stop layer 103. In other words, the opening 108a overlaps the opening 103a of the etch stop layer 103 and the conductive contact 101 in the direction D3. In some embodiments, the width of opening 108a is no greater than (e.g., less than or substantially equal to) the width of opening 103a. Herein, the width of the opening 108a and the width of the opening 103a refer to their widths in the direction D1.
Referring to fig. 7A, the dielectric layer 104, the dielectric layer 106, the etch stop layer 103 and the dielectric layer 102 are patterned to form a trench 109a and a via 109b. The patterning includes performing an etching process using the mask layer 108 as an etching mask to remove portions of the dielectric layer 104, the dielectric layer 106, the etch stop layer 103, and the dielectric layer 102 exposed by the openings 108a and form a plurality of openings 109. In some embodiments, each opening 109 includes a trench 109a in spatial communication with one another and a via 109b located below the trench 109 a. The trenches 109a may also be referred to as bitline trenches.
The trenches 109a extend parallel to each other along the direction D2, and the vias 109b extend downward from the bottoms of the trenches 109a in the direction D3 to expose the top surfaces of the conductive contacts 101, respectively. The trench 109a includes a first portion FP and a second portion SP adjacent to and communicating with each other. The first portion FP extends at least through the dielectric layer 104 and the etch stop layer 103, and may in some embodiments extend further into the dielectric layer 102. The bottom surface of the first portion FP exposes the dielectric layer 102. The second portion SP and the via 109b are in spatial communication with each other, and pass through the dielectric layer 106 and the dielectric layer 102, exposing the top surface of the conductive contact 101.
In some embodiments, the forming of the opening 109 includes removing portions of the dielectric layer 104, the etch stop layer 103, and the dielectric layer 102 exposed by the mask opening 108a to form the first portion FP of the trench 109 a. The formation of the opening 109 further includes removing a portion of the dielectric layer 106 exposed by the mask opening 108a and the dielectric layer 102 thereunder to form a second portion SP of the trench 109a and a via 109b. In some embodiments, the etchant used for the etching process has a high etch selectivity of the dielectric layers 106, 104, 102 (e.g., silicon oxide) to the etch stop layer 103 (e.g., silicon nitride). For example, the etching process has substantially the same etching rate for the dielectric layers 106/104/102, and has a first etching rate. The etch process has a second etch rate for the etch stop layer 103, and the second etch rate may be much lower than the first etch rate.
In the etching process, since the first portion FP of the trench 109a is formed by removing the etching stop layer 103, and the second portion SP of the trench 109a and the via hole 109b are formed by removing the etching stop layer 103, the etching process removes the dielectric layers 106 and 102 at a faster etching rate while removing the etching stop layer 103 to form the first portion FP of the trench 109a, thereby forming the second portion BP of the trench 109a and forming the deeper via hole 109b. In some embodiments, when the etching process is stopped, the via 109b extends to expose the top surface of the conductive contact 101, and the trench 109a extends to expose the dielectric layer 102. The bottom surface of the trench 109a may be substantially flush with the bottom surface of the etch stop layer 103 or lower than the topmost surface of the dielectric layer 102.
Fig. 7B showsbase:Sub>A plan view along linebase:Sub>A-base:Sub>A' of fig. 7A. Fig. 7A is a sectional view taken along line B-B' of fig. 7B. As shown in fig. 7A and 7B, a portion of the dielectric layer 106 embedded in the etch stop layer 103 is removed. In some embodiments, the width W1 of the trench 109a is smaller than the width W2 of the dielectric layer 106, and the remaining portions of the dielectric layer 106 are located on two opposite sides of the trench 109a and can be separated by the trench 109 a. The second portion SP of the trench 109a is located in the dielectric layer 106 and is defined by at least the sidewall of the dielectric layer 106.
Referring to fig. 8A, the mask layer 108 is removed, and the bit line BL and the conductive contact 112 are formed in the trench 109a and the via 109b. In some embodiments, the material of the bit line BL and the conductive contact 112 may include a metal or a metal alloy, such as copper, aluminum, tungsten, an alloy thereof, or a combination thereof. In some embodiments, the formation of the bit line BL and the conductive contact 112 includes the following processes: after removing the mask layer 108, a conductive material is formed on the dielectric layers 104/106 by a suitable deposition process such as CVD/PVD to fill the trenches 109a and the vias 109b, and then a planarization process (e.g., CMP) is used to remove excess portions of the conductive material above the top surfaces of the dielectric layers 104/106, the conductive material remaining in the trenches 109a forming the bit lines BL, and the conductive material remaining in the vias 109b forming the conductive contacts 112. In some embodiments, the top surface of the bit line BL is substantially flush with the top surfaces of the dielectric layer 106 and the dielectric layer 104.
Fig. 8B showsbase:Sub>A plan view along linebase:Sub>A-base:Sub>A' of fig. 8A. Fig. 8A is a sectional view taken along line B-B' of fig. 8B.
Referring to fig. 8A and 8B, in some embodiments, a plurality of bit lines BL extend along a direction D2 in parallel with each other. The conductive contact 112 is located between the bit line BL and the conductive contact 101 to electrically connect the bit line BL to the conductive contact 101. Each bit line BL includes a first portion 113a and a second portion 113b. The first portion 113a is located in the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102. In some embodiments, the bottom surface of the first portion 113a is in contact with the dielectric layer 102, and may be substantially flush with or below the bottom surface of the etch stop layer 103 (or flush with or below the topmost surface of the dielectric layer 102). The sidewalls of the first portion 113a are in physical contact with the dielectric layer 104, the etch stop layer 103, and/or the dielectric layer 102. The second portion 113b of the bit line BL is located in the dielectric layer 106 and may further extend into the dielectric layer 102. The bottom surface (shown in phantom in fig. 8A) of the second portion 113b is substantially flush with the bottom surface of the first portion 113a and is in contact with the conductive contact 112. The sidewalls of the second portion 113b are surrounded by the dielectric layer 106 and are in physical contact with the dielectric layer 106. In some embodiments, the second portion 113b is spaced apart from the dielectric layer 104 and the etch stop layer 103 by the dielectric layer 106 therebetween. The bottom surface of the bit line 113 may be above, substantially flush with, or below the bottom surface of the dielectric layer 106. The conductive contacts 112 are embedded in the dielectric layer 102 and laterally surrounded by the dielectric layer 102. In some embodiments, the conductive contact 112 is embedded in both the dielectric layer 102 and the dielectric layer 106, and its sidewalls are in contact with both the dielectric layers 102 and 106.
The bit line BL is integrally formed with the conductive contact 112. There is no interface between the bit line BL and the conductive contact 112. The top width Wt of the conductive contact 112 is not greater than the bottom width Wb of the bit line BL. In some embodiments, the top width Wt of the conductive contact 112 is effectively equal to the bottom width Wb of the bit line. It should be noted that the top width Wt of the conductive contact 112 and the bottom width Wb of the bit line BL described herein refer to their widths in the direction D1.
In the embodiment of the invention, the bit line trench and the dielectric hole are formed by one-time etching process, and then the conductive material is filled in the bit line trench and the dielectric hole to simultaneously form the bit line and the conductive contact. Therefore, the bit line and the conductive contact are integrally formed, and the risk of short circuit between the conductive contact and the bit line adjacent to the bit line on the conductive contact can be avoided or reduced. In addition, the etching process and the depth of the via hole can be better controlled by adjusting the thickness of the etching stop layer.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
a gate located on the substrate;
a source/drain region in the substrate to the side of the gate;
a first dielectric layer over the gate;
an etch stop layer on the first dielectric layer;
a second dielectric layer on the etch stop layer;
an additional dielectric layer in the second dielectric layer and the etch stop layer;
a conductive contact passing through the first dielectric layer and electrically connected to the source/drain region; and
a bit line passing through the second dielectric layer, the etch stop layer, and the additional dielectric layer and electrically connected to the conductive contact.
2. The semiconductor device of claim 1, wherein there is no interface between the bit line and the conductive contact.
3. The semiconductor device of claim 1, wherein the bit line comprises:
a first portion in the first dielectric layer and the etch stop layer; and
a second portion connected with the first portion and overlying the conductive contact, wherein the second portion is spaced apart from the first dielectric layer and the etch stop layer by the additional dielectric layer.
4. The semiconductor device of claim 1, wherein the bit line extends along a first direction, a top width of the conductive contact is no greater than a bottom width of the bit line in a second direction, the second direction perpendicular to the first direction.
5. The semiconductor device according to claim 1, further comprising:
the inner dielectric layer is positioned between the first dielectric layer and the substrate and covers the side wall and the top surface of the grid; and
a source/drain contact in the interlayer dielectric layer and connected to the source/drain region, wherein the conductive connection is electrically connected to the source/drain region through the source/drain contact.
6. A method of forming a semiconductor device, comprising:
forming a first dielectric layer;
forming an etch stop layer on the first dielectric layer;
forming a second dielectric layer on the etch stop layer;
patterning the second dielectric layer and the etch stop layer to form openings in the second dielectric layer and the etch stop layer;
forming an additional dielectric layer in the opening;
forming a patterned mask layer on the second dielectric layer and the additional dielectric layer;
performing an etching process according to the patterned mask layer to remove portions of the second dielectric layer, the additional dielectric layer, the etch stop layer, and the first dielectric layer and form bit line trenches and vias;
removing the patterned mask layer; and
and filling conductive materials in the bit line trenches and the dielectric holes to form bit lines in the bit line trenches and conductive contacts in the dielectric holes.
7. The method of claim 6, wherein the patterned masking layer has a mask opening to expose a portion of the second dielectric layer and a portion of the additional dielectric layer, and the mask opening is disposed directly above a portion of the additional dielectric layer that is embedded in the etch stop layer.
8. The method of claim 7, wherein a width of the mask opening is less than a width of the portion of the additional dielectric layer.
9. The method for forming a semiconductor device according to claim 6, wherein the etching process comprises:
removing a portion of the second dielectric layer and a portion of the etch stop layer thereunder to form a first portion of the bit line trench; and
removing a portion of the additional dielectric layer and a portion of the first dielectric layer thereunder to form a second portion of the bit line trench and the via thereunder.
10. The method of forming a semiconductor device according to claim 6, wherein the bit line is electrically connected to a source/drain contact through the conductive contact, the source/drain contact being connected to a source/drain region of a select gate.
CN202110339425.5A 2021-03-30 2021-03-30 Semiconductor device and method of forming the same Pending CN115148689A (en)

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Publication number Priority date Publication date Assignee Title
CN1493087A (en) * 2000-12-26 2004-04-28 ����Τ�����ʹ�˾ Method for eliminating reaction between photoresist and organosilicate glass (OSG)
CN104867967A (en) * 2014-02-26 2015-08-26 台湾积体电路制造股份有限公司 Semiconductor Device And Fabricating Method Thereof
CN111129123A (en) * 2018-10-30 2020-05-08 台湾积体电路制造股份有限公司 Combined etching stop layer for contact field plate etching, integrated chip and forming method thereof
US20200365451A1 (en) * 2019-05-16 2020-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures using via holes filled with dielectric film first and structures formed thereby

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1493087A (en) * 2000-12-26 2004-04-28 ����Τ�����ʹ�˾ Method for eliminating reaction between photoresist and organosilicate glass (OSG)
CN104867967A (en) * 2014-02-26 2015-08-26 台湾积体电路制造股份有限公司 Semiconductor Device And Fabricating Method Thereof
CN111129123A (en) * 2018-10-30 2020-05-08 台湾积体电路制造股份有限公司 Combined etching stop layer for contact field plate etching, integrated chip and forming method thereof
US20200365451A1 (en) * 2019-05-16 2020-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures using via holes filled with dielectric film first and structures formed thereby

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