CN207781610U - Power semiconductor - Google Patents

Abstract

This application discloses power semiconductors.The power semiconductor includes：Multiple grooves in semiconductor substrate, semiconductor substrate are the first doping type, and multiple grooves include first area to the third region for being located at semiconductor substrate first to third groove；Division grid structure in first groove and second groove；At least part is located at the shield wiring in third groove；And source electrode, gate electrode and the bucking electrode being electrically connected with source region, grid conductor and shield wiring, wherein, shield wiring is electrically connected with shielded conductor, and shield wiring includes the second part filled the first part of third groove and be laterally extended in semiconductor substrate surface, and second part is for rerouting.The power semiconductor improves charge balance effect using the shield wiring of independent extraction electrode, and by shield wiring for rerouting to improve yield of devices and reliability.

Description

Power semiconductor

Technical field

The utility model is related to technical field of electronic devices, more particularly, to power semiconductor.

Background technology

Power semiconductor is also known as power electronic devices, including power diode, thyristor, VDMOS (vertical double expansions Dispersed metallic oxide semiconductor) field-effect transistor, LDMOS (lateral diffusion metal oxide semiconductor) field-effect transistors with And IGBT (insulated gate bipolar transistor) etc..VDMOS field-effect transistors include the shape on the apparent surface of semiconductor substrate At source region and drain region, in the on-state, longitudinal flow of the electric current mainly along semiconductor substrate.

In the high frequency of power semiconductor uses, lower conduction loss and switching loss are evaluation device performances Important indicator.On the basis of VDMOS field-effect transistors, further develop groove type MOS field-effect transistor, wherein Grid conductor is formed in the trench, and gate-dielectric is formed on trenched side-wall to separate grid conductor and semiconductor layer, thus The direction of side wall forms raceway groove in the semiconductor layer along groove.Groove (Trench) technique from level by raceway groove due to becoming vertical Directly, the influence for eliminating planar structure parasitism JFET resistance, makes cellular size be substantially reduced.It is close to increase primitive unit cell on this basis Degree improves the overall width of unit area chip interior raceway groove, so that it may so that channel width-over-length ratio of the device on unit silicon chip increases To make electric current increase, conducting resistance declines and relevant parameter is optimized, and realizes smaller size of tube core and possesses bigger Power and high performance target, therefore trench process is more and more applies in novel power semiconductor.

However, with the raising of cell density, electrode resistance can increase, and switching loss accordingly increases, and gate leakage capacitance Cgd is straight Connect the switching characteristic for being related to device.In order to reduce gate leakage capacitance Cgd, division gate groove (Split Gate are further developed Trench is abbreviated as SGT) type power semiconductor, wherein grid conductor extends to drift region, while grid conductor and leakage It is separated using thick-oxide between pole, to reduce gate leakage capacitance Cgd, improves switching speed, reduce switching loss.With This shielded conductor below grid conductor and is connected simultaneously with source electrode, common to be grounded, flat to introduce charge Weigh effect, has reduction surface field (Reduced Surface Field, abbreviation in the vertical direction of power semiconductor For RESURF) effect, it is further reduced conducting resistance Rdson, to reduce conduction loss.

Cutting for the manufacturing method key step of SGT power semiconductors according to prior art is shown respectively in Fig. 1 a and 1b Face figure.As shown in Figure 1a, groove 102 is formed in semiconductor substrate 101.The first insulating layer is formed in the lower part of groove 102 103, shielded conductor 104 fills groove 102.On the top of groove 102, two openings separated by shielded conductor 104 are formed.Into One step, as shown in Figure 1 b, gate-dielectric is formed in the upper portion side wall of groove 102 and the expose portion of shielded conductor 104 105, then conductive material is filled to form two grid conductors 106 in two openings that shielded conductor 104 separates.

In the SGT power semiconductors, shielded conductor 104 is connected with the source electrode of power semiconductor, For generating RESURF effects.Two grid conductors 106 are located at the both sides of shielded conductor 104.Shielded conductor 104 is partly led with power It is separated by the first insulating layer 103 between the drain region of body device, is separated by gate-dielectric 105 between gate electrode 106.Grid It is separated by gate-dielectric 105 between well region in conductor 106 and semiconductor substrate 101, to form raceway groove in well region.Such as Shown in figure, the thickness of the first insulating layer 103 is less than the thickness of gate-dielectric 105.

According to SGT theories, no matter which kind of SGT structure, the material of shielded conductor 104 is required for and the isolation of the second conductive material And the material for isolation needs to meet certain capacitance parameter, is otherwise susceptible to the short circuit of grid source, gate leakage capacitance Cgd exceptions etc. Failure.How optimised devices structure and to meet the parameter and reliability requirement of product, while wiring method being accomplished most efficient, low Cost is the content to be studied of those skilled in the art.

Utility model content

In view of the above problems, the purpose of this utility model is to provide a kind of power semiconductors, wherein using independent The shield wiring of extraction electrode improves charge balance effect, and the wiring area of shielded conductor using separation layer to reduce technique Step.

It is according to the present utility model in a first aspect, provide a kind of manufacturing method of power semiconductor, including：First Multiple grooves are formed in the semiconductor substrate of doping type, the multiple groove includes be located at the semiconductor substrate The first of one region to third region is to third groove；Splitting bar knot is formed in the first groove and the second groove Structure, the division grid structure include shielded conductor, grid conductor and are clipped in second insulating layer between the two；In the third ditch At least part of shield wiring is formed in slot；The second doping type is formed in the region of the semiconductor substrate adjacent trench Body area, second doping type is opposite with first doping type；The first doping class is formed in the body area The source region of type；And formed be electrically connected respectively with the source region, source conductor and shield wiring source electrode, gate electrode and Bucking electrode, wherein the shield wiring is electrically connected with the shielded conductor, and the shield wiring includes filling described the The first part of three grooves and the second part being laterally extended in the semiconductor substrate surface, the second part is for weight Wiring.

Preferably, the step of dividing grid structure is formed in the first groove and the second groove includes：Described Form insulating laminate on the side wall and bottom of first groove and the second groove, the insulating laminate include the first insulating layer and Second insulating layer, first insulating layer surround the second insulating layer；In the upper of the first groove and the second groove Portion and lower part are respectively formed opening and the shielded conductor；Described in the removal of the top of the first groove and the second groove A part for first separation layer；Gate-dielectric is formed on the side wall on the first groove top；And form the grid Conductor is to fill the opening, wherein between the grid conductor and the shielded conductor by the gate-dielectric each other every From being isolated from each other by the gate-dielectric between the grid conductor and the body area, the shielded conductor is partly led with described It is isolated from each other by the insulating laminate between body substrate.

Preferably, include the step of formation shield wiring in the third groove：The third groove side wall and Insulating laminate is formed on bottom, the insulating laminate includes the first insulating layer and second insulating layer, and first insulating layer surrounds The second insulating layer；The shield wiring is formed to fill the third groove, wherein the shield wiring is partly led with described It is isolated from each other by the insulating laminate between body substrate.

Preferably, the shielding is formed simultaneously in the first groove, the second groove and the third groove to lead Body and the shield wiring.

Preferably, the step of forming the grid conductor include：Form conductor layer, first part's filling of the conductor layer The opening, second part are laterally extended above the semiconductor substrate surface；And the etching conductor layer is to remove The second part of conductor layer is stated, the conductor layer stays in the first part in the first groove and the second groove and forms institute State grid conductor.

Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area, The bucking electrode is located in the third region, the first area, the second area and the third region each other every It opens.

Preferably, first insulating layer is made of silica, and the second insulating layer is by being selected from silicon nitride, nitrogen oxides Or at least one of polysilicon composition, the separation layer are made of silica.

Preferably, the thickness of first insulating layer is in the range of 500 to 50000 angstroms, the thickness of the second insulating layer For degree in the range of 50 to 5000 angstroms, the thickness of the separation layer is in the range of 0.5 to 5 micron.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple The bottom width of groove.

Preferably, the step of forming the shielded conductor forms the step of shield wiring and forms the grid and lead The step of body, respectively includes depositing at least once.

Second aspect according to the present utility model provides a kind of power semiconductor, including：In semiconductor substrate Multiple grooves, the semiconductor substrate is the first doping type, and the multiple groove includes being located at semiconductor lining The first of the first area at bottom to third region is to third groove；Division in the first groove and the second groove Grid structure, the division grid structure include shielded conductor, grid conductor and are clipped in second insulating layer between the two；At least one Divide the shield wiring being located in the third groove；Positioned at the areas the semiconductor substrate Zhong Ti, the body area is adjacent to described One groove top, and be the second doping type, second doping type is opposite with first doping type；Positioned at the body Source region in area, the source region are first doping type；And with the source region, the grid conductor and the shielding cloth Source electrode, gate electrode and the bucking electrode that line is electrically connected, wherein the shield wiring is electrically connected with the shielded conductor It connects, and the shield wiring includes filling the first part of the third groove and in semiconductor substrate surface transverse direction The second part of extension, the second part is for rerouting.

Preferably, the division grid structure in the first groove and the second groove includes：Positioned at described first The insulating laminate of groove and the second groove lower sides and bottom, the insulating laminate include that the first insulating layer and second are exhausted Edge layer, first insulating layer surround the second insulating layer；Positioned at the screen of the first groove and the second groove lower part Cover conductor；And the grid conductor positioned at the first groove and the first groove top, wherein the grid conductor and institute It states and is isolated from each other by the gate-dielectric between shielded conductor, by grid electricity between the grid conductor and the body area Medium is isolated from each other, and is isolated from each other by the insulating laminate between the shielded conductor and the semiconductor substrate.

Preferably, the source electrode is located in the first area, and the gate electrode is located in the second area, The bucking electrode is located in the third region, the first area, the second area and the third region each other every It opens.

Preferably, first insulating layer is made of silica, and the second insulating layer is by being selected from silicon nitride, nitrogen oxides Or at least one of polysilicon composition.

Preferably, the thickness of first insulating layer is in the range of 500 to 50000 angstroms, the thickness of the second insulating layer Degree is in the range of 50 to 5000 angstroms.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

Preferably, the sidewall slope of the multiple groove so that the top width of the multiple groove is more than the multiple The bottom width of groove.

Preferably, the power semiconductor is selected from cmos device, BCD devices, mosfet transistor, IGBT and Xiao One kind in special based diode.

In the method according to the utility model embodiment, SGT structures are formed in power semiconductor, wherein Insulating laminate is formed between shielded conductor and semiconductor substrate, to reduce gate leakage capacitance Cgd.The SGT structures include with it is described Source electrode, gate electrode and the bucking electrode that source region, the grid conductor and the shield wiring are electrically connected, the screen Wiring is covered to be electrically connected with the shielded conductor.The shield wiring of independent extraction electrode on shielded conductor for example for individually applying Bias voltage, so as to improve charge balance effect.Using separation layer so that the division grid structure and shielded conductor of different zones can To be formed in public step, to reduce manufacturing cost.This method realizes SGT structures by better simply processing step, Complex process in common process is solved, is susceptible to the problems such as grid source is short-circuit, gate leakage capacitance Cgd is abnormal to meet the ginseng of product While number and reliability requirement, wiring method is accomplished into most efficient, low cost in conjunction with specific process step.With prior art phase Than, be based on 0.25~0.35um techniques, this method can by the photoresist mask used in currently manufactured technique reduce 3~ 4 photoresist masks.

The utility model embodiment use a kind of reduction source drain capacitance separate gate power semiconductor device structure and its Forming method can also apply in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.

Description of the drawings

By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from, in the accompanying drawings：

The section of the manufacturing method key step of power semiconductor according to prior art is shown respectively in Fig. 1 a and 1b Figure.

Fig. 2 shows the flow charts of the manufacturing method of power semiconductor according to the ... of the embodiment of the present invention.

Fig. 3 a to 3i show the sectional view of method, semi-conductor device manufacturing method different phase according to the ... of the embodiment of the present invention.

Specific implementation mode

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Reference numeral indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown Certain well known parts.For brevity, the semiconductor structure that can be obtained after several steps described in a width figure.

It should be appreciated that in the structure of outlines device, it is known as positioned at another floor, another area when by a floor, a region When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also include other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario The form of presentation of face " or " A is on B and abuts therewith ".In this application, " A is in B " indicates that A is located in B, and And A and B is abutted rather than A is located in the doped region formed in B.

In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices The general designation of conductor structure, including all layers formed or region.

Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art Material is constituted.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC and IV race semiconductor, such as Si、Ge。

Fig. 2 shows the flow chart according to the manufacturing methods of the SGT power semiconductors of the utility model embodiment, Fig. 3 a The sectional view in different step is shown respectively to 3i.It is described according to the utility model embodiment below in conjunction with Fig. 2 and 3a to 3i Manufacturing method the step of.

This method starts from semiconductor substrate 101.Semiconductor substrate is, for example, to be doping to the silicon substrate of N-type, the silicon substrate Longitudinal uniform doping, resistivity is for example between the range of 1~15 Ω cm.Semiconductor substrate has opposite first surface And second surface.Preferably, in the first surface of semiconductor substrate, pass through the works such as photoetching, etching, ion implanting, impurity activation Skill forms the partial pressure ring structure of power semiconductor, and the partial pressure ring structure belongs to the well known knot of one kind of this field device architecture Structure part, this will not be detailed here.Preferably, it is brilliant that the semiconductor substrate 101 used in the present embodiment could be formed with MOS field-effects The semiconductor devices such as body pipe, IGBT isolated-gate field effect transistor (IGFET)s, Schottky diode.

In step S101, in the first area of semiconductor substrate 101 201, second area 202 and third region 203 It is respectively formed groove 102, as shown in Figure 3a.

The technique for being used to form groove 102 includes forming Etching mask by photoetching and etching, via Etching mask Opening etching removal semiconductor substrate 101 expose portion.

In this embodiment, first area 201 refers to that the wiring area of source region in SGT structures, second area 202 refer to It is the wiring area of grid conductor in SGT structures, second area 203 refers to the wiring area of shielded conductor in SGT structures.

Groove 102 is extended downwardly from the surface of semiconductor substrate 101, and is reached in the semiconductor substrate 101 and made a reservation for Depth.In this embodiment, the width of groove 102 is, for example, 0.2 to 10 micron, and depth is, for example, 0.1 to 50 micron.SGT The width of the groove of structure is wider much than the groove of the convention trench power semiconductor of identical conducting level of efficiency, and its The depth of groove is also deeply more many than the groove of convention trench power semiconductor.

Preferably, the sidewall slope of groove 102, for example, relative to vertical trench 102 top at 85 to 89 degree angle, So that the bottom width of groove 102 is less than top width.The angle of groove is more oblique, is conducive to follow-up each dielectric layer, conductive material Filling, caused by reduction blind the problems such as defect.

In step s 102, insulating laminate is sequentially formed on the surface of semiconductor substrate 101, which includes altogether The first insulating layer 122 and second insulating layer 123 of shape, as shown in Figure 3b.

In groove 102, the first insulating layer 122 surrounds second insulating layer 123.First insulating layer 122 and second insulating layer 123 are made of different insulating materials.In this embodiment, the first insulating layer 122 is for example made of silica.Second insulating layer 123 are for example formed by being selected from least one of silicon nitride, nitrogen oxides or polysilicon.Preferably, second insulating layer 123 is by nitrogen SiClx forms.The thickness of first insulating layer 122 is, for example, 500 to 50000 angstroms, the thickness of second insulating layer 123 be, for example, 50 to 5000 angstroms.The thickness of first insulating layer 122 is bigger, then gate leakage capacitance Cgd is smaller.

The technique for being used to form the first insulating layer 122 includes by thermal oxide, chemical vapor deposition (CVD) or high density etc. Ion body chemical vapor phase growing forms oxide layer in the inner wall of groove 102.The side of the oxide layer conformally covering groove 102 Wall and bottom, to still retain a part of inner space of groove 102.

The technique for being used to form second insulating layer 123 includes passing through chemical vapor deposition (CVD) or high-density plasma Chemical vapor deposition forms nitride layer on 122 surface of the first insulating layer.The nitride layer conformally covers the first insulating layer 122 surface, to still retain a part of inner space of groove 102.

In step s 103, it is respectively formed out in 102 upper and lower part of groove of first area 201 and second area 202 Mouth 124 and shielded conductor 104 form shield wiring 131, as shown in Figure 3c in the groove 102 in third region 203.

In this embodiment, shielded conductor 104 and shield wiring 131 are formed using the same conductor layer, for example, respectively by The non-crystalline silicon or polysilicon of doping form.It is used to form technique process deposits polycrystalline such as including using sputtering of conductor layer Silicon so that polysilicon fills the remainder of groove 102.Then, in first area 201 and second area 202, etched conductors Layer and second insulating layer 123 are to remove the part positioned at the outside and top of groove 102, to be formed on the top of groove 102 Opening.

Preferably, the conductor layer for being used to form shielded conductor 104 and shield wiring 131 is made of polysilicon.The polysilicon Deposition velocity be, for example, 1 to 100 angstrom per minute, depositing temperature is, for example, 510 to 650 degrees Celsius, thickness be, for example, 1000 to 100000 angstroms.By controlling the doping concentration of conductor layer, its resistance can be adjusted.In this embodiment, the square electricity of conductor layer It is, for example, less than 20 ohm to hinder Rs.Further, the square resistance Rs of conductor layer is smaller, is formed during subsequent oxidation layer Oxidated layer thickness is bigger compared with silicon.Further, the material selection amorphous of conductor layer, it is easier to form lower square resistance Rs。

In above-mentioned deposition step, one or many depositions may be used and form conductor layer material.In Multiple depositions, The rate of subsequent deposition process is less than previous deposition step, to which deposition rate is gradually reduced.In trench fill process, deposition The slower filling effect of rate is better, the filling of channel bottom packing ratio the top of the groove difficulty, therefore in multiple filling, previously deposited Rate needs to be less than the rate of any primary depositing below.

In the etching step, Etching mask is formed by photoetching and etching, with the first of exposing semiconductor substrate 101 Region 201 and second area 202, and block the third region 203 of semiconductor substrate 101.It, can in above-mentioned etching step To use wet etching.Due to the selectivity of etchant, conductor layer and second insulating layer are removed relative to the first insulating layer 122 123 expose portion.The etching not only removes conductor layer and second insulating layer 123 is located at the part outside groove 102, but also Etch-back conductor layer and second insulating layer 123 are located at the part inside groove 102.After the etching, the conductor layer is in the firstth area The part retained in the groove 102 of domain 201 and second area 202 forms shielded conductor 104.In third region 203, shielding cloth Line 131 includes the first part in the groove 102 in third region 203 and is laterally extended on the surface of semiconductor substrate 101 Second part.Preferably, which includes etching twice, using different etchants, in first time etches, relatively The expose portion of conductor layer is removed in second insulating layer 123, in second etches, relative to the first insulating layer 122 removal the The expose portion of two insulating layers 123.After the etch back, the opening 124 that predetermined depth is formed in groove 102, for example, the depth Degree is to extend downwardly 0.2 to 4 micron from the surface of semiconductor substrate 101.The opening 124 exposes the upper side of groove 102 again Wall.

In step S104, the first insulating layer 122 of etching removal in the groove of first area 201 and second area 202 A part, as shown in Figure 3d.

In the etching step, Etching mask is formed by photoetching and etching, with the first of exposing semiconductor substrate 101 Region 201 and second area 202, and block the third region 203 of semiconductor substrate 101.The etch process is, for example, wet method Etching.Due to the selectivity of etchant, the expose portion of the first insulating layer 122 is removed relative to semiconductor substrate 101.Opening 124 depth extended downwardly from the surface of semiconductor substrate 101 are, for example, 0.5 to 5 micron.The etching removes the first insulating layer 122 are located at the part on 102 top of groove.After the etching, the first insulating layer 122 is located at lower sides and the bottom of groove 102 A part retain so that still by insulating between the lower part and semiconductor substrate 101 of shielded conductor 104 and shield wiring 131 Lamination is isolated from each other.

In step S105, gate-dielectric 105 is formed in the upper portion side wall of groove 102 and the top of shielded conductor 104, As shown in Figure 3 e.

Thermal oxide may be used in the technique for being used to form gate-dielectric 105.The temperature of the thermal oxide be, for example, 950 to 1200 degrees Celsius.The exposure silicon materials of semiconductor substrate 101 and shielded conductor 104 form silica in thermal oxidation process. In step of thermal oxidation, the surface of semiconductor substrate 101 is also exposed in atmosphere.Gate-dielectric 105 is not placed only in groove 102 Upper portion side wall on, and be covered on the surface of semiconductor substrate 101.

Compared with fine and close semiconductor substrate 101, shielded conductor 104 is the amorphous or polycrystalline material of heavy doping, structure More loose, doping concentration is higher.As a result, gate-dielectric 105 is located at the thickness ratio of the second part on 104 surface of shielded conductor The thickness of first part on 101 surface of semiconductor substrate and in groove 102 is big.The first part of gate-dielectric 105 Thickness be, for example, 50 to 5000 angstroms, the thickness of second part is, for example, 60 to 10000 angstroms.

In step s 106, grid conductor 106, Yi Ji is formed in the groove of first area 201 and second area 202 Body area 107 and source region 108 are formed in the region adjacent with groove 102 of semiconductor substrate 101, as illustrated in figure 3f.

The grid conductor 106 is for example made of the non-crystalline silicon or polysilicon that adulterate.It is used to form the technique of grid conductor 106 Such as including using process deposits polysilicons such as sputterings so that polysilicon fills the opening at 104 top of shielded conductor.

The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius, Thickness is, for example, 1000 to 100000 angstroms.By controlling the doping concentration of grid conductor 106, its resistance can be adjusted.In the reality It applies in example, the square resistance Rs of grid conductor 106 is, for example, less than 20 ohm.Further, the square resistance Rs of grid conductor 106 Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, grid conductor 106 Material selection amorphous, it is easier to form lower square resistance Rs.

In above-mentioned deposition step, one or many materials for depositing and forming grid conductor 106 may be used.Multiple When deposition, the rate of subsequent deposition process is less than previous deposition step, to which deposition rate is gradually reduced.In trench fill process In, the slower filling effect of deposition rate is better, the filling of channel bottom packing ratio the top of the groove difficulty, therefore in multiple filling, preceding The rate of face deposition needs to be less than the rate of any primary depositing below.

The polysilicon includes the first part in the groove of first area 201 and second area 202, and is partly being led The second part being laterally extended on the surface of body substrate 101.

Then, in first area 201 and second area 202, etching removal polysilicon is located at 101 surface of semiconductor substrate The second part that top is laterally extended so that polysilicon is only filled in the first area of semiconductor substrate 101 and second area The opening 124 on 102 top of groove, to form grid conductor 106.In third region 203, it is located at 131 surface of shield wiring On polysilicon can completely remove.Further, the second part of shield wiring 131 may also be etched partly and thickness Reduce.However, the second part of shield wiring 131 will be used to reroute, therefore, shielding can be retained by controlling etching period The second part of wiring 131.

Then, the areas PXing Ti 107 are formed in semiconductor substrate 101, and the source region of N-type is formed in body area 107. The technique for being used to form body area 107 and source region 108 is, for example, multiple ion implanting.By selecting suitable dopant to form difference Then the doped region of type carries out thermal annealing with activator impurity.In ion implanting, using grid conductor 106 and shield wiring 131 are used as hard mask, the lateral position in body area 107 and source region 108 can be limited, so as to save photoresist mask. The angle of the ion implanting is, for example, zero degree, i.e., relative to the surface vertical injection of semiconductor substrate 101.By controlling ion The energy of injection can limit the injection depth of body area 107 and source region 108, to limit upright position.

When forming body area 107, the dopant used can also be first to note B11 to note BF2 again, inject energy for B11 or BF2 Amount is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.Forming source region 108 When, for the dopant used for P+ or AS+, Implantation Energy is 60~150Kev, and implantation dosage is 1E14~1E16, thermal annealing temperatures It is 800 to 1100 degrees Celsius.

In this step, SGT structures are formed in the groove 102 of first area 201 and second area 202, including are located at Shielded conductor 104 in groove and grid conductor 106.Grid conductor 106 includes the first part being located in groove 102, and The second part extended above semiconductor substrate 101.The first part of grid conductor 106 is formed in 104 both sides of shielded conductor Opening 124 in, be clipped in the middle to shielded conductor 104.By second insulating layer between shielded conductor 104 and grid conductor 106 123 are isolated from each other.The lower part of shielded conductor 104 extends to the lower part of groove 102, folded by insulating between semiconductor substrate 101 Layer is being isolated each other, which includes the first insulating layer 122 and second insulating layer 123.Grid conductor 106 and body area 107 It is adjacent with source region 108, and be isolated from each other by gate-dielectric 105.

In step s 107, the dielectric layer 109 between the surface deposits of semiconductor structure, as shown in figure 3g.

Interlayer dielectric layer 109 covers the first area of semiconductor substrate 101 and second area interlayer dielectric layer 109 can be by It is formed selected from least one of silica, silicon nitride, silicon oxynitride, and can be single layer or laminated construction.In the reality It applies in example, interlayer dielectric layer 109 for example can be the boron-phosphorosilicate glass (BPSG) that thickness is 2000 to 15000 angstroms.

In step S108, is formed in interlayer dielectric layer 109 and reach source region 108, grid conductor 106 and shield wiring 131 multiple contact holes 125, and contact zone 110 is respectively formed in the bottom of multiple contact holes 125 by ion implanting, such as Shown in Fig. 3 h.

The technique for being used to form contact hole 125 is, for example, dry etching.The sidewall slope of contact hole 125, such as relative to The angle that the top of vertical trench 102 is spent at 85 to 89.9 so that the bottom width of contact hole 125 is less than top width.Contact The angle in hole 125 is more oblique, the problems such as being conducive to the filling of subsequent conductive material, reduce defect caused by blind.

In the first area of semiconductor substrate 101 201, first group of contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109 and gate-dielectric 105, extend to the predetermined depth in shield wiring 131, and second group of contact hole is worn successively Cross the predetermined depth in interlayer dielectric layer 109, gate-dielectric 105, the arrival body of source region 108 area 107.The predetermined depth is, for example, 0.1 to 1 micron.

In the second area 202 of semiconductor substrate 101, second group of contact hole in multiple contact holes 125 sequentially passes through Interlayer dielectric layer 109 extends to the predetermined depth in grid conductor 106.

In the third region 203 of semiconductor substrate 101, the third group contact hole in multiple contact holes 125 passes through interlayer Dielectric layer 109 extends to the predetermined depth in shield wiring 131.

In ion implanting, using interlayer dielectric layer as hard mask, the lateral position of contact zone 110 is limited, so as to To save photoresist mask.The dopant that the ion implanting uses can also be first to note B11 to note BF2 again for B11 or BF2, Implantation Energy is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.In ion After injection, thermal annealing can be carried out to activate dopant.

In step S109, source electrode 111, gate electrode 112 and bucking electrode 113 are formed, as shown in figure 3i.

The step is for example including deposited metal layer and patterning.The metal layer for example by be selected from Ti, TiN, TiSi, W, One kind in AL, AlSi, AlSiCu, Cu, Ni or its composition of alloy.By etching by metal layer pattern be melted into source electrode 111, Gate electrode 112 and bucking electrode 113.As shown, source electrode 111, gate electrode 112 and bucking electrode 113 each other every From.

In the first area of semiconductor substrate 101 201, source electrode 111 is via in the multiple contact hole 125 One group of contact hole reaches source region 108.

In the second area 202 of semiconductor substrate 101, gate electrode 112 is via in the multiple contact hole 125 Two groups of contact holes reach grid conductor 106.

In the third region 203 of semiconductor substrate 101, bucking electrode 113 is via in the multiple contact hole 125 Three groups of contact holes reach shield wiring 131.

After step S109, the metallization of power semiconductor is had been carried out.Further, according to the needs of product, Passivation layer protection can be increased, complete the processing of power semiconductor Facad structure.By being thinned, carrying on the back a systems such as gold, scribing Row postchannel process completes the final realization of device.

Although should be noted that in above-mentioned sectional view, shielded conductor 104 and shield wiring 131 in different grooves that This isolation, grid conductor 106 are isolated from each other, however, in actual power semiconductor, it is above-mentioned from planar structure Shielded conductor 104 and shield wiring 131 in different grooves can be connected to each other, and grid conductor 106 can also be connected to each other. In a kind of embodiment, which is, for example, that the grid conductor 106 in different grooves 102 is integrally formed by single conductive layer, And shielded conductor 104 in different groove 102 and shield wiring 131 are integrally formed by single conductive layer.In the implementation of replacement Example in, the connection type be, for example, using public bucking electrode 113 by different grooves 102 shielded conductor 104 and shielding Wiring 131 is connected to each other, and is connected the grid conductor 106 in different grooves 102 each other using public gate electrode 112 It connects.

In this embodiment, shield wiring 131 includes not only the first part of filling groove 102, but also includes from groove 102 second parts being laterally extended on 101 surface of semiconductor substrate.The second part is as wiring layer.This mainly considers work( The groove width of rate semiconductor devices is limited.Shielded conductor 104 in the trench is formed after contact hole, semiconductor substrate 101 First area 201 and second area 102 in contact hole it is intensive.It is led to improve source region 108, shielded conductor 104 and grid Electric isolution between body 106, using the second part of shield wiring 131 as wiring layer so that the multiple contact hole 125 In, for source region 108, shield wiring 104 and grid conductor 106 contact hole can away from each other, to reduce technology difficulty, The reliability of power semiconductor is provided.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including element.

For example above according to the embodiments of the present invention, there is no all details of detailed descriptionthe for these embodiments, also not Limit the specific embodiment that the utility model is only.Obviously, as described above, can make many modifications and variations.This explanation These embodiments are chosen and specifically described to book, is in order to preferably explain the principles of the present invention and practical application, to make Skilled artisan can utilize the utility model and modification on the basis of the utility model to use well.This Utility model is limited only by the claims and their full scope and equivalents.

Claims (8)

1. a kind of power semiconductor, including：

Multiple grooves in semiconductor substrate, the semiconductor substrate are the first doping type, and the multiple groove includes The first of first area to the third region of the semiconductor substrate is located to third groove；

Division grid structure in the first groove and the second groove, the division grid structure include shielded conductor, Grid conductor and it is clipped in second insulating layer between the two；

At least part is located at the shield wiring in the third groove；

Positioned at the areas the semiconductor substrate Zhong Ti, the body area is the second doping type adjacent to the first groove top, Second doping type is opposite with first doping type；

Source region in the body area, the source region are first doping type；And

Source electrode, gate electrode and the shielding being electrically connected with the source region, the grid conductor and the shield wiring Electrode,

Wherein, the shield wiring is electrically connected with the shielded conductor, and the shield wiring includes filling the third ditch The first part of slot and the second part being laterally extended in the semiconductor substrate surface, the second part are used for weight cloth Line.

2. power semiconductor according to claim 1, wherein the institute in the first groove and the second groove Stating division grid structure includes：

Positioned at the insulating laminate of the first groove and the second groove lower sides and bottom, the insulating laminate includes the One insulating layer and second insulating layer, first insulating layer surround the second insulating layer；

Positioned at the shielded conductor of the first groove and the second groove lower part；And

Positioned at the grid conductor of the first groove and the first groove top,

Wherein, it is isolated from each other by gate-dielectric between the grid conductor and the shielded conductor, the grid conductor and institute It is isolated from each other by the gate-dielectric between the areas Shu Ti, by the insulation between the shielded conductor and the semiconductor substrate Lamination is isolated from each other.

3. power semiconductor according to claim 2, wherein the source electrode is located in the first area, The gate electrode is located in the second area, and the bucking electrode is located in the third region, the first area, institute It states second area and the third region is separated from each other.

4. power semiconductor according to claim 2, wherein first insulating layer is made of silica, described Second insulating layer is formed by being selected from least one of silicon nitride, nitrogen oxides or polysilicon.

5. power semiconductor according to claim 2, wherein the thickness of first insulating layer is 500 to 50000 In the range of angstrom, the thickness of the second insulating layer is in the range of 50 to 5000 angstroms.

6. power semiconductor according to claim 2, wherein first doping type is one in N-type and p-type Kind, second doping type is the another kind in N-type and p-type.

7. power semiconductor according to claim 2, wherein the sidewall slope of the multiple groove so that described The top width of multiple grooves is more than the bottom width of the multiple groove.

8. power semiconductor according to claim 2, wherein the power semiconductor is selected from CMOS devices One kind in part, BCD devices, mosfet transistor, IGBT and Schottky diode.