CN105762182A - IGBT device with high latching resisting capability - Google Patents
IGBT device with high latching resisting capability Download PDFInfo
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- CN105762182A CN105762182A CN201610298661.6A CN201610298661A CN105762182A CN 105762182 A CN105762182 A CN 105762182A CN 201610298661 A CN201610298661 A CN 201610298661A CN 105762182 A CN105762182 A CN 105762182A
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- 239000002184 metal Substances 0.000 claims abstract description 54
- 230000001413 cellular effect Effects 0.000 claims description 103
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 13
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical group NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 1
- -1 certainly Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Abstract
The invention relates to an IGBT device with a high latching resisting capability.Each active cell of the IGBT device comprises a second conduction type base region and a first conduction type source electrode region.Barrier rings are arranged in the second conduction type base regions.On the section of the IGBT device, each barrier ring comprises a first conduction type buried layer and an insulating dielectric cylinder, wherein the upper end of the insulating dielectric cylinder makes contact with source electrode metal, the end, located under the corresponding first conduction type source electrode region, of the first conduction type buried layer makes contact with the insulating dielectric cylinder, the other end of the first conduction type buried layer makes contact with the side wall of a conducting channel, the length of the part, under the corresponding first conduction type source electrode region, of the first conduction type buried layer is not smaller than the length of the part, in the corresponding second conduction type base region, of the corresponding first conduction type source electrode region, and the first conduction type buried layer is insulated from the source electrode metal.The IGBT device is compact in structure, compatible with the existing process, safe, reliable and capable of effectively reducing the latching risk and providing a basis for reducing the on-state voltage drop.
Description
Technical field
The present invention relates to a kind of semiconductor device, especially a kind of IGBT device with high resistance breech lock ability, belong to the technical field of IGBT device.
Background technology
Parasitic IGCT, i.e. NPNP structure is there is in IGBT device.In the process of proper device operation, it is undesirable to open the IGCT of described parasitism.If described parasitic thyristor is in opening state, then the grid of IGBT device will lose the control to electric current.But, in IGBT work process, if it is too big to flow through the hole current below source electrode, so the PN junction of source electrode and base will positively biased, namely source electrode start to base inject electronics, base start to source electrode inject hole, now parasitic turn on thyristors, namely IGBT device is in latch mode.
The electric current density that present IGBT pursues is increasing, and when the big current work of device, device has the risk that breech lock occurs.There is the risk of breech lock in order to reduce IGBT device in the course of the work, be to increase the doping content of base below source electrode on the one hand, reduce the resistance of this subregion, but this threshold voltage being easy to affect device, thus giving the design of device and manufacturing increase difficulty；Being the doping content reducing device backside collector on the other hand, thus reducing the composition of hole current in On current, but this can increase the conduction voltage drop of device, and especially to the high pressure IGBT device with wide N-type base, conduction voltage drop can be very big.And when the doping of the device back side is too low, the short-circuit robustness of device can reduce.
As shown in Figure 1, structure for existing groove-shaped IGBT device, for N-type IGBT device, described IGBT device includes N-type base 7, and the top in N-type base 7 is provided with P type base 6, is provided with cellular groove 13 in P type base 6, the bottom land of cellular groove 13 is positioned at N-type base 7, being arranged over N+ source area 4 at cellular groove 13 outer wall side, sidewall and diapire at cellular groove 13 are coated with insulated gate oxide layer 14, and are filled with conductive polycrystalline silicon 3 in cellular groove 13.It is provided with source metal 1 in the front of N-type base 7, described source metal 1 is dielectrically separated from conductive polycrystalline silicon 3 by the insulating medium layer 2 on N-type base 7, source metal 1 and the P type heavily doped region 5 in N+ source area 4 and P type base 6, described P type heavily doped region 5 also extends to the lower section of N+ source area 4 in P type base 6, but P type heavily doped region 5 does not contact with the outer wall of cellular groove 13.Be provided with collector structure at the back side of N-type base 7, described collector structure includes P type collecting zone 9 and the collector electrode metal 10 with described P type collecting zone 9 Ohmic contact.
During specific works, P type heavily doped region 5 is positioned at the region part below N+ source area 4 can form anti-bolt lock structure 11, in order to make device have high anti-breech lock performance, forming the P type doping content in anti-bolt lock structure 11 must be very high, simultaneously highly doped must also as close as the sidewall of cellular groove 13, and directly affect the threshold voltage of IGBT device owing to the P type of cellular groove 13 sidewall adulterates, therefore described anti-bolt lock structure 11 brings very big difficulty to IGBT device design and processes.
On the other hand, in order to make IGBT device that breech lock in use not occur, the doping content of P type collecting zone 9 is generally relatively low, its junction depth is general, and also ratio is shallower, this makes N-type base 7 injected holes fewer, and conductivity modulation effect is not notable, can cause that IGBT device conduction voltage drop is relatively larger.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of IGBT device with high resistance breech lock ability, its compact conformation, can effectively reduce the risk that breech lock occurs, provide basis for reducing conduction voltage drop, mutually compatible with existing technique, safe and reliable.
According to technical scheme provided by the invention, described in there is the IGBT device of high resistance breech lock ability, including the semiconductor substrate with two opposing main faces, two opposing main faces of semiconductor substrate include the first interarea and second interarea corresponding with the first interarea；The first conduction type base region is included between the first interarea of semiconductor substrate and the second interarea；Some regular array and the active cellular of the distribution that is parallel to each other are set in the first conduction type base region of semiconductor substrate, described active cellular includes the second conduction type base region being positioned at the first conduction type base region internal upper part and the first conduction type source area being positioned at described second conduction type base region, described second conduction type base region, the first conduction type source area and the source metal Ohmic contact on semiconductor substrate the first interarea；
The blocker ring being positioned at the first conduction type source area outer ring is set in described second conduction type base region；On the cross section of described IGBT device, described blocker ring includes the first conduction type buried regions and dielectric post, described dielectric post is positioned at the outside of the first conduction type source area, the upper end of dielectric post contacts with source metal, one end that first conduction type buried regions is positioned at immediately below the first conduction type source area contacts with dielectric post, the other end of the first conduction type buried regions and conducting channel sidewall contact, first conduction type buried regions length immediately below the first conduction type source area is not less than first conduction type source area length in the second conduction type base region, first conduction type buried regions and source metal mutually insulated, and first conduction type buried regions and the first conduction type source electrode interval, and first between conduction type buried regions and the first conduction type base region each through the second conduction type base region interval.
Second interarea of semiconductor substrate is provided with collector structure, described collector structure includes collector electrode metal and the collector layer with described collector electrode metal Ohmic contact, collector layer is positioned between the second interarea of collector electrode metal and semiconductor substrate, and described collector layer includes the second conduction type collecting zone.
It is additionally provided with the first conductive type buffer layer between the second interarea of described collector layer and semiconductor substrate.
Described collector layer also includes the some first conduction type collecting zones being positioned at the second conduction type collecting zone, the first conduction type collecting zone and collector electrode metal Ohmic contact.
Described active cellular is plane or channel form.
nullWhen described active cellular adopts planar structure，On the cross section of described IGBT device，Described flat surface active cellular includes two adjacent the second conduction type base region and is positioned at the first conduction type source area of described second conduction type base region，The second adjacent conduction type base region is by the first conduction type base region separately，It is provided with conductive polycrystalline silicon and insulating medium layer in the surface of the first conduction type base region of adjacent second conductive type base, interval，Conductive polycrystalline silicon is dielectrically separated from by the first interarea and the source metal of insulating medium layer and semiconductor substrate，And the first conduction type source area of the two ends of conductive polycrystalline silicon and lower section overlaps mutually，The first conduction type buried regions and dielectric post it is respectively provided with in each second conduction type base region，It is positioned at the one end immediately below the first conduction type source area to contact with dielectric post，The other end of first conduction type buried regions contacts with the insulating medium layer on semiconductor substrate the first interarea，Described conductive polycrystalline silicon and gate metal Ohmic contact.
When described active cellular adopts channel form structure, on the cross section of described IGBT device, described active cellular includes the cellular groove being positioned at the second conduction type base region, the bottom land of described cellular groove is positioned at the first conduction type base region below the second conduction type base region, the inwall of cellular groove and diapire are coated with insulated gate oxide layer, and it is filled with conductive polycrystalline silicon in the cellular groove being coated with insulated gate oxide layer, the notch of cellular groove is covered by the insulating medium layer on semiconductor substrate the first interarea, conductive polycrystalline silicon in cellular groove is dielectrically separated from by insulating medium layer and source metal；First conduction type source area is positioned at above cellular groove outer wall side, the first conduction type source area, the first conduction type buried regions the other end contact with cellular groove outer wall, the conductive polycrystalline silicon in cellular groove and gate metal Ohmic contact.
The material of described semiconductor substrate includes silicon, and described dielectric post includes silica column, and the height of dielectric post is less than the thickness of the second conduction type base region.
The shape of described active cellular has a bar shape, square or circular.
The second conduction type heavily doped region for forming anti-bolt lock structure it is provided with in described first conduction type blocker ring, described second conduction type heavily doped region is positioned at outside and the lower section of the first conduction type source area, second conduction type heavily doped region and the first conduction type source region contact, and the length that the second conduction type heavily doped region is below the first conduction type source area is less than the length of the first conduction type source area.
In both described " the first conduction type " and " the second conduction type ", for N-type IGBT device, the first conduction type refers to N-type, and the second conduction type is P type；For P type IGBT device, the type of the first conduction type and the second conduction type indication and N-type IGBT device contrast.
Advantages of the present invention:
1, the first conduction type buried regions is set in the second conduction type base region, first conduction type buried regions is positioned at the length more than the first conduction type source area of the zone length immediately below the first conduction type source area, one end of first conduction type buried regions contacts with dielectric post, the other end and active cellular conducting channel sidewall contact；By the first conduction type buried regions by the first conduction type source area be carried out below surround, effectively electronic current and hole current are carried out discrete opening, it is substantially reduced the lower section even preventing hole current from flowing through the first conduction type source area, electronic current is only allowed to flow to the first conduction type source area by raceway groove, the anti-breech lock ability of IGBT device can be improved, basis is provided for reducing conduction voltage drop, mutually compatible with existing technique, safe and reliable.
2, when the first conduction type buried regions is formed by double; two thermal diffusions, the horizontal proliferation of the first conduction type buried regions can be limited by dielectric post, thus reducing the size of IGBT device cellular；When the first conduction type buried regions is formed by other technique, it is possible to prevent the concentration of the first conduction type buried regions fringe field, raising reliability, and the doping content of the first conduction type buried regions can be improved, improve the anti-breech lock ability of device further.
Accompanying drawing explanation
Fig. 1 is the sectional view of existing groove-shaped IGBT device.
Fig. 2 is the sectional view of groove PT type IGBT device of the present invention.
Fig. 3 is the sectional view of plane PT type IGBT device of the present invention.
Fig. 4 is the sectional view of groove NPT type IGBT device of the present invention.
Fig. 5 is the sectional view of groove PT type RCIGBT device of the present invention.
Fig. 6 is the sectional view of groove NPT type RCIGBT device of the present invention.
Fig. 7 is the sectional view of plane NTP type IGBT device of the present invention.
Fig. 8 is the sectional view of plane PT type RCIGBT device of the present invention.
Fig. 9 is the sectional view of plane NPT type RCIGBT device of the present invention.
Figure 10 is the structural representation that the active cellular of the present invention is elongated.
Figure 11 is the structural representation that the active cellular of the present invention is square.
Figure 12 is the present invention rounded structural representation of active cellular.
Description of reference numerals: 1-source metal, 2-insulating medium layer, 3-conductive polycrystalline silicon, 4-N+ source area, 5-P type heavily doped region, 6-P type base, 7-N type base, 8-N type cushion, 9-P type collecting zone, 10-collector electrode metal, the anti-bolt lock structure of 11-, 12-N type buried regions, 13-cellular groove, 14-insulated gate oxide layer, 15-N type collecting zone and the active cellular of 16-and 17-dielectric post.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the invention will be further described.
In order to enable effectively to reduce the risk that breech lock occurs, basis is provided for reducing conduction voltage drop, for N-type IGBT device, the present invention includes the semiconductor substrate with two opposing main faces, and two opposing main faces of semiconductor substrate include the first interarea and second interarea corresponding with the first interarea；N-type base 7 is included between the first interarea of semiconductor substrate and the second interarea；Some regular array and the active cellular 16 of the distribution that is parallel to each other are set in the N-type base 7 of semiconductor substrate, described active cellular 16 includes the P type base 6 being positioned at N-type base 7 internal upper part and the N+ source area 4 being positioned at described P type base 6, described P type base 4, N+ source area 4 and source metal 1 Ohmic contact on semiconductor substrate the first interarea；
The blocker ring being positioned at N+ source area 4 outer ring is set in described P type base 6；On the cross section of described IGBT device, described blocker ring includes n type buried layer 12 and dielectric post 17, described dielectric post 17 is positioned at the outside of N+ source area 4, the upper end of dielectric post 17 contacts with source metal 1, one end that n type buried layer 12 is positioned at immediately below N+ source area 4 contacts with dielectric post 17, the other end of n type buried layer 12 contacts with the sidewall of active cellular 16 conducting channel, and the length that n type buried layer 12 is immediately below N+ source area 4 is not less than the N+ source area 4 length in P type base 6, n type buried layer 12 and source metal 1 mutually insulated, and between n type buried layer 12 and N source area 4, and each through interval, P type base 6 between n type buried layer 12 and N-type base 7.
Specifically, the material of semiconductor substrate includes silicon, certainly, semiconductor substrate can also adopt the semi-conducting material that other are conventional, and for N-type IGBT device, the conduction type of semiconductor substrate is N-type, usually, the front of semiconductor substrate forms the first interarea, and the back side of semiconductor substrate forms the second interarea, and the first interarea and the second interarea are corresponding.P type base 6 is positioned at the top of N-type base 7, and N+ source area 4 is positioned at type base, P type base 6, P 6 and source metal 1 Ohmic contact.The shape of described active cellular 16 has a bar shape, square or circular, respectively as shown in Figure 10, Figure 11 and Figure 12.
Blocker ring is positioned at P type base 6, blocker ring is in the outer ring of N+ source area 4, namely N+ source area 4 is positioned at the encirclement ring that blocker ring is formed, and N+ source area 4 is positioned at the top of P type base 6, the top of N+ source area 4 and the direct Ohmic contact of source metal 1 on semiconductor substrate the first interarea.Being formed by blocker ring to surround and surround ring below N+ source area 4, one end of blocker ring and source metal 1 are dielectrically separated from, the other end and active cellular 16 conducting channel sidewall contact.Blocker ring in P type base 6 is equivalent to a hole barrier, therefore, can effectively open discrete to electronic current and hole current, the lower section even preventing hole current through N+ source area 4 can be reduced significantly, and only allow electronic current to flow to N+ source area 4 by raceway groove, such that it is able to improve the anti-breech lock ability of IGBT device.
When being embodied as, on the cross section of described IGBT device, blocker ring includes dielectric post 17 and n type buried layer 12, dielectric post 17 is in vertical distribution in P type base 6, n type buried layer 12 and N+ source area 4 are respectively positioned on the same side of dielectric post 17, dielectric post 17 can adopt the forms such as silica column, and the upper end of dielectric post 17 directly contacts with source metal 1, and the dielectric post 17 height in P type base 6 is less than the degree of depth of P type base 6.N type buried layer 12 includes being positioned at the region immediately below N+ source area 4, and one end of the n type buried layer 12 immediately below N+ source area 4 contacts with dielectric post 17, the other end of described n type buried layer 12 contacts with the sidewall of the conducting channel of active cellular 16, namely the other end of n type buried layer 12 may be located at the underface of N+ source area 4 or is positioned at the outside of N+ source area 4, the position of n type buried layer 12 other end is relevant with the concrete form of active cellular 16, it is specially known by those skilled in the art, no longer describes in detail herein.Dielectric post 17 and N+ source area 4 noncontact.N type buried layer 12 can be dielectrically separated from source metal 1 by dielectric post 17.
In the embodiment of the present invention, when n type buried layer 12 is formed by double; two thermal diffusions, the horizontal proliferation of n type buried layer 12 can be limited by dielectric post 17, it is thus possible to reduce the size of IGBT device cellular；When n type buried layer 12 is formed by other techniques (such as extension+ion implanting), by etching a groove and the method filling dielectric, it is possible to prevent the concentration of n type buried layer 12 fringe field, improve reliability, and the doping content of n type buried layer 12 can be improved, thus improving the anti-breech lock ability of device.
In the specific implementation, described active cellular 16, in plane or channel form, specifically can be determined as required, active cellular 16 adopts plane and channel form form illustrate below.
nullWhen described active cellular 16 adopts planar structure，On the cross section of described IGBT device，Described flat surface active cellular includes two adjacent P type bases 6 and is positioned at the N+ source area 4 of described P type base 6，Adjacent P type base 6 is by N-type base 7 separately，At interval, the surface of the N-type base 7 of adjacent P type base 6 is provided with conductive polycrystalline silicon 3 and insulating medium layer 2，Conductive polycrystalline silicon 3 is dielectrically separated from by the first interarea and the source metal 1 of insulating medium layer 2 and semiconductor substrate，And the N+ source area 4 of the two ends of conductive polycrystalline silicon 3 and lower section overlaps mutually，It is respectively provided with n type buried layer 12 and dielectric post 17 in each P type base 6，One end that n type buried layer 12 is positioned at immediately below N+ source area 4 contacts with dielectric post 17，The other end of n type buried layer 12 contacts with the insulating medium layer 2 on semiconductor substrate the first interarea，Described conductive polycrystalline silicon 3 and gate metal Ohmic contact.
In the embodiment of the present invention, when active cellular 16 adopts plane, on the cross section of IGBT device, P type base 6 in discontinuous distribution, passes through N-type base 7 spaced in N-type base 7 between adjacent P type base 6；For an active cellular 16, in two adjacent P type base 6, all there is the doping content doping content more than N-type base 7 of N+ source area 4, N+ source area 4.It is respectively provided with n type buried layer 12 and dielectric post 17 in each P type base 6, one end that n type buried layer 12 is positioned at immediately below N+ source area 4 contacts with dielectric post 17, the other end of n type buried layer 12 contacts with the insulating medium layer 2 on semiconductor substrate the first interarea, namely n type buried layer 12 is except the region existed immediately below N+ source area 4, there is also the part paralleled with dielectric post 17, described and the parallel part of dielectric post 17 upper end contacts with insulating medium layer 2, the lower section of the N+ source area 4 in each P type base 6 and exterior lateral area effectively can be surrounded thereby through dielectric post 17 and n type buried layer 12.
Conductive polycrystalline silicon 3 is surrounded by cellular insulating medium layer 2, the two ends of conductive polycrystalline silicon 3 overlap with N+ source area 4 part, the part that conductive polycrystalline silicon 3 and N+ source area 4 overlap mutually is by 2 intervals of cellular insulating medium layer, remaining part of N+ source area 4 and source metal 1 Ohmic contact.In order to be able to be formed the grid of IGBT device, with gate metal Ohmic contact after all of conductive polycrystalline silicon 3 is drawn, by conductive polycrystalline silicon 3, the concrete form drawn with gate metal Ohmic contact can adopt the form that the art is conventional, it is specially known by those skilled in the art, repeats no more herein.
When active cellular 16 is flat surface active cellular, the collector structure difference at the flat surface active cellular back side can obtain PT type IGBT or NPT type IGBT, Fig. 3 are plane PT type IGBT device, and Fig. 7 is plane NPT type IGBT device.For plane NPT type IGBT device, described collector structure includes collector electrode metal 10 and P type collecting zone 9, the P type collecting zone 9 with described collector electrode metal 10 Ohmic contact is positioned between the second interarea of collector electrode metal 10 and semiconductor substrate.For plane PT type IGBT device, being additionally provided with N-type cushion 8 between the second interarea of described P type collecting zone 9 and semiconductor substrate, described N-type cushion 8 adjoins N-type base 7 and P type collecting zone 9.
In addition, difference according to collector layer, RCIGBT(Reverseconductinginsulatedgatebipolartransistor can also be formed) device, Fig. 8 is plane PT type RCIGBT device, some N-type collecting zones 15 it are additionally provided with in P type collecting zone 9, collector layer is formed, to obtain plane PT type RCIGBT device by P type collecting zone 9 and N-type collecting zone 15.In Fig. 9, in P type collecting zone 9, it also is provided with some N-type collecting zones 15, by coordinating of P type collecting zone 9 and N-type collecting zone 15, thus obtaining plane NPT type RCIGBT device.During by the IGBT device being differently formed of collector structure, its work process is known by those skilled in the art, repeats no more herein.
When described active cellular 16 adopts channel form structure, the active cellular of described groove includes the cellular groove 13 being positioned at P type base 6, the bottom land of described cellular groove 13 is positioned at the N-type base 7 below P type base 6, the inwall of cellular groove 13 and diapire are coated with insulated gate oxide layer 14, and in the cellular groove 13 being coated with insulated gate oxide layer 14, it is filled with conductive polycrystalline silicon 3,13 notches of cellular groove are covered by the insulating medium layer 2 on semiconductor substrate the first interarea, and the conductive polycrystalline silicon 3 in cellular groove 13 is dielectrically separated from by insulating medium layer 2 and source metal 1；N+ source area 4 is positioned at above cellular groove 13 outer wall side, and N+ source area 4, N-type blocker ring 12 contact with cellular groove 13 outer wall, conductive polycrystalline silicon in cellular groove 13 3 and gate metal Ohmic contact.
When being embodied as, the notch of cellular groove 13 is positioned on the first interarea of semiconductor substrate, and is extended vertically downward by the first interarea of semiconductor substrate, and cellular groove 13 is through P type base 6, and the bottom land of cellular groove 13 is positioned at the N-type base 7 below P type base 6.By techniques such as thermal oxides, sidewall and diapire growth at cellular groove 13 have insulated gate oxide layer 14, insulated gate oxide layer 14 can be silicon dioxide layer, filled conductive polysilicon 3 in the cellular groove 13 of insulated gate oxide layer 14 is had in growth, conductive polycrystalline silicon 3 fills up cellular groove 13, the insulating medium layer 2 of cellular groove 13 notch blocks cellular conductive polycrystalline silicon 3, so that conductive polycrystalline silicon 3 and source metal 1 are dielectrically separated from.The doping content of N+ source area 4 is more than the doping content of N-type base 7, the degree of depth of N+ source area 4 is less than the degree of depth of P type base 5, N+ source area 4 contacts with the lateral wall of cellular groove 13, and with source metal 1 Ohmic contact such that it is able to form the source terminal of required IGBT device.
On the cross section of IGBT device, dielectric post 17 and cellular groove 13 are parallel to each other, the height of dielectric post 17 is less than the degree of depth of cellular groove 13, dielectric post 17 and n type buried layer 12 are symmetrically distributed in the both sides of cellular groove 13, now, n type buried layer 12 exists only in immediately below N+ source area 4, the two ends of n type buried layer 12 contact with the outer wall of dielectric post 17 and cellular groove 13 respectively, it is thus possible to realize the effective encirclement to N+ source area 4, realize electronic current and the effectively discrete of hole current are opened, it is substantially reduced the lower section even preventing hole current from flowing through N+ source area 4.In cellular groove 13, conductive polycrystalline silicon 3 coordinates known by those skilled in the art with the connection between gate metal, repeats no more herein.
When active cellular 16 is the active cellular of groove, the collector structure difference at the active cellular back side of groove can obtain PT type IGBT or NPT type IGBT, Fig. 2 are groove PT type IGBT device, and Fig. 4 is groove NPT type IGBT device.For groove NPT type IGBT device, described collector structure includes collector electrode metal 10 and P type collecting zone 9, the P type collecting zone 9 with described collector electrode metal 10 Ohmic contact is positioned between the second interarea of collector electrode metal 10 and semiconductor substrate.For groove PT type IGBT device, being additionally provided with N-type cushion 8 between the second interarea of described P type collecting zone 9 and semiconductor substrate, described N-type cushion 8 adjoins N-type base 7 and P type collecting zone 9.
In addition, difference according to collector layer, RCIGBT(Reverseconductinginsulatedgatebipolartransistor can also be formed) device, Fig. 5 is groove PT type RCIGBT device, some N-type collecting zones 15 it are additionally provided with in P type collecting zone 9, collector layer is formed, to obtain groove PT type RCIGBT device by P type collecting zone 9 and N-type collecting zone 15.In Fig. 6, in P type collecting zone 9, it also is provided with some N-type collecting zones 15, by coordinating of P type collecting zone 9 and N-type collecting zone 15, thus obtaining groove NPT type RCIGBT device.During by the IGBT device being differently formed of collector structure, its work process is known by those skilled in the art, repeats no more herein.
Further, the P type heavily doped region 5 for forming anti-bolt lock structure 11 it is provided with in described N-type blocker ring 12, described P type heavily doped region 5 is positioned at outside and the lower section of N+ source area 4, P type heavily doped region 5 contacts with N+ source area 4, and the length that P type heavily doped region 5 is below N+ source area 4 is less than the length of N+ source area.
In the embodiment of the present invention, no matter active cellular 16 adopts flat surface active cellular or the active cellular of groove, all can arrange existing anti-bolt lock structure 11 in active cellular 16；Described anti-bolt lock structure 11 includes the P type heavily doped region 5 coordinated with N+ source area 4, and the doping content of described P type heavily doped region 5 is more than the doping content of P type base 6.P type heavily doped region 5 is positioned at P type base 6, P type heavily doped region 5 and is positioned at the length less than N+ source area 4 of the length below N+ source area 4, and namely when active cellular 16 is the active cellular of groove, P type heavily doped region 5 does not contact with the outer wall of cellular groove 13.It is all identical with existing that P type heavily doped region 5 and N+ source area 4 cooperatively form the concrete form of anti-bolt lock structure 11 etc., repeats no more herein.
The present invention arranges n type buried layer 12 in P type base 6, n type buried layer 12 is positioned at the length more than N+ source area 4 of the zone length immediately below N+ source area 4, namely it is P type base 6 between n type buried layer 12 and N+ source area 4 and between n type buried layer 12 and N-type base 7, one end of n type buried layer 12 contacts with dielectric post 17, the conducting channel sidewall contact of the other end of n type buried layer 12 and active cellular 16；By n type buried layer 12 by N+ source area 4 be carried out below surround, effectively electronic current and hole current are carried out discrete opening, it is substantially reduced the lower section even preventing hole current from flowing through N+ source area 4, electronic current is only allowed to flow to N+ source area 4 by raceway groove, the anti-breech lock ability of IGBT device can be improved, basis is provided for reducing conduction voltage drop, mutually compatible with existing technique, safe and reliable.
Claims (10)
1. having an IGBT device for high resistance breech lock ability, including the semiconductor substrate with two opposing main faces, two opposing main faces of semiconductor substrate include the first interarea and second interarea corresponding with the first interarea；The first conduction type base region is included between the first interarea of semiconductor substrate and the second interarea；Some regular array and the active cellular of the distribution that is parallel to each other are set in the first conduction type base region of semiconductor substrate, described active cellular includes the second conduction type base region being positioned at the first conduction type base region internal upper part and the first conduction type source area being positioned at described second conduction type base region, described second conduction type base region, the first conduction type source area and the source metal Ohmic contact on semiconductor substrate the first interarea；It is characterized in that:
The blocker ring being positioned at the first conduction type source area outer ring is set in described second conduction type base region；On the cross section of described IGBT device, described blocker ring includes the first conduction type buried regions and dielectric post, described dielectric post is positioned at the outside of the first conduction type source area, the upper end of dielectric post contacts with source metal, one end that first conduction type buried regions is positioned at immediately below the first conduction type source area contacts with dielectric post, the other end of the first conduction type buried regions and conducting channel sidewall contact, and first conduction type buried regions length immediately below the first conduction type source area be not less than first conduction type source area length in the second conduction type base region, first conduction type buried regions and source metal mutually insulated, and first conduction type buried regions and the first conduction type source electrode interval, and first between conduction type buried regions and the first conduction type base region each through the second conduction type base region interval.
2. the IGBT device with high resistance breech lock ability according to claim 1, it is characterized in that: on the second interarea of semiconductor substrate, be provided with collector structure, described collector structure includes collector electrode metal and the collector layer with described collector electrode metal Ohmic contact, collector layer is positioned between the second interarea of collector electrode metal and semiconductor substrate, and described collector layer includes the second conduction type collecting zone.
3. the IGBT device with high resistance breech lock ability according to claim 2, is characterized in that: be additionally provided with the first conductive type buffer layer between the second interarea of described collector layer and semiconductor substrate.
4. the IGBT device with high resistance breech lock ability according to claim 2, it is characterized in that: described collector layer also includes being positioned at some first conduction type collecting zones of the second conduction type collecting zone, the first conduction type collecting zone and collector electrode metal Ohmic contact.
5. the IGBT device with high resistance breech lock ability according to claim 1, is characterized in that: described active cellular is plane or channel form.
null6. the IGBT device with high resistance breech lock ability according to claim 5，It is characterized in that: when described active cellular adopts planar structure，On the cross section of described IGBT device，Described flat surface active cellular includes two adjacent the second conduction type base region and is positioned at the first conduction type source area of described second conduction type base region，The second adjacent conduction type base region is by the first conduction type base region separately，It is provided with conductive polycrystalline silicon and insulating medium layer in the surface of the first conduction type base region of adjacent second conductive type base, interval，Conductive polycrystalline silicon is dielectrically separated from by the first interarea and the source metal of insulating medium layer and semiconductor substrate，And the first conduction type source area of the two ends of conductive polycrystalline silicon and lower section overlaps mutually，The first conduction type buried regions and dielectric post it is respectively provided with in each second conduction type base region，It is positioned at the one end immediately below the first conduction type source area to contact with dielectric post，The other end of first conduction type buried regions contacts with the insulating medium layer on semiconductor substrate the first interarea，Described conductive polycrystalline silicon and gate metal Ohmic contact.
7. the IGBT device with high resistance breech lock ability according to claim 5, it is characterized in that: when described active cellular adopts channel form structure, on the cross section of described IGBT device, described active cellular includes the cellular groove being positioned at the second conduction type base region, the bottom land of described cellular groove is positioned at the first conduction type base region below the second conduction type base region, the inwall of cellular groove and diapire are coated with insulated gate oxide layer, and it is filled with conductive polycrystalline silicon in the cellular groove being coated with insulated gate oxide layer, the notch of cellular groove is covered by the insulating medium layer on semiconductor substrate the first interarea, conductive polycrystalline silicon in cellular groove is dielectrically separated from by insulating medium layer and source metal；First conduction type source area is positioned at above cellular groove outer wall side, the first conduction type source area, the first conduction type buried regions the other end contact with cellular groove outer wall, the conductive polycrystalline silicon in cellular groove and gate metal Ohmic contact.
8. the IGBT device with high resistance breech lock ability according to claim 1, is characterized in that: the material of described semiconductor substrate includes silicon, and described dielectric post includes silica column, and the height of dielectric post is less than the thickness of the second conduction type base region.
9. the IGBT device with high resistance breech lock ability according to claim 1, is characterized in that: the shape of described active cellular has a bar shape, square or circular.
10. the IGBT device with high resistance breech lock ability according to claim 1, it is characterized in that: in described first conduction type blocker ring, be provided with the second conduction type heavily doped region for forming anti-bolt lock structure, described second conduction type heavily doped region is positioned at outside and the lower section of the first conduction type source area, second conduction type heavily doped region and the first conduction type source region contact, and the length that the second conduction type heavily doped region is below the first conduction type source area is less than the length of the first conduction type source area.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256885A (en) * | 2017-06-30 | 2017-10-17 | 北京工业大学 | A kind of high stability insulation grid bipolar transistor and preparation method thereof |
| CN107994073A (en) * | 2017-12-27 | 2018-05-04 | 江苏中科君芯科技有限公司 | Lift the low on-state voltage drop IGBT of latch-up immunity |
| CN113497112A (en) * | 2020-03-19 | 2021-10-12 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, intelligent power device and electronic product |
| CN117476757A (en) * | 2023-12-28 | 2024-01-30 | 深圳天狼芯半导体有限公司 | IGBT with high latch-up resistance and preparation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1157488A (en) * | 1995-10-13 | 1997-08-20 | Abb管理有限公司 | Power semiconductor element |
| CN1317834A (en) * | 2000-04-13 | 2001-10-17 | 三洋电机株式会社 | Semiconductor device and mfg. method thereof |
| CN102064191A (en) * | 2010-11-02 | 2011-05-18 | 浙江大学 | Insulated gate bipolar transistor (IGBT) |
| CN205621739U (en) * | 2016-05-04 | 2016-10-05 | 江苏中科君芯科技有限公司 | IGBT device with high locking -resisting ability |
-
2016
- 2016-05-04 CN CN201610298661.6A patent/CN105762182B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1157488A (en) * | 1995-10-13 | 1997-08-20 | Abb管理有限公司 | Power semiconductor element |
| CN1317834A (en) * | 2000-04-13 | 2001-10-17 | 三洋电机株式会社 | Semiconductor device and mfg. method thereof |
| CN102064191A (en) * | 2010-11-02 | 2011-05-18 | 浙江大学 | Insulated gate bipolar transistor (IGBT) |
| CN205621739U (en) * | 2016-05-04 | 2016-10-05 | 江苏中科君芯科技有限公司 | IGBT device with high locking -resisting ability |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107256885A (en) * | 2017-06-30 | 2017-10-17 | 北京工业大学 | A kind of high stability insulation grid bipolar transistor and preparation method thereof |
| CN107994073A (en) * | 2017-12-27 | 2018-05-04 | 江苏中科君芯科技有限公司 | Lift the low on-state voltage drop IGBT of latch-up immunity |
| CN107994073B (en) * | 2017-12-27 | 2023-08-15 | 江苏中科君芯科技有限公司 | Low-on-state voltage drop IGBT capable of improving latch-up resistance |
| CN113497112A (en) * | 2020-03-19 | 2021-10-12 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, intelligent power device and electronic product |
| CN117476757A (en) * | 2023-12-28 | 2024-01-30 | 深圳天狼芯半导体有限公司 | IGBT with high latch-up resistance and preparation method |
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| CN105762182B (en) | 2018-11-06 |
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