CN104008971B - Trenched IGBT process for improving anti-short-circuit ability of devices - Google Patents
Trenched IGBT process for improving anti-short-circuit ability of devices Download PDFInfo
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- CN104008971B CN104008971B CN201410014263.8A CN201410014263A CN104008971B CN 104008971 B CN104008971 B CN 104008971B CN 201410014263 A CN201410014263 A CN 201410014263A CN 104008971 B CN104008971 B CN 104008971B
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- 238000000034 method Methods 0.000 title abstract description 33
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 2
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 238000000926 separation method Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 10
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a trenched IGBT device process for improving the anti-short-circuit ability of devices. Through a novel dummy trench process design, the channel density of devices is effectively reduced on the premise that the withstand voltage of the devices is not affected, thereby ensuring the short-circuit tolerance of the devices. Switching surge voltage caused by a traditional dummy process does not exist in the design, thus ensuring the working safety of the devices.
Description
Technical field
The present invention relates to trench-type insulated gate bipolar transistor (Trenched Insulated Gate Bipolar
Transistrors, IGBTs), relate more specifically to the groove-shaped IGBT device for having for boost device anti-short circuit capability.
Background technology
IGBT is the power power electronic device it is known that being widely used in power electronic equipment.For IGBT
For device, there is the JFET areas of parasitism between each unit's bag, JFET resistance is the important component part of device resistance, is also to cut
The key factor of weak IGBT bipolar devices conductance modulation effect.Therefore, the saturation conduction pressure drop overall in order to reduce device, adopts
Parasitism JFET areas are eliminated with plough groove type (Trench) structure, the overall conduction voltage drop of device can be effectively reduced.
Conventional groove IGBT current density is big, haves the shortcomings that anti-short circuit capability is poor.Therefore need close by reducing raceway groove
Spend to reduce saturation current density, to improve its anti-short circuit capability.Method by increasing spacing between groove, can be effectively
Gully density is reduced, but the pressure performance of device can be weakened.Therefore, in order in the gully density that can effectively reduce device
Meanwhile, keep pressure and be not subject to too big impact, generally realized using pseudo- groove (Dummy Trench) structure：Control whole
A part of grid groove normal work in device channel, other parts cannot carry out conduction, only as the work that maintenance is pressure
With.
Current pseudo- groove (Dummy Trench) structure is generally by the way of being electrically connected.Including by dummy
Grid connect with real trench-gate；Can be connected with emitter stage, it is also possible to floating, it is also possible to connect with the field limiting ring of termination environment
Connect.
And there is following defect by way of being electrically connected：When dummy grids are with real trench-gate or emitter stage
When electrode connects, the electric capacity between them can be caused to become big so that switching surge is larger, easily infringement switch.And floating dummy
Groove does not result in the shortcoming that switching loss is big or switching abnormal voltage is big, but due to its current potential floating, therefore can not have
Effect ensures its short-circuit tolerance and pressure.
The content of the invention
This patent is by the innovation in layout techniques, it is proposed that a kind of trench IGBT for boost device anti-short circuit capability
Device technology.The method can be effectively reduced the gully density of device by a kind of new dummy trench process design,
So as to ensure that the short-circuit tolerance of device.And the impact to the voltage endurance of device is very low.And due to there is no tradition
The surge voltage in switching process brought in dummy techniques, so as to avoid the switching loss of device, and then ensure that device
The security of part work.
According to the present invention, by under emitter stage, the local of the diffusion window of P+ type separation layer, along parallel to groove side
To extension in proportion, and be allowed to be covered in the trench-gate channel location that original P- raceway grooves are diffuseed to form.The P+ type diffusion
Higher concentration is spread with relative to P-type raceway groove, so that by such setting, the grid voltage in script can be made
Under the conditions of, be redefined P+ type doping raceway groove diffusion region cannot transoid, so as to the transoid of enough high concentrations cannot be formed
Electronics is realizing the N+ types emitter layer from below emitter stage to the conducting channel between N-type drift layer so that the ditch of the position
Fail in road, it is impossible to conductive.By such design, can effectively weaken gully density, the short-circuit tolerance of boost device.
Description of the drawings
Fig. 1 is the sectional view of the initial configuration of embodiments of the present invention
Fig. 2 is the sectional view of the embodiments of the present invention first step
Fig. 3 is the sectional view of embodiments of the present invention second step
Fig. 4 is the sectional view of the step of embodiments of the present invention the 3rd
Fig. 5 is the sectional view of the step of embodiments of the present invention the 4th
Fig. 6 is the top view of the step process of embodiment the 5th of traditional handicraft
Fig. 7 is the top view of the step process of embodiments of the present invention the 5th
Fig. 8 is the step process of embodiment the 5th of traditional handicraft along A-A directions/step process of embodiments of the present invention the 5th
Along the sectional view in C-C directions
Fig. 9 is sectional view of the step process of embodiments of the present invention the 5th along B-B directions
Specific embodiment
Figure (1-9) is a kind of trench IGBT process for boost device anti-short circuit capability, to identical or corresponding
Inscape marks identical reference, and repeat specification is omitted sometimes.
Fig. 1 is the initial configuration figure of the vertical trench IGBT technique of embodiments of the present invention, is along device cross-section
Material schematic diagram.For the initial configuration figure of the trench IGBT of boost device anti-short circuit capability, including drift layer 1.Drift layer
1, it is N conductive type semiconductor materials, the doping content scope of n type material is [1e12/cm3, 1e20/cm3]。
Fig. 2 is the first step process of the vertical trench IGBT technique of embodiments of the present invention, is mixed by ion implanting p-type
Miscellaneous element, by [20KeV, 1000KeV] scope implantation dosage scope in [1e12/cm2, 1e15/cm2] boron injection apply
To the semiconductor surface of Fig. 1, through annealing, P-type body layer 2 is formed.The layer is P conductive type semiconductor materials, P-type material
Doping content scope is [1e12/cm3, 1e20/cm3]。
Fig. 3 is the second step process of the vertical trench IGBT technique of embodiments of the present invention, is along device cross-section
Schematic diagram.Performed etching by the etching window of trench gate structure, form gate trench, depositing insulating layer 3, deposition grid is more
Crystal silicon filling 4, and the excess gate polysilicon and gate oxide insulating layer of etching groove structural outer.
Fig. 4 is the three step process of the vertical trench IGBT technique of embodiments of the present invention, and deposited oxide layer is simultaneously utilized
Etching window, by ion implanting n-type doping element, by existing in [20KeV, 1000KeV] scope implantation dosage scope
[1e12/cm2, 1e15/cm2] phosphorus injection be applied to established emitter stage injection etching window, through annealing, form N+ types
Emitter layer 5.
Fig. 5 is the 4th step process of the vertical trench IGBT technique of embodiments of the present invention, by the oxidation of deposition of thick
Layer, usually boron-phosphorosilicate glass (boron-phosphor-silicate-glass, BPSG), the surface of whole device is covered.
As the metal electrode separation layer of device surface, and make mask for the 5th step process.
Fig. 6 is the top view based on the above step process of embodiment the 5th of the traditional handicraft of four process steps, is passed through
The injection window of photoetching setting p-type separation layer simultaneously etches BPSG insulating barriers, the injecting mask 7 of p-type separation layer is formed, by ion
Implanting p-type doped chemical, by [20KeV, 1000KeV] scope by dosage range in [1e12/cm2, 1e16cm2] boron note
Enter BPSG masks 7, through annealing, form P+ type separation layer 8.The layer be P conductive type semiconductor materials, the doping of P-type material
Concentration range is [1e12/cm3, 1e20/cm3], the doping content of this layer of P conductive type semiconductor material is higher than P-type body layer
2 doping content.
Fig. 7 is the 5th step based on the above vertical trench IGBT technique of the embodiments of the present invention of four process steps
The top view of technique, sets the injection window of p-type separation layer and etches BPSG insulating barriers by photoetching, forms p-type separation layer
Injecting mask 9, by ion implanting p-type doped chemical, by existing in [20KeV, 1000KeV] scope implantation dosage scope
[1e12/cm2, 1e15/cm2] boron injection BPSG masks 7, through annealing, form P+ type separation layer 8.The layer is P conduction types
Semi-conducting material, the doping content scope of P-type material is [1e12/cm3, le20/cm3], this layer of P conductive type semiconductor material
Doping content, be higher than the doping content of P-type body layer 2.And due to the injecting mask 9 of the p-type separation layer define along hang down
The parallel direction of straight flute extends to the broken line edge windows of an angle of 90 degrees, therefore diverse location in this direction, the p-type for carrying out
The window width of the injecting mask 9 of separation layer is divided into two kinds：The injecting mask 9 of the p-type separation layer of C-C directions position along in figure
Window with consistent along the window width of the injecting mask 7 of the p-type separation layer of A-A directions position in figure (8), and along in figure
The window width of the injecting mask 9 of the p-type separation layer of B-B directions position, will widen to both sides equivalent, to ensure to enter in the position
The injection of capable p-type separation layer can realize the covering in the P- bodies area 2 in the grid groove region to the position groove.
In the process, described unit is in singulated dies up to thousands of kinds.Here term tube core and crystalline substance
Piece can be used interchangeably.
Although describing the present invention relative to specific enforcement, many other changes to those skilled in the art
Change, amendment and other using will become clear from.It is therefore preferable that the invention is not restricted to specifically disclosed content here.
Claims (6)
1. a kind of trench IGBT device for boost device anti-short circuit capability, comprising：
A kind of conduction type and with the monocrystalline silicon body of the first concentration, and with parallel top and bottom surface, extend perpendicularly to
The groove at multiple intervals of given depth in the top surface, the gate insulator of the vertical wall of groove, is formed in described in liner
Between each described groove and have the depth less than the gash depth other conduction types raceway groove diffusion；From described
The top surface of body extends and along the emitter stage of monosymmetric a kind of conduction type on the top of groove each described
Diffusion；Given spacing between the top that the emitter diffusion passes through the groove is isolated from each other；With than raceway groove expansion
The diffusion of the high concentration of scattered concentration and other conduction types being arranged between the adjacent emitter diffusion pair；Tool
There is the concentration higher than the raceway groove diffusion concentration and be selectively arranged on the raceway groove diffusion position between groove
The raceway groove diffusion of other conduction types.
2. device as claimed in claim 1, the wherein top surface of each emitter region have and extend and along described in each
The emitter stage high concentration diffusion of monosymmetric a kind of conduction type on the top of groove, and the diffusion has 0.01-0.5 micro-
Rice depth and 0.05-2 microns width, and wherein emitter region have away from its each the shallow of raceway groove extend laterally,
The emitter metal is contacted to provide the contact surface of increase.
3. device as claimed in claim 1, have wherein between the groove described in each concentration higher than raceway groove diffusion concentration and
Selectively spread in the raceway groove for being arranged on other conduction types of the raceway groove diffusion position between groove, and high concentration
Raceway groove is diffused as selectively covering raceway groove diffusion according to the fixed proportion of gully density regulatory demand.
4. device as claimed in claim 1, wherein a kind of conduction type is N-type, described other conduction types are p-type.
5. device as claimed in claim 1, wherein the groove is laterally spaced straight parallel groove.
6. device as claimed in claim 1, wherein described selective other conduction type raceway grooves diffusions for covering raceway groove diffusion, are horizontal
To the broken line type distribution for covering in proportion at interval.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410014263.8A CN104008971B (en) | 2014-01-13 | 2014-01-13 | Trenched IGBT process for improving anti-short-circuit ability of devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410014263.8A CN104008971B (en) | 2014-01-13 | 2014-01-13 | Trenched IGBT process for improving anti-short-circuit ability of devices |
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| Publication Number | Publication Date |
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| CN104008971A CN104008971A (en) | 2014-08-27 |
| CN104008971B true CN104008971B (en) | 2017-05-03 |
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| CN201410014263.8A Expired - Fee Related CN104008971B (en) | 2014-01-13 | 2014-01-13 | Trenched IGBT process for improving anti-short-circuit ability of devices |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835735A (en) * | 2015-05-07 | 2015-08-12 | 嘉兴斯达微电子有限公司 | Trench IGBT device manufacturing method |
| CN113506826B (en) * | 2021-06-17 | 2023-07-07 | 重庆伟特森电子科技有限公司 | Groove type silicon carbide transistor and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219241A (en) * | 2012-01-19 | 2013-07-24 | 立新半导体有限公司 | Method of preparing groove discrete semiconductor device |
| CN103474458A (en) * | 2013-08-14 | 2013-12-25 | 中航（重庆）微电子有限公司 | Insulated gate bipolar transistor (IGBT) device and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8441046B2 (en) * | 2010-10-31 | 2013-05-14 | Alpha And Omega Semiconductor Incorporated | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances |
| JP5594276B2 (en) * | 2010-12-08 | 2014-09-24 | 株式会社デンソー | Insulated gate semiconductor device |
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2014
- 2014-01-13 CN CN201410014263.8A patent/CN104008971B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219241A (en) * | 2012-01-19 | 2013-07-24 | 立新半导体有限公司 | Method of preparing groove discrete semiconductor device |
| CN103474458A (en) * | 2013-08-14 | 2013-12-25 | 中航（重庆）微电子有限公司 | Insulated gate bipolar transistor (IGBT) device and preparation method thereof |
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