CN103219241A - Method of preparing groove discrete semiconductor device - Google Patents
Method of preparing groove discrete semiconductor device Download PDFInfo
- Publication number
- CN103219241A CN103219241A CN2012100191974A CN201210019197A CN103219241A CN 103219241 A CN103219241 A CN 103219241A CN 2012100191974 A CN2012100191974 A CN 2012100191974A CN 201210019197 A CN201210019197 A CN 201210019197A CN 103219241 A CN103219241 A CN 103219241A
- Authority
- CN
- China
- Prior art keywords
- type
- contact hole
- layer
- oxide layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a method of preparing a groove discrete semiconductor device. The method comprises the following steps: first, injecting P type dopant into an epitaxial layer of a substrate to form a P type area I by using a groove mask, and carrying out etching on the external layer to form a plurality of grid electrode grooves; then depositing interlamination media on the surface of the external layer, carrying out etching on the interlamination media by using a contact hole mask to form openings in the interlamination media, and injecting the P type dopant and N type dopant to the openings to form a P type area II and an N type source region respectively, wherein the P type area I and the P type area II are combined into a P type base region; then carrying out etching on the surface of the external layer to form contact hole grooves, and carrying out metal plugging filling on the contact hole grooves; and finally, depositing a metal layer on the surface of a device, carrying out metal etching by using metal mask to form a metal cushion layer and connection wires. By adopting the method of preparing the groove discrete semiconductor device, preparation procedures of base region masking and source region masking are eliminated, and the preparation cost of the device is made to be greatly reduced.
Description
Technical field
The present invention relates to semiconductor power discrete device technical field, specifically, relate to a kind of preparation method of trench semiconductor power discrete device.
Background technology
At present, power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, mos field effect transistor) has been widely used in each electron-like, communication product, computer, consumer appliances, automobile etc., simultaneously, it also has a multiple application industrial.
The power semiconductor of power MOSFET representative, but because the low and speed-sensitive switch of conducting resistance, so it can control the big electric current of high frequency effectively.Simultaneously, power MOSFET is just being utilized power unit switch, power circuit at for example power amplifier, power converter, low noise amplifier and some personal computers widely as the mini power conversion element, is characterized in that low-power consumption, speed are fast.
Groove type power MOS FET, because of it has the structural efficient and low advantage of on-resistance characteristics, control is widely used with electronic device as power supply for it, the flourish power circuit that requires of industry has higher efficient and littler power consumption, require low price simultaneously, force manufacturer that cost of manufacture is reduced.
In the design and manufacturing field of existing groove type power MOS FET, the base of MOSFET and source region are all to need base mask and active region mask step to introduce separately, in order to reduce manufacturing cost, propose before some, as the american documentation literature US20110233667 that discloses, US20090085074, US20110233666, US077996427 etc., attempt to omit the manufacture method of base or active region mask step, its step is comparatively complicated, is difficult for generating, and the terminal of the semiconductor device that produces (termination) structure is bad, so that the puncture voltage of device is also relative with reliability relatively poor.
Summary of the invention
The present invention has overcome shortcoming of the prior art, a kind of method for preparing the trench semiconductor discrete device is provided, its groove type power discrete device manufacture method step before is few, omit base and active region mask step or only omitted the base masks, reduced the manufacturing cost of groove type power discrete device, and do not influence the electric property of groove type power discrete device, q﹠r, and then improved the ratio of performance to price of semiconductor device.
The present invention can be used for preparing the trench semiconductor power discrete device of 12V to 1200V.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions:
A kind of method for preparing the trench semiconductor discrete device may further comprise the steps:
(1) utilizes trench mask that the epitaxial loayer on the substrate 10 200 is injected P type dopants and form P types 1 district 201, and on epitaxial loayer, corrode and form a plurality of gate trenchs;
(2) at epi-layer surface deposition inter-level dielectric 401, utilize contact hole mask again, inter-level dielectric is corroded, in inter-level dielectric, form perforate, inject P type and N type dopant then, form P type 2 districts 202 and N type source region 204 respectively, afterwards epi-layer surface is corroded formation contact hole groove, and the contact hole groove is carried out metal plug 502 fill;
(3) at the upper surface depositing metal layers 404 of device, utilize metal mask to carry out metal attack, form metal bed course and line.
Further, described step (1) may further comprise the steps:
A, on epitaxial loayer the formation oxide layer, accumulation lithography coating 1000 on oxide layer, expose the partial oxidation layer by trench mask again, the partial oxidation layer that exposes is carried out dry corrosion, until exposing epitaxial loayer, be formed on a plurality of trench mask perforates on the oxide layer, dispose lithography coating then;
B, inject P type dopant on the surface, the part that has former oxide layer to cover is not injected into, and the part that does not have former oxide layer to cover can be injected into, and by a High temperature diffusion operation P type dopant is advanced to be diffused into and form P type 1 district 201 in the epitaxial loayer;
C, form groove 300 by etching, this groove passes P type 1 district and extends to epitaxial loayer, to the oxidation of groove sacrifice property, disposes all oxide layers then;
D, in sidewall and bottom that groove is exposing, and the upper surface of epitaxial loayer forms grid oxic horizon 301, the polysilicon 302 of deposition N type high dopant in groove again is with filling groove and cover end face;
E, the polysilicon layer on epi-layer surface is carried out plane corrosion treatment or chemico-mechanical polishing.
Further, it is characterized in that in step a, described a plurality of trench mask aperture widths are different, width range wherein is 0.2um to 2.0um.
Further, it is characterized in that, in step a, after disposing lithography coating, form the new oxide layer of one deck in the epi-layer surface that exposes.
Further, it is characterized in that in steps d, by the mode of heat growth, in sidewall and the bottom that groove is exposing, and the upper surface of epitaxial loayer forms grid oxic horizon.
Further, described step (1) may further comprise the steps in a kind of modification of the present invention (embodiment): in step b, after P type dopant is injected on the surface, just precipitating layer of oxide layer also seals up at least one the trench mask perforate in oxide layer, the aperture widths of sealing up can be 0.2um, or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, then oxide layer is carried out dry corrosion, remove the oxide layer in the perforate, expose the epitaxial loayer in the perforate, then enter step c, need not pass through a High temperature diffusion operation.
Further, described step (1) may further comprise the steps in a kind of modification of the present invention (embodiment): in step c, before etching groove, the precipitation layer of oxide layer is also sealed up at least one the trench mask perforate in oxide layer earlier, the aperture widths of sealing up can be 0.2um, or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, the benefit of this step is the perforate of some trench mask to be had injected by P type dopant to form P type 1 district but do not left groove, then oxide layer is carried out dry corrosion, remove the oxide layer in the perforate, expose the epitaxial loayer in the perforate; Etching groove afterwards.
Further, it is characterized in that in step b, a described High temperature diffusion processing temperature is 950 to 1200 ℃, the time is 10 minutes to 1000 minutes.
Further, described step (2) may further comprise the steps:
A, at topsheet surface deposition inter-level dielectric;
B, at inter-level dielectric surface accumulation lithography coating, utilize contact hole mask to expose the part inter-level dielectric, then the part inter-level dielectric that exposes is carried out dry corrosion, until exposing epitaxial loayer, in inter-level dielectric, form a plurality of contact hole mask perforates, dispose lithography coating then;
C, inject P type dopant on the surface, the part that has inter-level dielectric to cover is not injected into, the part that does not have inter-level dielectric to cover, P type dopant can be injected on the epi-layer surface, and by the operation of secondary High temperature diffusion P type dopant is advanced to be diffused into and form P type 2 districts in the epitaxial loayer, P type 1 district and P type 2 districts synthesize P type base 203;
D, inject N type dopant on the surface, the part that has inter-level dielectric to cover is not injected into, the part that does not have inter-level dielectric to cover, N type dopant can be injected on the epi-layer surface, and by three High temperature diffusion operations the propelling of N type dopant is diffused into formation N type source region 204 in the P type base;
E, by the inter-level dielectric perforate, epi-layer surface is corroded, form the contact hole groove, the contact hole groove passes N type source region and enters into P type base, afterwards the contact hole groove is injected P type high dopant;
F, on contact hole trenched side-wall, bottom and inter-level dielectric surface, deposit one deck titanium layer and one deck titanium nitride layer successively, again the contact hole groove is carried out tungsten and fill to form contact hole trench metal connector.
Further, described step (2) is characterised in that, in step a, deposits undoped silicon successively and boro-phosphorus glass forms inter-level dielectric in topsheet surface.
Further, described step (2) is characterised in that in step b, the aperture widths of described a plurality of contact hole masks is all equally big or small.
Further, described step (2) is characterised in that in step b, described contact hole mask aperture widths is not all equally big or small, and width range is 0.2um to 1.6um.
Further, described step (2) is characterised in that described secondary High temperature diffusion processing temperature is 950 to 1200 ℃, and the time is 10 minutes to 1000 minutes, and described three High temperature diffusion processing temperatures are 950 to 1200 ℃, and the time is 10 minutes to 100 minutes.
Further, described step (2) may further comprise the steps in a kind of modification of the present invention (embodiment):
In step e, before etching contact hole groove, the precipitation layer of oxide layer is carried out dry corrosion to oxide layer then earlier, disposes the oxide layer in the perforate, exposes the epitaxial loayer in the perforate; Etching contact hole groove afterwards, other steps are identical with described step (2), and the benefit of this step is to make the P type high dopant of injecting from the contact hole groove keep clear of trenched side-wall (raceway groove of device) relatively.
Further, described step (2) may further comprise the steps in a kind of modification of the present invention (embodiment): in step e, the width of contact hole mask perforate is not all equally big or small, before etching contact hole groove, the precipitation layer of oxide layer is also sealed up at least one the contact hole mask perforate in inter-level dielectric earlier, the aperture widths of sealing up can be that 0.2um or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, the benefit of this step is to make those contact hole perforates of being sealed up not have metal plug therein, does not also form the contact hole groove; Then oxide layer is carried out dry corrosion, dispose the oxide layer in the contact hole perforate of not sealed up, expose the epitaxial loayer in the perforate; Etching contact hole groove afterwards, other steps are identical with described step (2).
Further, described step (2) may further comprise the steps in a kind of modification of the present invention (embodiment):
In steps d, the width of contact hole mask perforate is not all equally big or small, before N type dopant is injected on the surface, the precipitation layer of oxide layer is also sealed up at least one the contact hole mask perforate in inter-level dielectric earlier, the aperture widths of sealing up can be that 0.2um or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, the benefit of this step is those are injected by N type dopant by the contact hole perforates of being sealed up and not have metal plug therein, does not also form the contact hole groove; Then N type dopant is injected on the surface, at this moment N type dopant can only inject those perforates of not sealed up, and other steps are identical with described (2).
Preparation method of the present invention also can be used for only having omitted the base mask and the source region needs the active region mask step to introduce, and its preparation method may further comprise the steps:
(1) utilizes trench mask that the epitaxial loayer on the substrate 10 200 is injected P type dopants and form P type bases, and on epitaxial loayer, corrode and form a plurality of gate trenchs;
(2) utilize the active region mask step to form the source region;
(3) at epi-layer surface deposition inter-level dielectric, utilize contact hole mask to form the contact hole groove again, and the contact hole groove is carried out metal plug fill;
(4) at the upper surface depositing metal layers of device, utilize metal mask to carry out metal attack, form metal bed course and line.
Further, described step (1) may further comprise the steps:
A, on epitaxial loayer the formation oxide layer, accumulation lithography coating on oxide layer, expose the partial oxidation layer by trench mask again, the partial oxidation layer that exposes is carried out dry corrosion, until exposing epitaxial loayer, be formed on a plurality of trench mask perforates on the oxide layer, the trench mask aperture widths is different, width range wherein is 0.2um to 2.0um, disposes lithography coating then;
B, P type dopant is injected on the surface, the part that has former oxide layer to cover is not injected into, the part that does not have former oxide layer to cover, P type dopant can be injected on the epi-layer surface, and by a High temperature diffusion operation propelling of P type dopant is diffused into formation P type base in the epitaxial loayer;
C, form groove by being etched in tapping, this groove passes P type base and extends in the epitaxial loayer, to the oxidation of groove sacrifice property, disposes all oxide layers then;
D, in sidewall and bottom that groove is exposing, and the upper surface of epitaxial loayer forms grid oxic horizon, the polysilicon of deposition N type high dopant in groove again is with filling groove and cover end face;
E, the polysilicon layer on epi-layer surface is carried out plane corrosion treatment or chemico-mechanical polishing.
Further, described step (1) is in step b, after P type dopant is injected on the surface, just precipitate layer of oxide layer and at least one trench mask perforate in oxide layer is sealed up, the aperture widths of sealing up can be 0.2um, or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, then oxide layer is carried out dry corrosion, remove the oxide layer in the perforate, expose the epitaxial loayer in the perforate, then enter step c, need not pass through a High temperature diffusion operation.
Compared with prior art, the invention has the beneficial effects as follows:
Adopt preparation method of the present invention, omitted the preparation section of base mask and active region mask or only omitted the preparation section of base mask,, make the manufacturing cost of device obtain bigger reduction; Simultaneously can not influence the original electrical characteristic of device, thereby increase the ratio of performance to price of device, and not influence the q﹠r of groove type power discrete device.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, is used from explanation the present invention with embodiments of the invention one, be not construed as limiting the invention, in the accompanying drawings:
Fig. 1 is exposure oxide layer 400 schematic diagrames of the embodiment of the invention 1;
Fig. 2 is the exposure epitaxial loayer schematic diagram of the embodiment of the invention 1;
Fig. 3 is the injection P type dopant schematic diagram of the embodiment of the invention 1;
Fig. 4 is P type 1 district 201 schematic diagrames of the embodiment of the invention 1;
Fig. 5 is groove 300 schematic diagrames of the embodiment of the invention 1;
Fig. 6 is all sacrifice property oxide layer schematic diagrames of disposing of the embodiment of the invention 1;
Fig. 7 is grid oxic horizon 301 schematic diagrames of the embodiment of the invention 1;
Fig. 8 is the highly doped polysilicon of the deposition of the embodiment of the invention 1 302 schematic diagrames;
Fig. 9 be the embodiment of the invention 1 carry out the plane treatment schematic diagram;
Figure 10 is inter-level dielectric 401 schematic diagrames of the embodiment of the invention 1;
Figure 11 be the embodiment of the invention 1 to contact hole to injecting P type dopant schematic diagram;
Figure 12 is P type base 203 schematic diagrames of the embodiment of the invention 1;
Figure 13 be the embodiment of the invention 1 to contact hole to injecting N type dopant schematic diagram;
Figure 14 is N type source region 204 schematic diagrames of the embodiment of the invention 1;
Figure 15 is that the contact hole groove of the embodiment of the invention 1 shows 501 intentions;
Figure 16 is metal plug 502 schematic diagrames of the embodiment of the invention 1;
Figure 17 is albronze layer 404 schematic diagram of the embodiment of the invention 1;
Figure 18 is the cross sectional representation of the device of the embodiment of the invention 2 (a kind of modification of the present invention);
Figure 19 is the cross sectional representation of the device of the embodiment of the invention 3 (a kind of modification of the present invention);
Figure 20 is the cross sectional representation of the device of the embodiment of the invention 4 (a kind of modification of the present invention);
Figure 21 is the cross sectional representation of the device of the embodiment of the invention 5 (a kind of modification of the present invention);
Figure 22 is the cross sectional representation of the device of the embodiment of the invention 6 (a kind of modification of embodiment).
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
A kind of method for preparing the trench semiconductor discrete device of the present invention may further comprise the steps: at first utilize trench mask that the epitaxial loayer on the substrate is injected P type dopant and form P type 1 district, and corrode on epitaxial loayer and form a plurality of gate trenchs; Then, at epi-layer surface deposition inter-level dielectric, utilize contact hole mask again, inter-level dielectric is corroded, in inter-level dielectric, form perforate, inject P type and N type dopant then, form P type 2 districts and N type source region respectively, afterwards epi-layer surface is corroded formation contact hole groove, and the contact hole groove is carried out metal plug fill; At last,, utilize metal mask to carry out metal attack, form metal bed course and line at the surface deposition metal level of device.
Embodiment 1:
As shown in Figure 1, epitaxial loayer 200 places the top of substrate 10, at first employing accumulation or hot growth pattern form oxide layer 400 (thickness is 0.3um to 1.5um oxide hard light shield) on epitaxial loayer, accumulation one deck lithography coating 1000 again on oxide layer forms the some parts that pattern exposes oxide layer by trench mask then.
As shown in Figure 2, after trench mask formed oxide layer that pattern exposes and carry out dry corrosion, expose epitaxial loayer, dispose lithography coating then.
As shown in Figure 3, (dosage is 2e12/cm silicon chip surface to be injected P type dopant
3To 2e14/cm
3), the part that has former oxide layer 400 to cover is not injected into, the part that does not have former oxide layer to cover, and P type dopant can be injected into and form p type island region on the epi-layer surface, and P type dopant can adopt B11 (boron boron).
As shown in Figure 4, the P type dopant of injection is pushed into to be diffused into by a High temperature diffusion operation (time is 10 minutes to 1000 minutes, and temperature is 950 ℃ to 1200 ℃) and forms P type 1 district 201 in the epitaxial loayer.The formed P type 1 district's degree of depth of this step (degree of depth is 0.3um to 4.0um) is not a ultimate depth, because also have other high-temperature operation after this step, so the formed P type 1 district's degree of depth of this step will suitably be adjusted.
As shown in Figure 5, form groove 300 by etching, this groove (degree of depth is 1.0um to 7.0um, and width is 0.2um to 2.0um) passes P type 1 district and extends to N type epitaxial loayer.
As shown in Figure 6, after forming groove, (time is 10 minutes to 100 minutes to the oxidation of groove sacrifice property, temperature is 1000 ℃ to 1200 ℃), to eliminate the silicon layer (sacrifice property oxidation operation meeting further advances P type alloy and is diffused into epitaxial loayer) that in grooving process, is destroyed, dispose all oxide layers then by plasma.As shown in Figure 7, and the mode by heat growth, the sidewall that is exposing at groove and the upper surface of bottom and epitaxial loayer form the thin grid oxic horizon 301 (thickness is 0.02um to 0.12um) of one deck.
As shown in Figure 8, the polysilicon 302 of deposition N type high dopant in groove, polysilicon doping concentration is R
S=5 Ω/ to 100 Ω/ (side resistance) are with filling groove and cover end face.
As shown in Figure 9, then the polysilicon layer on epi-layer surface is carried out plane corrosion treatment or chemico-mechanical polishing.
As shown in figure 10, on epitaxial loayer is the most surperficial, deposit undoped silicon dioxide layer (thickness is 0.1um to 0.5um) earlier, deposit boro-phosphorus glass (thickness is 0.1um to 0.8um) then and form inter-level dielectric 401.
As shown in figure 11, at inter-level dielectric surface accumulation lithography coating, utilize contact hole mask to expose the part inter-level dielectric, then the part inter-level dielectric that exposes is carried out dry corrosion, until exposing epitaxial loayer, in inter-level dielectric, form a plurality of contact hole mask perforates 500, dispose lithography coating then; (boron, dosage are 2e12/cm then to inject P type dopant to epitaxial loayer
3To 2e14/cm
3).
As shown in figure 12, handle by the secondary High temperature diffusion, the high-temperature operation temperature is 950 to 1200 ℃, and the time is 10 minutes to 1000 minutes, P type dopant Tui Jin is diffused into forms P type 2 districts on the epitaxial loayer, and P type 1 district and P type 2 districts synthesize P type base 203.
As shown in figure 13, (phosphorus or arsenic, dosage are 1e15/cm to inject N type dopant to epitaxial loayer again
3To 2e16/cm
3), on epitaxial loayer, form N type district.
As shown in figure 14, handle by three High temperature diffusion, temperature is 950 to 1200 ℃, and the time is 10 minutes to 100 minutes, make N type Qu Tui Jin be diffused into P type base and form N type source region 204 (N type active area depth is 0.2um to 0.8um, and the P type base degree of depth is 0.5um to 4.5um).
As shown in figure 15, pass through contact hole mask, the epitaxial loayer that contains dopant is carried out etch, (degree of depth is 0.4um to 1.0um to make contact hole groove 501, width is 0.2um to 1.6um) pass N type source region and enter into P type base, afterwards the contact hole groove is injected P type high dopant 205, assorted agent concentration is 10
14To 5 * 10
15/ cm
3, to reduce the contact resistance between P type base and metal plug, this increases the safe handling district of device effectively.
As shown in figure 16, at contact hole trenched side-wall, bottom and epitaxial loayer upper surface deposition one deck titanium/titanium nitride layer 402, then the contact hole groove is carried out tungsten 403 and fill to form metal plug 502.
As shown in figure 17,, carry out the metal etch by metal mask then, form metal bed course and line at this deposition layer of aluminum copper alloy 404 (thickness is 0.8um to 10um) above device.
Embodiment 2:
The technical scheme of present embodiment and embodiment 1 are roughly the same, and its difference only is:
In the foregoing description 1 before Fig. 5 etching groove, the precipitation layer of oxide layer is also sealed up the trench mask aperture widths scope in oxide layer by the perforate of 0.2um to 0.6um earlier, the aperture widths of sealing up can be that 0.2um or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, the benefit of this step is the perforate of some trench mask to be had injected (P type 1 district) by P type dopant but do not left groove, the terminal structure of device is better, thereby the puncture voltage of device is higher and more stable, then oxide layer is carried out dry corrosion, remove the oxide layer in the perforate, expose the epitaxial loayer in the perforate; Etching groove afterwards, at this moment the perforate of having only those not precipitated oxide layers to seal up is just left groove, and this groove (degree of depth is 1.0um to 7.0um, and width is 0.2um to 2.0um) passes P type 1 district and extends to epitaxial loayer, other steps are identical with embodiment 1, and the cross section of device as shown in figure 18.
Embodiment 3:
The technical scheme of present embodiment and embodiment 1 are roughly the same, and its difference only is:
Figure 15 is before etching contact hole groove in the foregoing description 1, and precipitation one deck (LPCVD) oxide layer is carried out dry corrosion to oxide layer then earlier, removes the oxide layer in the contact hole trenches openings, exposes the epitaxial loayer in the perforate; Etching contact hole groove afterwards.Other steps are identical with embodiment 1 substantially, and the cross section of device as shown in figure 19.
Embodiment 4:
The technical scheme of present embodiment and embodiment 2 are roughly the same, and its difference only is:
In the foregoing description 2, before etching contact hole groove, precipitation one deck (LPCVD) oxide layer is carried out dry corrosion to oxide layer then earlier, removes the oxide layer in the contact hole trenches openings, exposes the epitaxial loayer in the perforate; Etching contact hole groove afterwards.Other steps are identical with embodiment 2 substantially, and the cross section of device as shown in figure 20.
Embodiment 5:
Be a kind of modification of the present invention.
Step is identical with embodiment 1, just:
Before the dopant in N type source region is injected on the surface, the precipitation layer of oxide layer is also sealed up contact hole mask aperture widths scope in inter-level dielectric by the perforate of 0.2um to 0.6um earlier, the aperture widths of sealing up can be that 0.2um or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, then the surface is injected the dopant in N type source region, other steps are identical with embodiment 1 described step, and the cross section of device as shown in figure 21.
The benefit of embodiment 5 is those are injected by N type dopant by the contact hole perforates of being sealed up and not have metal plug therein, does not also form the contact hole groove.
Embodiment 6:
Be a kind of modification of the present invention.
Step is identical with embodiment 2, just:
Before the dopant in N type source region is injected on the surface, the precipitation layer of oxide layer is also sealed up contact hole mask aperture widths scope in inter-level dielectric by the perforate of 0.2um to 0.6um earlier, the aperture widths of sealing up can be that 0.2um or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, then the surface is injected the dopant in N type source region, other steps are identical with embodiment 2 described steps, and the cross section of device as shown in figure 22.
The benefit of embodiment 6 is the perforate of some trench mask to be had injected (P type 1 district) by P type dopant but do not left groove, some contact hole perforate has by P type dopant injection (P type 2 districts) but by the injection of N type dopant and does not have metal plug therein, do not form the contact hole groove yet, the benefit of this embodiment is to make the terminal structure of device better, thereby the puncture voltage of device is higher and more stable.
It should be noted that at last: above only is the preferred embodiments of the present invention; be not limited to the present invention; the present invention (for example can be used for relating to manufacturing trench semiconductor power discrete device; insulated trench gate bipolar transistor (Trench IGBT) or trench diode; groove has special based diode); the present invention can be used for preparing the trench semiconductor power discrete device of 12V to 1200V; embodiments of the invention are to make an explanation with N type passage device; the present invention also can be used for P type passage device; although the present invention is had been described in detail with reference to embodiment; for a person skilled in the art; it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing; perhaps part technical characterictic wherein is equal to replacement; but it is within the spirit and principles in the present invention all; any modification of being done; be equal to replacement; improve etc., all should be included in protection scope of the present invention it.
The reference symbol table:
10 substrates
200 epitaxial loayers
201 P types, 1 district
202 P types, 2 districts
203 P type bases
204 N type source regions
The P type high-doped zone of 205 contact hole channel bottoms
300 grooves
301 grid oxic horizons
302 highly doped polysilicons
400 oxide layers
401 inter-level dielectrics
402 titaniums/titanium nitride
403 tungsten
404 aluminium coppers
405 LPCVD oxide layers
The 500 contact hole mask perforates that in inter-level dielectric, form
501 contact hole grooves
502 metal plugs
1000 lithography coatings
Claims (12)
1. a method for preparing the trench semiconductor discrete device is characterized in that, may further comprise the steps:
(1) utilizes trench mask that the epitaxial loayer on the substrate is injected P type dopant and form P type 1 district, and on epitaxial loayer, corrode and form a plurality of gate trenchs;
(2) at epi-layer surface deposition inter-level dielectric, utilize contact hole mask again, inter-level dielectric is corroded, in inter-level dielectric, form perforate, inject P type and N type dopant then, form P type 2 districts and N type source region respectively, afterwards epi-layer surface is corroded formation contact hole groove, and the contact hole groove is carried out metal plug fill;
(3) at the surface deposition metal level of device, utilize metal mask to carry out metal attack, form metal bed course and line.
2. a kind of method for preparing the trench semiconductor discrete device according to claim 1 is characterized in that, described step (1) may further comprise the steps:
A, on epitaxial loayer the formation oxide layer, accumulation lithography coating on oxide layer, expose the partial oxidation layer by trench mask again, the partial oxidation layer that exposes is carried out dry corrosion, until exposing epitaxial loayer, be formed on a plurality of trench mask perforates on the oxide layer, the trench mask aperture widths is different, width range wherein is 0.2um to 2.0um, disposes lithography coating then;
B, P type dopant is injected on the surface, the part that has former oxide layer to cover is not injected into, the part that does not have former oxide layer to cover, P type dopant can be injected on the epi-layer surface, and by a High temperature diffusion operation propelling of P type dopant is diffused into formation P type 1 district in the epitaxial loayer;
C, form groove by being etched in tapping, this groove passes P type 1 district and extends in the epitaxial loayer, to the oxidation of groove sacrifice property, disposes all oxide layers then;
D, in sidewall and bottom that groove is exposing, and the upper surface of epitaxial loayer forms grid oxic horizon, the polysilicon of deposition N type high dopant in groove again is with filling groove and cover end face;
E, the polysilicon layer on epi-layer surface is carried out plane corrosion treatment or chemico-mechanical polishing.
3. a kind of method for preparing the trench semiconductor discrete device according to claim 2 is characterized in that, in step a, after disposing lithography coating, forms the new oxide layer of one deck in the epi-layer surface that exposes.
4. a kind of method for preparing the trench semiconductor discrete device according to claim 2, it is characterized in that, in step b, after P type dopant is injected on the surface, just precipitating layer of oxide layer also seals up at least one the trench mask perforate in oxide layer, the aperture widths of sealing up can be 0.2um, or 0.3um or 0.4um or 0.5um or 0.6um do not wait, decide on the preparation method, then oxide layer is carried out dry corrosion, remove the oxide layer in the perforate, expose the epitaxial loayer in the perforate, then enter step c, need not pass through a High temperature diffusion operation.
5. a kind of method for preparing the trench semiconductor discrete device according to claim 2, it is characterized in that, in step c, before etching groove, the precipitation layer of oxide layer is also sealed up at least one the trench mask perforate in oxide layer earlier, then oxide layer is carried out dry corrosion, removes the oxide layer in the perforate, expose the epitaxial loayer in the perforate, afterwards etching groove.
6. a kind of method for preparing the trench semiconductor discrete device according to claim 1 is characterized in that, described step (2) may further comprise the steps:
A, at topsheet surface deposition inter-level dielectric;
B, at inter-level dielectric surface accumulation lithography coating, utilize contact hole mask to expose the part inter-level dielectric, then the part inter-level dielectric that exposes is carried out dry corrosion, until exposing epitaxial loayer, in inter-level dielectric, form a plurality of contact hole mask perforates, a plurality of contact hole mask aperture widths can not be all equally big or small, and width range is 0.2um to 1.6um, disposes lithography coating then;
C, inject P type dopant on the surface, the part that has inter-level dielectric to cover is not injected into, the part that does not have inter-level dielectric to cover, P type dopant can be injected on the epi-layer surface, and by the operation of secondary High temperature diffusion P type dopant is advanced to be diffused into and form P type 2 districts in the epitaxial loayer, P type 1 district and P type 2 districts synthesize P type base;
D, inject N type dopant on the surface, the part that has inter-level dielectric to cover is not injected into, the part that does not have inter-level dielectric to cover, N type dopant can be injected on the epi-layer surface, and by three High temperature diffusion operations the propelling of N type dopant is diffused into formation N type source region in the P type base;
E, by the inter-level dielectric perforate, epi-layer surface is corroded, form the contact hole groove, the contact hole groove passes N type source region and enters into P type base, afterwards the contact hole groove is injected P type high dopant;
F, on contact hole trenched side-wall, bottom and inter-level dielectric surface, deposit one deck titanium layer and one deck titanium nitride layer successively, again the contact hole groove is carried out tungsten and fill to form the trench metal connector.
7. a kind of method for preparing the trench semiconductor discrete device according to claim 6, it is characterized in that, in steps d, the width of contact hole mask perforate is not all equally big or small, before N type dopant is injected on the surface, the precipitation layer of oxide layer is also sealed up at least one the contact hole mask perforate in inter-level dielectric earlier, then N type dopant is injected on the surface.
8. a kind of method for preparing the trench semiconductor discrete device according to claim 6, it is characterized in that, in step e, before epi-layer surface is carried out the contact hole trench erosion, precipitate layer of oxide layer earlier, then oxide layer is carried out dry corrosion, remove the oxide layer in the inter-level dielectric perforate, expose the epitaxial loayer in the perforate; Etching contact hole groove afterwards.
9. a kind of method for preparing the trench semiconductor discrete device according to claim 6, it is characterized in that, in step e, the width of contact hole mask perforate is not all equally big or small, before etching contact hole groove, the precipitation layer of oxide layer is also sealed up at least one the contact hole mask perforate in inter-level dielectric earlier, then oxide layer is carried out dry corrosion, dispose the oxide layer in the contact hole perforate of not sealed up, expose the epitaxial loayer in the perforate; Etching contact hole groove injects P type high dopant to the contact hole groove afterwards then.
10. a method for preparing the trench semiconductor discrete device is characterized in that, may further comprise the steps:
(1) utilizes trench mask that the epitaxial loayer on the substrate 10 200 is injected P type dopants and form P type bases, and on epitaxial loayer, corrode and form a plurality of gate trenchs;
(2) utilize active region mask to form the source region;
(3) at epi-layer surface deposition inter-level dielectric, utilize contact hole mask to form the contact hole groove again, and the contact hole groove is carried out metal plug fill;
(4) at the upper surface depositing metal layers of device, utilize metal mask to carry out metal attack, form metal bed course and line.
11. a kind of method for preparing the trench semiconductor discrete device according to claim 10 is characterized in that, described step (1) may further comprise the steps:
A, on epitaxial loayer the formation oxide layer, accumulation lithography coating on oxide layer, expose the partial oxidation layer by trench mask again, the partial oxidation layer that exposes is carried out dry corrosion, until exposing epitaxial loayer, be formed on a plurality of trench mask perforates on the oxide layer, the trench mask aperture widths is different, width range wherein is 0.2um to 2.0um, disposes lithography coating then;
B, P type dopant is injected on the surface, the part that has former oxide layer to cover is not injected into, the part that does not have former oxide layer to cover, P type dopant can be injected on the epi-layer surface, and by a High temperature diffusion operation propelling of P type dopant is diffused into formation P type base in the epitaxial loayer;
C, form groove by being etched in tapping, this groove passes P type base and extends in the epitaxial loayer, to the oxidation of groove sacrifice property, disposes all oxide layers then;
D, in sidewall and bottom that groove is exposing, and the upper surface of epitaxial loayer forms grid oxic horizon, the polysilicon of deposition N type high dopant in groove again is with filling groove and cover end face;
E, the polysilicon layer on epi-layer surface is carried out plane corrosion treatment or chemico-mechanical polishing.
12. the preparation method of trench semiconductor power discrete device according to claim 11, it is characterized in that, in step c, before etching groove, the precipitation layer of oxide layer is also sealed up at least one the trench mask perforate in oxide layer earlier, then oxide layer is carried out dry corrosion, removes the oxide layer in the perforate, expose the epitaxial loayer in the perforate, afterwards etching groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210019197.4A CN103219241B (en) | 2012-01-19 | 2012-01-19 | A kind of method preparing groove discrete semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210019197.4A CN103219241B (en) | 2012-01-19 | 2012-01-19 | A kind of method preparing groove discrete semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103219241A true CN103219241A (en) | 2013-07-24 |
| CN103219241B CN103219241B (en) | 2016-06-22 |
Family
ID=48816926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210019197.4A Expired - Fee Related CN103219241B (en) | 2012-01-19 | 2012-01-19 | A kind of method preparing groove discrete semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103219241B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104008971A (en) * | 2014-01-13 | 2014-08-27 | 佛山芯光半导体有限公司 | Trenched IGBT device process for improving anti-short-circuit ability of devices |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281547B1 (en) * | 1997-05-08 | 2001-08-28 | Megamos Corporation | Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask |
| US20020081795A1 (en) * | 2000-12-27 | 2002-06-27 | Jong-Dae Kim | Method for manufacturing trench-gate type power semiconductor device |
| CN101777514A (en) * | 2010-02-03 | 2010-07-14 | 香港商莫斯飞特半导体有限公司 | A kind of trench semiconductor power device and preparation method thereof |
| CN101834142A (en) * | 2010-05-21 | 2010-09-15 | 香港商莫斯飞特半导体有限公司 | A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof |
| CN101901765A (en) * | 2009-03-17 | 2010-12-01 | 三菱电机株式会社 | Method of manufacturing power semiconductor device |
| CN101997030A (en) * | 2009-08-17 | 2011-03-30 | 力士科技股份有限公司 | Trench metal-oxide-semiconductor field effect transistor (MOSFET) with shallow trench structure and manufacturing method thereof |
-
2012
- 2012-01-19 CN CN201210019197.4A patent/CN103219241B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281547B1 (en) * | 1997-05-08 | 2001-08-28 | Megamos Corporation | Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask |
| US20020081795A1 (en) * | 2000-12-27 | 2002-06-27 | Jong-Dae Kim | Method for manufacturing trench-gate type power semiconductor device |
| CN101901765A (en) * | 2009-03-17 | 2010-12-01 | 三菱电机株式会社 | Method of manufacturing power semiconductor device |
| CN101997030A (en) * | 2009-08-17 | 2011-03-30 | 力士科技股份有限公司 | Trench metal-oxide-semiconductor field effect transistor (MOSFET) with shallow trench structure and manufacturing method thereof |
| CN101777514A (en) * | 2010-02-03 | 2010-07-14 | 香港商莫斯飞特半导体有限公司 | A kind of trench semiconductor power device and preparation method thereof |
| CN101834142A (en) * | 2010-05-21 | 2010-09-15 | 香港商莫斯飞特半导体有限公司 | A kind of have the groove of heavy insulation bottom and a manufacture method of semiconductor device thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104008971A (en) * | 2014-01-13 | 2014-08-27 | 佛山芯光半导体有限公司 | Trenched IGBT device process for improving anti-short-circuit ability of devices |
| CN104008971B (en) * | 2014-01-13 | 2017-05-03 | 佛山芯光半导体有限公司 | Trenched IGBT process for improving anti-short-circuit ability of devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103219241B (en) | 2016-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101777514B (en) | Trench semiconductor power device and preparation method thereof | |
| CN101834142B (en) | Method for manufacturing flute with thick insulating bottom and semiconductor device thereof | |
| CN106463504A (en) | Semiconductor device and method for producing semiconductor device | |
| CN103632964A (en) | Method of preparing groove semiconductor power device | |
| CN1364315A (en) | High cell density power rectifier | |
| CN108091573A (en) | Shield grid groove MOSFET ESD structures and its manufacturing method | |
| CN102789987A (en) | Method for manufacturing super junction power transistor with low miller capacitance | |
| CN103187288A (en) | Preparation method of groove semiconductor power device with static protection function | |
| CN108447911A (en) | A kind of depth groove semiconductor power device and preparation method thereof | |
| CN107887256A (en) | The method for forming electronic device | |
| CN113053738A (en) | Split gate type groove MOS device and preparation method thereof | |
| CN101246886B (en) | Power transistor with MOS structure and production method thereof | |
| CN102544005B (en) | Power assembly for reducing conduction of parasitic transistor and manufacturing method thereof | |
| CN103730493A (en) | Structure of semiconductor power device | |
| CN103632965A (en) | Method of preparing a groove grid-control power device | |
| CN103839999A (en) | Structure and preparation method of power field effect transistor | |
| CN102496568A (en) | Method for manufacturing trench power device structure | |
| CN102496573A (en) | Manufacturing method of trench IGBT | |
| CN103187291B (en) | A kind of method preparing trench semiconductor power discrete device | |
| CN103219241A (en) | Method of preparing groove discrete semiconductor device | |
| CN108417637A (en) | A kind of more groove semiconductor power devices and preparation method thereof | |
| CN103187292B (en) | A kind of method manufacturing trench semiconductor power device | |
| CN103187281A (en) | Preparation method of trench semiconductor power discrete device | |
| CN103632963A (en) | Method of preparing groove grid-control semiconductor power device | |
| CN103187287B (en) | A kind of preparation method of groove discrete semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160622 Termination date: 20210119 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |