CN106887465A - The preparation method of groove type double-layer gate MOSFET - Google Patents
The preparation method of groove type double-layer gate MOSFET Download PDFInfo
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- CN106887465A CN106887465A CN201710004146.7A CN201710004146A CN106887465A CN 106887465 A CN106887465 A CN 106887465A CN 201710004146 A CN201710004146 A CN 201710004146A CN 106887465 A CN106887465 A CN 106887465A
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- layer
- film
- silicon
- oxide
- source polysilicon
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000003628 erosive effect Effects 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention discloses a kind of preparation method of groove type double-layer gate MOSFET, step includes：1) etching groove, the channeled layer for growing ONO structure connects film；2) source polysilicon is grown, it is counter to be etched to groove upper surface；3) source polysilicon exit is protected with photoresist, anti-carves the source polysilicon of erosion compact district；4) removal channeled layer connects the remaining outer oxide silicon fiml that portion outer layer silicon oxide film in film, photoresist, channeled layer are connect in film successively；5) oxide layer between growing polycrystalline silicon；6) removal channeled layer connects the silicon nitride film and internal layer silicon oxide film in film；7) grid oxic horizon, grid polycrystalline silicon are grown successively, and anti-carves erosion grid polycrystalline silicon, complete the making of device.The present invention connects the amount of oxidation that film removes technique and reduction source polysilicon by optimizing channeled layer, improves IPO layers of pattern of source polysilicon exit, solves the problems, such as that grid polycrystalline silicon is remained, so as to eliminate grid to the electric leakage hidden danger of source electrode.
Description
Technical field
It is to be related to (the golden oxygen oxidation of groove type double-layer gate MOSFET specifically the present invention relates to IC manufacturing field
The making of thing semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor)
Method.
Background technology
The compact district (Cell area) of existing 100V groove type double-layer grids (Split Gate) MOSFET element and source electrode
Structure, the pattern of polysilicon exit (Source poly linkup area) are as shown in figure 1, groove lower floor is source electrode polycrystalline
Silicon, upper strata is grid polycrystalline silicon, and trenched side-wall connects film (TCH liner) for channeled layer, and it is ONO (oxidations that the channeled layer connects film
Silicon fiml-silicon nitride film-silicon oxide film) structure is IPO layers of (inter- between grid polycrystalline silicon and source polysilicon
Polysilicon oxide, the oxide layer of inter polysilicon), described IPO layers is formed by aoxidizing source polysilicon.
The thickness requirement of film is connect due to the channeled layer in convention trench type bilayer grid MOSFET component structureI.e. to IPO
The oxide thickness requirement of layer is sufficiently thick, and this causes the pattern of source polysilicon uncontrollable, shown in (b) in such as Fig. 1, source electrode polycrystalline
Silicon top is more steep, and the degree of crook of IPO layers of top both sides is larger (dotted line irises out part in figure), causes source polysilicon to draw
Go out end and usually have grid polycrystalline silicon residual, so as to trigger grid to the electric leakage of source electrode, produce the hidden danger of short circuit current.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method of groove type double-layer gate MOSFET, and it can change
The pattern of IPO layers of kind source polysilicon exit, it is to avoid grid polycrystalline silicon remains in source polysilicon exit.
In order to solve the above technical problems, the preparation method of groove type double-layer gate MOSFET of the invention, comprises the following steps：
1) etching forms groove on a silicon substrate, and growth channeled layer connects film in groove；The channeled layer connects the film of film
Rotating fields are oxide-nitride-oxide；
2) source polysilicon is grown, and anti-carves erosion source polysilicon to groove upper surface；
3) protecting source polysilicon exit, the source polysilicon to compact district with photoresist carries out anti-carving erosion；
4) removal channeled layer connects portion outer layer silicon oxide film, the photoetching of protection source polysilicon exit in film successively
Glue, channeled layer connect the remaining outer oxide silicon fiml in film；
5) oxide layer between growing polycrystalline silicon above source polysilicon；
6) removal channeled layer connects the silicon nitride film and internal layer silicon oxide film in film；
7) grid oxic horizon, grid polycrystalline silicon are grown successively, and grid polycrystalline silicon is carried out to anti-carve erosion；Subsequently according to tradition
Technological process completes the making of groove type double-layer gate MOSFET.
Step 1), the channeled layer is connect in film, and the thickness of internal layer silicon oxide film isIntermediate layer silicon nitride film
Thickness beThe thickness of outer oxide silicon fiml is
Step 2), it is possible to use wavelength detection etching terminal.
Step 3), can control to anti-carve the etch amount of erosion by controlling etch period.Preferably, after the completion of anti-carving erosion,
The height of remaining source polysilicon is lower than the height at groove upper surface monocrystalline silicon bottom 1 micron.
Step 4), the thickness of the portion outer layer silicon oxide film is
Step 5), thermal oxidation process can be used.The thickness of the oxide layer of the inter polysilicon is
Step 7), the thickness of grid oxic horizon isIt is counter to etch into monocrystalline silicon surface.
Fabrication processing by improving groove type double-layer gate MOSFET of the invention, optimization channeled layer connects film removal work
Skill, and the amount of oxidation of source polysilicon is reduced, IPO layers of source polysilicon exit of pattern is improved, solve grid many
The problem of crystal silicon residual, so as to avoid grid to the electric leakage of source electrode, eliminates the hidden danger of MOSFET element short circuit current.
Brief description of the drawings
Fig. 1 is compact district and the structure and topography scan of source polysilicon exit of existing groove type double-layer gate MOSFET
Electron microscope.Wherein, (a) figure is compact district, and (b) figure is source polysilicon exit.
The device architecture schematic diagram obtained after the completion of the step of Fig. 2 is the embodiment of the present invention 3.
The device architecture and the scanning electron microscope (SEM) photograph of pattern obtained after the completion of the step of Fig. 3 is the embodiment of the present invention 3.
The device architecture and the scanning electron microscope (SEM) photograph of pattern obtained after the completion of the step of Fig. 4 is the embodiment of the present invention 7.Wherein,
A () figure is compact district, (b) figure is source polysilicon exit.
The device architecture and the scanning electron microscope (SEM) photograph of pattern obtained after the completion of the step of Fig. 5 is the embodiment of the present invention 11.Wherein,
A () figure is compact district, (b) figure is source polysilicon exit.
Fig. 6 be the embodiment of the present invention groove type double-layer grid MOSFET component be ultimately produced after structure and pattern
Scanning electron microscope (SEM) photograph.
Description of reference numerals is as follows in figure
1：Source polysilicon
2：Grid polycrystalline silicon
3：The oxide layer (IPO) of inter polysilicon
4：Channeled layer connects film
5：Grid polycrystalline silicon is remained
6：Grid oxic horizon
7：Contact hole
Specific embodiment
It is have more specifically to understand to technology contents of the invention, feature and effect, in conjunction with the drawings and specific embodiments,
Technical scheme is further described in detail.
The preparation method of groove type double-layer gate MOSFET of the invention, its specific fabrication processing comprises the following steps：
Step 1, forms groove by etching on a silicon substrate.
Step 2, the channeled layer of boiler tube growth ONO (oxide-nitride-oxide) structure connects film in groove.The ditch
Groove layer is connect in film, and the thickness of internal layer silicon oxide film isThe thickness of intermediate layer silicon nitride film isOutward
Layer silicon oxide film thickness be
Step 3, grows source polysilicon, and anti-carves erosion (dry etching) source polysilicon to groove upper surface, using ripple
Detecting etching end point (EPD) long, as shown in Figure 2,3.
Step 4, protects source polysilicon exit with photoresist, the source polysilicon of compact district is carried out anti-carving erosion and (is done
Method is etched), etch amount is controlled by controlling etch period.In the present embodiment, anti-carve after the completion of erosion, remaining source electrode is more
The height of crystal silicon is lower than the height of groove upper surface monocrystalline substrate 1 micron.
Step 5, removal channeled layer connects the portion outer layer oxide-film in film (i.e. away from that layer of silicon oxide film of trenched side-wall).
The thickness of the outer oxide film of this step removal is about
Step 6, the photoresist of dry or wet removal protection source polysilicon exit.
Step 7, wet etching removal channeled layer connects the remaining outer oxide film in film.After the completion of this step, obtain such as Fig. 4
Shown structure.
Step 8, by thermal oxidation process, forms thickness above source polysiliconInter polysilicon
Oxide layer (IPO).
Step 9, wet etching removal channeled layer connects silicon nitride film and the internal layer silicon oxide film (oxygen i.e. on trench wall in film
SiClx film).
Step 10, growth thickness isGrid oxic horizon.Source polysilicon exit is due to source polysilicon
, beyond the depth of groove, therefore grid oxic horizon is only grown on the monocrystalline silicon of flute surfaces for height with IPO layers.
Step 11, grow grid polycrystalline silicon, and it is counter etch into monocrystalline silicon surface (dry etching, it is automatic by End point
Control etching terminal).After the completion of this step, structure as shown in Figure 5 is obtained.
Fig. 5 and Fig. 1 are compared and be can see, the groove type double-layer gate MOSFET that the present invention makes, its source electrode polycrystalline
Silicon top is gentle, and preferably, source polysilicon exit does not have grid polycrystalline silicon to remain to severity control.
Follow-up traditional manufacturing technique flow (including the injection of Base injection, source class, contact hole, metal company according to MOSFET
Connect the techniques such as layer, surface passivation layer) techniques such as the etching of contact hole are completed, ultimately form structure as shown in Figure 6.
Claims (9)
1. the preparation method of groove type double-layer gate MOSFET, it is characterised in that comprise the following steps：
1) etching forms groove on a silicon substrate, and growth channeled layer connects film in groove；The channeled layer connects the film layer knot of film
Structure is oxide-nitride-oxide；
2) source polysilicon is grown, and anti-carves erosion source polysilicon to groove upper surface；
3) protecting source polysilicon exit, the source polysilicon to compact district with photoresist carries out anti-carving erosion；
4) removal channeled layer connects portion outer layer silicon oxide film, photoresist, the ditch of protection source polysilicon exit in film successively
Groove layer connects the remaining outer oxide silicon fiml in film；
5) oxide layer between growing polycrystalline silicon above source polysilicon；
6) removal channeled layer connects the silicon nitride film and internal layer silicon oxide film in film；
7) grid oxic horizon, grid polycrystalline silicon are grown successively, and grid polycrystalline silicon is carried out to anti-carve erosion；Subsequently traditionally
Flow completes the making of groove type double-layer gate MOSFET.
2. method according to claim 1, it is characterised in that step 1), the channeled layer is connect in film, internal layer silicon oxide film
Thickness beThe thickness of intermediate layer silicon nitride film isThe thickness of outer oxide silicon fiml is
3. method according to claim 1, it is characterised in that step 2), using wavelength detection etching terminal.
4. method according to claim 1, it is characterised in that step 3), after the completion of anti-carving erosion, remaining source polysilicon
Height is lower than the height at groove upper surface monocrystalline silicon bottom 1 micron.
5. method according to claim 1, it is characterised in that step 4), the thickness of the portion outer layer silicon oxide film is
6. method according to claim 1, it is characterised in that step 5), using thermal oxidation process.
7. method according to claim 1, it is characterised in that step 5), the thickness of the oxide layer of the inter polysilicon is
8. method according to claim 1, it is characterised in that step 7), the thickness of grid oxic horizon is
9. method according to claim 1, it is characterised in that step 7), it is counter to etch into monocrystalline silicon surface.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710004146.7A CN106887465B (en) | 2017-01-04 | 2017-01-04 | manufacturing method of trench type double-layer gate MOSFET |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710004146.7A CN106887465B (en) | 2017-01-04 | 2017-01-04 | manufacturing method of trench type double-layer gate MOSFET |
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| Publication Number | Publication Date |
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| CN106887465A true CN106887465A (en) | 2017-06-23 |
| CN106887465B CN106887465B (en) | 2019-12-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111276394A (en) * | 2020-02-18 | 2020-06-12 | 捷捷微电(上海)科技有限公司 | Manufacturing method of split gate MOSFET |
| CN113223933A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for removing polysilicon residue in power device manufacturing process and power device thereof |
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| CN102005377A (en) * | 2009-08-31 | 2011-04-06 | 万国半导体股份有限公司 | Fabrication of trench DMOS device having thick bottom shielding oxide |
| CN102097323A (en) * | 2009-12-09 | 2011-06-15 | 半导体元件工业有限责任公司 | Method of forming an insulated gate field effect transistor device having a shield electrode structure |
| CN102856182A (en) * | 2011-06-27 | 2013-01-02 | 半导体元件工业有限责任公司 | Method of making an insulated gate semiconductor device and structure |
| CN103887342A (en) * | 2014-04-10 | 2014-06-25 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET and manufacturing method thereof |
| CN105225935A (en) * | 2015-09-22 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | There is trench gate structure and the manufacture method thereof of shield grid |
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2017
- 2017-01-04 CN CN201710004146.7A patent/CN106887465B/en active Active
Patent Citations (6)
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| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| CN102005377A (en) * | 2009-08-31 | 2011-04-06 | 万国半导体股份有限公司 | Fabrication of trench DMOS device having thick bottom shielding oxide |
| CN102097323A (en) * | 2009-12-09 | 2011-06-15 | 半导体元件工业有限责任公司 | Method of forming an insulated gate field effect transistor device having a shield electrode structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111276394A (en) * | 2020-02-18 | 2020-06-12 | 捷捷微电(上海)科技有限公司 | Manufacturing method of split gate MOSFET |
| CN111276394B (en) * | 2020-02-18 | 2022-09-23 | 捷捷微电(上海)科技有限公司 | Manufacturing method of split gate MOSFET |
| CN113223933A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for removing polysilicon residue in power device manufacturing process and power device thereof |
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| Publication number | Publication date |
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| CN106887465B (en) | 2019-12-10 |
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