CN114256077A - Method for manufacturing low-voltage separation gate groove MOS device - Google Patents
Method for manufacturing low-voltage separation gate groove MOS device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
A manufacturing method of a low-voltage separation gate groove MOS device comprises the steps of forming an epitaxial layer on a substrate, etching the epitaxial layer to form a groove, forming first field oxide layers on the side face and the bottom of the groove, depositing a side wall protection layer on the side wall surface of the first field oxide layer, and depositing a second thickness oxide layer with preset thickness on the bottom surface of the first field oxide layer. Because the height of the bottom of the side wall protection layer from the bottom of the groove can be controlled, a second thickness oxidation layer with preset thickness can be deposited on the bottom surface of the first field oxidation layer, so that the field oxidation layer at the bottom of the groove comprises two layers of the first field oxidation layer and the second thickness oxidation layer, namely the thickness of the field oxidation layer at the bottom of the shielding grid can be controlled and adjusted according to the actual requirement of the device, the electric field intensity of the device can be optimized to the optimal value, the on-resistance of the device can be improved, and the electrical performance of the device can be improved.
Description
Technical Field
The invention relates to the field of power semiconductor device manufacturing, in particular to a manufacturing method of a low-voltage separation gate groove MOS device.
Background
Because of the charge-coupled effect, the MOS device with the SGT (split-gate-trench) structure can obtain a higher breakdown voltage under the condition of adopting the same epitaxial specification with the same doping concentration.
The structure utilizes a shield gate electrode to shield the capacitive coupling between the control gate electrode and the device epitaxial layer for reducing gate-drain parasitic capacitance. The split-gate trench MOS device has lower gate charge, and meanwhile, the on-resistance is not degraded, thereby being beneficial to improving the switching characteristic and the working efficiency of a power management system. According to the structure, the charge coupling is realized by growing a thicker oxide layer of the shielding grid electrode on the inner wall of the deep groove, so that the source-drain breakdown voltage of the structure is controlled by the thickness of the oxide layer of the shielding grid electrode, and the higher the breakdown voltage is, the thicker the oxide layer is required to be. In the low-voltage split gate device, the thickness of the oxide layer on the side wall of the shielding gate is limited, so that the oxide layer at the bottom and the corner of the shielding gate is always relatively thin, and the device is more easily broken down due to overlarge electric field. Meanwhile, if the low-voltage split gate device is required to have a higher breakdown voltage, an oxide layer with a proper thickness at the bottom of the shielding grid electrode is required to ensure a lower electric field intensity, so that the device with the on-resistance meeting the requirement is obtained.
However, the method is limited by the limitation of the oxidation process, and the relative thickness of the oxide layer at the bottom and the corner of the trench cannot be controlled due to the difference of the crystal orientation in the trench, so that the electrical performance of the device is difficult to improve.
Disclosure of Invention
The invention mainly solves the technical problem of providing a manufacturing method of a low-voltage separation gate groove MOS device, so that the formed low-voltage separation gate groove MOS device has better electrical performance.
According to a first aspect, an embodiment provides a method for manufacturing a split gate trench MOS device, including the steps of:
forming an epitaxial layer on a substrate, and etching the epitaxial layer to form a groove;
forming a first field oxide layer on the side surface and the bottom of the groove;
depositing a side wall protection layer on the surface of the side wall of the first field oxide layer, and then depositing a second thickness oxide layer with a preset thickness on the surface of the bottom of the first field oxide layer;
depositing a first layer of polycrystalline silicon to fill the groove, and etching back the first layer of polycrystalline silicon to form a shielding gate positioned in the groove;
removing the side wall protective layer and the trench oxide layer on the side surface of the trench above the shielding gate, and only keeping the side wall protective layer and the trench oxide layer on the side surface of the shielding gate and the trench oxide layer and the second thickness oxide layer at the bottom of the shielding gate;
forming an isolation dielectric layer above the shielding gate;
forming a gate oxide layer on the side surface of the groove above the isolation medium layer;
depositing a second layer of polycrystalline silicon on the isolation medium layer to fill the groove, and etching back the second layer of polycrystalline silicon to form a control gate;
and sequentially forming a body junction injection layer, a source electrode injection layer, an interlayer dielectric layer, a tungsten plug and surface metal to form the MOS device.
Optionally, the etching to form the trench in the epitaxial layer includes:
forming a trench etching mask layer on the upper surface of the epitaxial layer, coating a photoresist, exposing and developing to define a trench area;
and etching the groove region by adopting a dry etching process to form a groove, and removing the light resistance and the groove etching mask layer.
Optionally, the dry etching process is controlled so that the area of the top of the trench is larger than the area of the bottom of the trench, and an included angle between the side surface of the trench and the bottom surface of the trench is 87 ° to 89 °.
Optionally, depositing a sidewall protection layer on the sidewall surface of the first field oxide layer, and depositing a second thickness oxide layer with a preset thickness on the bottom surface of the first field oxide layer, including:
depositing a protective layer on the surface of the first field oxide layer;
etching the protective layer at the bottom of the groove, and reserving the protective layer on the side face of the groove as the side wall protective layer;
and continuously growing a second oxide layer in the groove by using a furnace tube process, so that the second oxide layer at the bottom of the groove and the corner from the bottom of the groove to the side part is thickened to form a second oxide layer with a preset thickness.
Optionally, the protective layer is silicon nitride, and the thickness of the protective layer is 0.1 μm to 0.3 μm; the second oxide layer is silicon oxide or thallium oxide.
Optionally, the first field oxide layer is silicon oxide.
Optionally, forming an isolation dielectric layer above the shield gate includes:
covering a high-density plasma dielectric layer on the surface of the shielding grid and the side face of the groove by using a chemical vapor deposition method, wherein the high-density plasma dielectric layer extends to the surface of an epitaxial layer outside the groove;
carrying out surface treatment on the high-density plasma dielectric layer on the surface of the epitaxial layer by using a chemical mechanical polishing process, and removing the high-density plasma dielectric layer on the surface of the epitaxial layer;
and etching and reserving the high-density plasma dielectric layer with partial thickness by using a wet process to form an isolation dielectric layer between the shielding gate and the control gate.
Optionally, the thickness of the isolation dielectric layer is 0.2 μm to 0.4 μm.
Optionally, before forming the gate oxide layer on the side surface of the trench above the isolation dielectric layer, the method further includes:
and growing a sacrificial layer on the side surface and the bottom surface of the groove above the isolation dielectric layer, and removing the sacrificial layer by using a wet process.
Optionally, etching back the second layer of polysilicon to form a control gate, including:
and depositing the highly doped polysilicon by using a furnace tube process, and etching back to 1000 mu m below the surface of the epitaxial layer to form a control gate.
According to the manufacturing method of the low-voltage separation gate trench MOS device, the side wall protection layer is formed on the surface of the first field oxide layer on the surface of the side wall of the trench, and the height from the bottom of the side wall protection layer to the bottom of the trench can be controlled, so that the second thickness oxide layer with the preset thickness can be deposited on the surface of the bottom of the first field oxide layer, and the field oxide layer at the bottom of the trench comprises the first field oxide layer and the second thickness oxide layer, namely, the thickness of the field oxide layer at the bottom of the shielding gate can be controlled and adjusted according to the actual requirements of the device, the electric field intensity of the device can be optimized to the optimal value, the on resistance of the device can be improved, and the electrical performance of the device can be improved.
Drawings
Fig. 1 is a schematic flow chart of a manufacturing method according to an embodiment of the invention;
FIG. 2 is a cross-sectional view of a middle stage of a manufacturing process according to an embodiment of the present invention;
FIG. 3 is a second schematic cross-sectional view illustrating a middle stage of a manufacturing process according to an embodiment of the present invention;
FIG. 4 is a third schematic cross-sectional view of a middle stage of a manufacturing process according to an embodiment of the present invention;
FIG. 5 is a fourth schematic cross-sectional view illustrating a middle stage of a manufacturing process according to an embodiment of the present invention;
FIG. 6 is a fifth schematic cross-sectional view of a middle stage of a manufacturing process according to an embodiment of the present invention;
FIG. 7 is a sixth schematic cross-sectional view of a middle stage of a fabrication process according to an embodiment of the present invention;
FIG. 8 is a seventh schematic cross-sectional view of a middle stage of a fabrication process according to an embodiment of the present invention;
FIG. 9 is an eighth schematic cross-sectional view taken at a mid-stage of a fabrication process in accordance with an embodiment of the present invention;
FIG. 10 is a ninth schematic cross-sectional view illustrating a middle stage of a manufacturing process according to one embodiment of the present invention;
FIG. 11 is a cross-sectional view of a middle stage of a fabrication process according to one embodiment of the present invention;
FIG. 12 is an eleventh schematic cross-sectional view taken at a mid-stage of a fabrication process according to an embodiment of the present invention;
FIG. 13 is a twelfth schematic cross-sectional view taken in a middle stage of a fabrication process in accordance with an embodiment of the present invention;
FIG. 14 is a thirteen schematic cross-sectional view taken at a middle stage of a fabrication process according to an embodiment of the present invention;
FIG. 15 is a fourteenth cross-sectional view illustrating a middle stage of a manufacturing process in accordance with one embodiment of the present invention;
FIG. 16 is a fifteen-stage schematic cross-sectional view of a middle portion of a fabrication process in accordance with an embodiment of the present invention;
FIG. 17 is a cross-sectional view of a sixteenth embodiment of a mid-stage fabrication process according to the present invention;
FIG. 18 is a seventeenth schematic cross-sectional view illustrating a middle stage of a manufacturing process according to an embodiment of the present invention;
FIG. 19 is an eighteen schematic cross-sectional view of a middle stage of a fabrication process according to one embodiment of the present invention;
FIG. 20 is a nineteen schematic cross-sectional view taken at a mid-stage of a fabrication process in accordance with an embodiment of the present invention;
fig. 21 is a schematic diagram of a low-voltage split-gate trench MOS device according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As can be seen from the background, the MOS device with SGT structure has a problem of thin oxide layer at the bottom and corner of the trench due to the limitation of the current oxidation process.
Through analysis, the problem that the oxide layers at the bottom and the corner of the trench of the MOS device with the SGT structure are thin at present cannot be solved by depositing the oxide layers at the bottom and the corner for multiple times, and because the angle of the corner at the bottom of the trench is related to the warpage of a chip, the warpage of the whole wafer is poor, and the in-plane uniformity of the device can be influenced. That is, if the angles of the bottom and the corner of the trench cannot be guaranteed, the subsequent fabrication is difficult, and even the chip is scrapped. In the embodiment of the invention, the first field oxide layer is formed on the side surface and the bottom of the trench, the side wall protective layer is deposited on the side wall surface of the first field oxide layer, the second thickness oxide layer with the preset thickness is deposited on the bottom surface of the first field oxide layer, so that the thickness of the field oxide layer at the bottom of the trench comprises the sum of the first field oxide layer and the second thickness oxide layer, and the thickness of the field oxide layer at the bottom of the shielding gate can be controlled and adjusted according to the actual requirement of the device, so that the electric field intensity of the device can be optimized to the optimal value, the on-resistance of the device can be improved, and the electrical performance of the device can be improved.
Referring to fig. 1, the present embodiment provides a method for manufacturing a split gate trench MOS device, including:
step 1, an epitaxial layer 100 is formed on a substrate, and trenches are etched in the epitaxial layer 100.
Referring to fig. 2, 3 and 4 in combination, the etching of the trenches in the epitaxial layer includes the steps of:
a trench etching mask layer 200 is formed on the upper surface of the epitaxial layer 100, and then a photoresist is coated, exposed and developed to define a trench region 201, that is, a patterned mask layer is formed, and the patterned mask layer having the trench region 201 is used as a mask to perform etching to form a trench 300.
The trench etch mask layer 200 may be silicon oxide and may have a thickness of 0.5 μm to 1.5 μm.
In this embodiment, a dry etching process is used to etch the trench region 201 to form a trench 300, and after etching, the photoresist and the trench etching mask layer 200 are removed. The depth of the groove can control the dry etching process according to the requirements of the device, and the depth of the groove is different along with the change of the withstand voltage, so the depth of the groove can be etched according to the withstand voltage requirements of the device. The area of the top of the groove is larger than that of the bottom, so that the included angle a between the side surface and the bottom surface of the groove is 87-89 degrees. When the shape of the groove is wide at the top and narrow at the bottom, and the included angle between the side surface and the bottom surface is 87-89 degrees, the subsequent filling of the shielding grid is facilitated, gaps among multiple layers of materials are avoided, and the filling of the shielding grid is more compact.
And 2, forming a first field oxide layer on the side surface and the bottom of the groove.
Referring to fig. 5, in the present embodiment, a first field oxide layer 400 is deposited on the surface of the trench by using a furnace process, and the first field oxide layer 400 may be silicon oxide or chromium oxide. The first field oxide layer 400 covers the bottom and sides of the trench 300 and the upper surface of the epitaxial layer 100.
And 3, depositing a side wall protection layer on the side wall surface of the first field oxide layer, and then depositing a second thickness oxide layer with a preset thickness on the bottom surface of the first field oxide layer.
In this embodiment, the step of depositing a sidewall protection layer on the sidewall surface of the first field oxide layer includes:
referring to fig. 5, a passivation layer 500 is deposited on the surface of the first field oxide layer 400, wherein the passivation layer 500 is silicon nitride and has a thickness of 0.1 μm to 0.3 μm.
Referring to fig. 6, the passivation layer on the bottom of the trench and on the epitaxial layer is etched away, and the passivation layer on the side of the trench is used as the sidewall protection layer 501.
It can be understood that, after the protective layer at the bottom of the trench is etched, the first field oxide layer at the bottom may be etched, so as to facilitate the development of a subsequent process for depositing an oxide layer (second thickness oxide layer) with a preset thickness again at the bottom, facilitate the thickness control, avoid the problem of a gap formed by the two oxide layers, and improve the uniformity of the device.
Referring to fig. 7, a furnace process is used to continue growing a second oxide layer, which is silicon oxide or thallium oxide, in the trench 300, so that the second oxide layer at the bottom of the trench and at the corners from the bottom to the sides of the trench is thickened, thereby forming a second oxide layer 402 with a predetermined thickness.
In this embodiment, by manufacturing the sidewall protection layer 501, the first field oxide layer 400 on the outer side of the shielding polysilicon can be protected, so that the first field oxide layer 400 on the sidewall is prevented from being etched when the first field oxide layer 400 at the bottom of the etching is etched, and the breakdown voltage of the device can be ensured by ensuring the thickness of the first field oxide layer on the sidewall. When the second oxide layer is further grown, the thickness of the second oxide layer at the bottom and the corner can be met, and the thickness of the second oxide layer can be adjusted according to requirements, so that the electric field intensity can be reduced, the electric field intensity is optimized, the on-resistance of the device is improved, and the electrical property of the device is improved.
It can be understood that the thickness of the bottom second thickness oxide layer 402 can be controlled by controlling the bottom etching height of the sidewall protection layer through the above method, and the adjustment of the thickness of the bottom second thickness oxide layer 402 is more free, so that the reduction of the electric field intensity can be flexibly controlled, and the optimization purpose is achieved. For example, if it is desired to make the second thickness oxide layer 402 thicker, the bottom protective layer may be etched more, so that the first field oxide layer higher from the bottom is not protected, and thus the second field oxide layer may be deposited at a position below the bottom of the sidewall protective layer, so that the second field oxide layer at the bottom and the corner is thicker.
In this embodiment, the second oxide layer is made of silicon oxide or chromium oxide, that is, the second thickness oxide layer 402 is made of silicon oxide or chromium oxide; the material of the protection layer 500 is silicon nitride, i.e., the material of the sidewall protection layer 501 is silicon nitride.
And 4, depositing a first layer of polysilicon to fill the groove, and etching back the first layer of polysilicon to form a shield gate 601 positioned in the groove.
Referring to fig. 8 and 9, the first polysilicon layer covers the trench, and then the surface of the epitaxial layer 100 and the first polysilicon layer above the trench may be etched away by a process to form a shield gate 601.
And 5, removing the side wall protective layer and the trench oxide layer on the side surface of the trench above the shield gate 601, and only keeping the side wall protective layer and the trench oxide layer on the side surface of the shield gate 601 and the trench oxide layer and the second thickness oxide layer at the bottom of the shield gate 601.
Referring to fig. 10, the sidewall protection layer on the side surface of the trench above the shield gate 601 is removed, and the sidewall protection layer may be etched away by removing the sidewall protection layer in a certain area above the shield gate 601 through an etching technique of dry etching; then, the trench oxide layer exposed in a certain region above the shield gate 601 is etched by using an etching technique of wet etching, and the actual etching solution may include an HF solution.
In this embodiment, a plasma etching apparatus may be used to etch the sidewall protection layer, and a 901E/903E TEGAL plasma etching system type plasma etching apparatus may be used, where the etching gas used may be: CF4, O2, N2, SF6, CHF3, NF3, He, C2F6, and the like.
And 6, forming an isolation dielectric layer above the shielding gate.
Referring to fig. 11, 12 and 13 in combination, an isolation dielectric layer is formed over the shield gate, including the steps of:
referring to fig. 11, a high density plasma dielectric layer 700 is deposited on the surface of the shield polysilicon 601 and the side surfaces of the trench by chemical vapor deposition, wherein the high density plasma dielectric layer 700 extends to the surface of the epitaxial layer 100 outside the trench.
The isolation dielectric layer 701 in this embodiment is made of silicon oxide, silicon dioxide, or the like, and the high-density plasma dielectric layer 700 deposited by using the chemical vapor deposition method is more compact and has better performance, so that the thickness of the high-density plasma dielectric layer can be better controlled.
Referring to fig. 12, the high-density plasma medium layer on the surface of the epitaxial layer 100 is surface-treated by using a chemical mechanical polishing process to remove the high-density plasma medium layer on the surface of the epitaxial layer.
As shown in fig. 13, a wet process is used to etch and retain a portion of the thickness of the high density plasma dielectric layer, forming an isolation dielectric layer 701 between the shield gate and the control gate. The thickness of the isolation dielectric layer is kept to be 0.2-0.4 μm.
And 7, forming a gate oxide layer on the side surface of the groove above the isolation medium layer.
In this embodiment, before forming the gate oxide layer on the side surface of the trench above the isolation dielectric layer, the method further includes:
and growing a sacrificial layer on the side surface and the bottom surface of the groove above the isolation dielectric layer, and removing the sacrificial layer by using a wet process. Because the crystal lattice is damaged by the plasma bombardment in the process before the step, the damaged surface is removed by the sacrificial layer, and then the quality of the subsequently grown gate oxide layer can be guaranteed.
In this embodiment, the gate oxide layer may be formed by forming silicon oxide through thermal oxidation, and the gate oxide layer is located on the side surface of the trench above the isolation dielectric layer.
Referring to fig. 14, in this embodiment, a furnace process may be employed to grow a thermal oxide layer on the side surface of the trench to form a gate oxide layer.
And 8, depositing a second layer of polysilicon on the isolation dielectric layer to fill the trench, and etching back the second layer of polysilicon to form a control gate.
Referring to fig. 15, in the present embodiment, a furnace process is used to deposit highly doped polysilicon, and then the polysilicon is etched back to about 1000 μm below the epitaxial layer 100 to form a control gate.
And 9, sequentially forming a body junction injection layer, a source injection layer, an interlayer dielectric layer, a tungsten plug and surface metal to form the MOS device.
Referring to fig. 16, the body junction implant layer 101 may be formed in the epitaxial layer by multiple ion implantations, and the doping type of the body junction implant layer 101 may be P-type.
Referring to fig. 17, a source implant layer 102 is formed in a portion of the depth of the body tie implant layer 101 by multiple ion implantations, and the doping type of the source implant layer 102 may be N-type.
Referring to fig. 18, an interlayer dielectric layer 103 is formed on the surface of the epitaxial layer 100.
Patterned photoresist is coated on the upper surface of the interlayer dielectric layer 103 to define a tungsten plug region, and the tungsten plug region is etched to the bottom of the source implant layer 102 to form a tungsten plug 104, as shown in fig. 19.
Please refer to fig. 20, the deposition of the surface metal 105 is performed.
Referring to fig. 21, the final device is completed through a series of subsequent processes such as thinning the surface metal 105 by using a chemical polishing method, and back-gold and scribing.
According to the device manufactured by the method in the embodiment, due to the manufacturing mode of the side wall protection layer and the control of the height from the bottom below the side wall protection layer, the thickness of the field oxide layer at the bottom and the corner of the trench can be better controlled, so that the electric field intensity of the device can be better optimized, the on-resistance of the device is improved, and the electrical performance of the device is improved.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A manufacturing method of a separation grid groove MOS device is characterized by comprising the following steps:
forming an epitaxial layer on a substrate, and etching the epitaxial layer to form a groove;
forming a first field oxide layer on the side surface and the bottom of the groove;
depositing a side wall protection layer on the surface of the side wall of the first field oxide layer, and then depositing a second thickness oxide layer with a preset thickness on the surface of the bottom of the first field oxide layer;
depositing a first layer of polycrystalline silicon to fill the groove, and etching back the first layer of polycrystalline silicon to form a shielding gate positioned in the groove;
removing the side wall protective layer and the trench oxide layer on the side surface of the trench above the shielding gate, and only keeping the side wall protective layer and the trench oxide layer on the side surface of the shielding gate and the trench oxide layer and the second thickness oxide layer at the bottom of the shielding gate;
forming an isolation dielectric layer above the shielding gate;
forming a gate oxide layer on the side surface of the groove above the isolation medium layer;
depositing a second layer of polycrystalline silicon on the isolation medium layer to fill the groove, and etching back the second layer of polycrystalline silicon to form a control gate;
and sequentially forming a body junction injection layer, a source electrode injection layer, an interlayer dielectric layer, a tungsten plug and surface metal to form the MOS device.
2. The method of claim 1, wherein said etching trenches into the epitaxial layer comprises the steps of:
forming a trench etching mask layer on the upper surface of the epitaxial layer, coating a photoresist, exposing and developing to define a trench area;
and etching the groove region by adopting a dry etching process to form a groove, and removing the light resistance and the groove etching mask layer.
3. The method of claim 2, wherein the dry etching process is controlled such that the top area of the trench is larger than the bottom area and the side surface of the trench forms an angle of 87 ° to 89 °.
4. The method of claim 1, wherein a sidewall protection layer is deposited on a sidewall surface of the first field oxide layer, and a second thickness oxide layer with a predetermined thickness is deposited on a bottom surface of the first field oxide layer, comprising the steps of:
depositing a protective layer on the surface of the first field oxide layer;
etching the protective layer at the bottom of the groove, and reserving the protective layer on the side face of the groove as the side wall protective layer;
and continuously growing a second oxide layer in the groove by using a furnace tube process, so that the second oxide layer at the bottom of the groove and the corner from the bottom of the groove to the side part is thickened to form a second oxide layer with a preset thickness.
5. The method of claim 4, wherein the protective layer is silicon nitride and has a thickness of 0.1 μm to 0.3 μm; the second oxide layer is silicon oxide or thallium oxide.
6. The method of claim 1, wherein the first field oxide layer is silicon oxide.
7. The method of claim 1, wherein forming an isolation dielectric layer over the shield gate comprises:
covering a high-density plasma dielectric layer on the surface of the shielding grid and the side face of the groove by using a chemical vapor deposition method, wherein the high-density plasma dielectric layer extends to the surface of an epitaxial layer outside the groove;
carrying out surface treatment on the high-density plasma dielectric layer on the surface of the epitaxial layer by using a chemical mechanical polishing process, and removing the high-density plasma dielectric layer on the surface of the epitaxial layer;
and etching and reserving the high-density plasma dielectric layer with partial thickness by using a wet process to form an isolation dielectric layer between the shielding gate and the control gate.
8. The method of claim 1, wherein the isolation dielectric layer has a thickness of 0.2 μm to 0.4 μm.
9. The method of claim 1, wherein before forming the gate oxide layer on the trench side over the isolation dielectric layer, further comprising:
and growing a sacrificial layer on the side surface and the bottom surface of the groove above the isolation dielectric layer, and removing the sacrificial layer by using a wet process.
10. The method of claim 9, wherein etching back the second layer of polysilicon to form a control gate comprises:
and depositing the highly doped polysilicon by using a furnace tube process, and etching back to 1000 mu m below the surface of the epitaxial layer to form a control gate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115050641A (en) * | 2022-05-30 | 2022-09-13 | 捷捷微电(上海)科技有限公司 | Manufacturing process of SGT MOSFET |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236989A (en) * | 2007-01-30 | 2008-08-06 | 万国半导体股份有限公司 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET |
| US20080296673A1 (en) * | 2007-05-29 | 2008-12-04 | Alpha & Omega Semiconductor, Ltd | Double gate manufactured with locos techniques |
| CN101621031A (en) * | 2008-06-20 | 2010-01-06 | 飞兆半导体公司 | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
| CN203325907U (en) * | 2012-07-16 | 2013-12-04 | 半导体元件工业有限责任公司 | Insulated gate semiconductor device structure |
| TW201901955A (en) * | 2017-05-19 | 2019-01-01 | 帥群微電子股份有限公司 | Trench type power semiconductor element and method of manufacturing same |
-
2022
- 2022-02-28 CN CN202210184449.2A patent/CN114256077A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236989A (en) * | 2007-01-30 | 2008-08-06 | 万国半导体股份有限公司 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET |
| US20080296673A1 (en) * | 2007-05-29 | 2008-12-04 | Alpha & Omega Semiconductor, Ltd | Double gate manufactured with locos techniques |
| CN101621031A (en) * | 2008-06-20 | 2010-01-06 | 飞兆半导体公司 | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
| CN103762179A (en) * | 2008-06-20 | 2014-04-30 | 飞兆半导体公司 | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
| CN203325907U (en) * | 2012-07-16 | 2013-12-04 | 半导体元件工业有限责任公司 | Insulated gate semiconductor device structure |
| TW201901955A (en) * | 2017-05-19 | 2019-01-01 | 帥群微電子股份有限公司 | Trench type power semiconductor element and method of manufacturing same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115050641A (en) * | 2022-05-30 | 2022-09-13 | 捷捷微电(上海)科技有限公司 | Manufacturing process of SGT MOSFET |
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