CN116759307B - Polysilicon etching method for rounded corner top angles - Google Patents
Polysilicon etching method for rounded corner top angles Download PDFInfo
- Publication number
- CN116759307B CN116759307B CN202310982033.XA CN202310982033A CN116759307B CN 116759307 B CN116759307 B CN 116759307B CN 202310982033 A CN202310982033 A CN 202310982033A CN 116759307 B CN116759307 B CN 116759307B
- Authority
- CN
- China
- Prior art keywords
- etching
- polysilicon
- medium
- rounded corner
- etching method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005530 etching Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 230000007547 defect Effects 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 230000001502 supplementing effect Effects 0.000 description 3
- 238000007792 addition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of semiconductor manufacturing, and discloses a polysilicon etching method for rounded corner angles, which comprises the following steps: s1, growing a layer of polysilicon on the surface of an epitaxial wafer; s2, photoresist coating and photoetching to form a pattern; s3, etching the polysilicon and removing the photoresist; s4, depositing a medium; s5, etching the medium on the whole surface in an anisotropic manner to form a side wall; s6, etching the polysilicon by using an etching method with subtrench etching defects; s7, removing the oxide layer side wall to obtain rounded corner angle polycrystalline silicon; s8, depositing an oxide layer, wherein the medium is a silicon oxide material, the etching method is relatively simple, repeated photoetching is not needed, the top angle can be changed into a round angle, the problem of electric field concentration is avoided, the reliability of the device is improved, the method is large in process Xu Rongxing, the process is still unimpeded under the condition that larger deviation occurs in process conditions, the loss is reduced, and the further thinning of the isolation layer oxide film is ensured.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a polysilicon etching method for rounded corner angles.
Background
MOSFET devices are widely used in the field of high-power discrete devices, and the MOSFET structures used in most of the current power device industries are two types, namely VDMOSFET and UMOSFET. For a VDMOWFET device, because the electrode structures are positioned above the epitaxial layers, how to make each film layer as thin as possible under the condition of meeting the reliability requirement of the basic device becomes a key for improving the reliability of the device; as shown in fig. 1-2, the G electrode is polysilicon, the oxide layer plays a role of isolating the G electrode from the S electrode, and how to improve the electric field bearing capability of the oxide layer as much as possible under the condition that the oxide layer has a certain quality becomes a key point for improving the reliability of the device. The concentration of the electric field will cause the oxide layer to be easily broken down, reducing the reliability of the device (as shown in fig. 1-2).
In order to solve the problem of electric field concentration, most of device manufacturers in the international market adopt a silicon oxide supplementing method, after polycrystalline etching, silicon oxide is deposited, the whole surface is etched to leave a side wall, and finally the silicon oxide is deposited again to form isolation (shown in figure 3).
The method increases the process steps, increases the thickness of the oxidation isolation layer in the side wall direction, and can properly enhance the electric field bearing capacity of the oxidation layer, but does not fundamentally solve the problem of electric field concentration caused by the sharp angle of polysilicon. And if the etching handle control is deviated, sharp corners still appear in the subsequent deposition (as shown in fig. 4).
In summary, an improved process scheme of using a defect etching method of subtrench by U-shaped groove etching and a silicon oxide supplementing method is lacking, and polysilicon can be etched to form rounded corner angles, so that the problem of electric field concentration is fundamentally solved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a polysilicon etching method for rounded corner angles, which solves the problems in the prior art.
In order to solve the above technical problems, according to one aspect of the present invention, more specifically, a method for etching polysilicon with rounded corners and corners, comprising the following steps:
s1, growing a layer of polysilicon on the surface of an epitaxial wafer;
s2, photoresist coating and photoetching to form a pattern;
s3, etching the polysilicon and removing the photoresist;
s4, depositing a medium;
s5, etching the medium on the whole surface in an anisotropic manner to form a side wall;
s6, etching the polysilicon by using an etching method with subtrench etching defects;
s7, removing the oxide layer side wall to obtain rounded corner angle polycrystalline silicon;
s8, depositing an oxide layer to provide guarantee for further thinning of the isolation layer oxide film.
Still further, the medium is a silicon oxide material.
The polysilicon etching method for the corner angles of the round corners has the beneficial effects that:
the etching method is relatively simple, does not need repeated photoetching, can change the top angle into a round angle, avoids the problem of electric field concentration, improves the reliability of the device, has large Xu Rongxing process, is still unimpeded under the condition of larger deviation of process conditions, reduces loss, and provides guarantee for further thinning of the isolation layer oxide film.
Drawings
The invention will be described in further detail with reference to the accompanying drawings and detailed description.
FIG. 1 is a schematic diagram of a VDMOSFET in a conventional MOSFET device;
FIG. 2 is a schematic diagram of a VDMOSFET in a conventional MOSFET device;
FIG. 3 is a schematic structural diagram of a silicon oxide replenishment method;
FIG. 4 is a schematic diagram of the structure of the silicon oxide replenishment process after the addition of process steps;
FIG. 5 is a schematic structural diagram of step S1 in the present invention;
FIG. 6 is a schematic structural diagram of step S2 in the present invention;
FIG. 7 is a schematic diagram of the structure of step S3 in the present invention;
FIG. 8 is a schematic diagram of the structure of step S4 in the present invention;
FIG. 9 is a schematic diagram of the structure of step S5 in the present invention;
FIG. 10 is a schematic diagram of the structure of step S6 in the present invention;
FIG. 11 is a schematic diagram of the structure of step S7 in the present invention;
fig. 12 is a schematic structural diagram of step S8 in the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
As shown in fig. 5-12, according to an aspect of the present invention, there is provided a polysilicon etching method for rounded corners, comprising the steps of:
s1, growing a layer of polysilicon (shown in figure 5) on the surface of an epitaxial wafer;
s2, photoresist coating and photoetching are carried out, and a graph is formed (shown in FIG. 6);
s3, etching the polysilicon, and removing the photoresist (shown in FIG. 7);
s4, depositing a medium (shown in figure 8);
s5, anisotropically etching the medium on the whole surface to form a side wall (shown in figure 9);
s6, etching the polysilicon by using an etching method (high power and high selectivity) with subtrench etching defects (shown in FIG. 10);
s7, removing the oxide layer side wall to obtain rounded corner angle polycrystalline silicon (shown in figure 11);
s8, depositing an oxide layer to provide guarantee for further thinning of the isolation layer oxide film (shown in FIG. 12).
In this embodiment, the medium is a silicon oxide material.
The working principle of the device is as follows: the defect etching method of subtrench by U-shaped groove etching and the silicon oxide supplementing method are utilized to improve the process scheme, so that polysilicon is etched to form rounded corner angles, and the problem of electric field concentration is fundamentally solved.
Of course, the above description is not intended to limit the invention, but rather the invention is not limited to the above examples, and variations, modifications, additions or substitutions within the spirit and scope of the invention will be within the scope of the invention.
Claims (2)
1. A polysilicon etching method for corner angles of round corners is characterized by comprising the following steps:
s1, growing a layer of polysilicon on the surface of an epitaxial wafer;
s2, photoresist coating and photoetching to form a pattern;
s3, etching the polysilicon and removing the photoresist;
s4, depositing a medium;
s5, etching the medium on the whole surface in an anisotropic manner to form a side wall;
s6, etching the polysilicon by using an etching method with subtrench etching defects;
s7, removing the oxide layer side wall to obtain rounded corner angle polycrystalline silicon;
s8, depositing an oxide layer to provide guarantee for further thinning of the isolation layer oxide film.
2. The method for etching polysilicon at a rounded corner according to claim 1, wherein: the medium is a silicon oxide material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310982033.XA CN116759307B (en) | 2023-08-07 | 2023-08-07 | Polysilicon etching method for rounded corner top angles |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310982033.XA CN116759307B (en) | 2023-08-07 | 2023-08-07 | Polysilicon etching method for rounded corner top angles |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116759307A CN116759307A (en) | 2023-09-15 |
| CN116759307B true CN116759307B (en) | 2024-02-02 |
Family
ID=87953492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310982033.XA Active CN116759307B (en) | 2023-08-07 | 2023-08-07 | Polysilicon etching method for rounded corner top angles |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116759307B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09270510A (en) * | 1996-03-29 | 1997-10-14 | Toshiba Corp | Method of manufacturing semiconductor |
| CN103794505A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180071101A (en) * | 2016-12-19 | 2018-06-27 | 삼성전자주식회사 | semiconductor device and method for manufacturing the same |
-
2023
- 2023-08-07 CN CN202310982033.XA patent/CN116759307B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09270510A (en) * | 1996-03-29 | 1997-10-14 | Toshiba Corp | Method of manufacturing semiconductor |
| CN103794505A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116759307A (en) | 2023-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20010036816A (en) | Trench Isolation structure and semiconductor device having the same, trench isolation method | |
| JPS6376330A (en) | Manufacture of semiconductor device | |
| US11127840B2 (en) | Method for manufacturing isolation structure for LDMOS | |
| KR100438772B1 (en) | Method for manufacturing semiconductor device capable to prevent bubble defects | |
| CN113013028A (en) | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device | |
| CN104282543A (en) | Groove gate applied to groove-type MOS device and manufacturing method thereof | |
| US20210343850A1 (en) | Trench gate structure and method of forming a trench gate structure | |
| CN116759307B (en) | Polysilicon etching method for rounded corner top angles | |
| CN102005373B (en) | Manufacture method of grid electrode and power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) | |
| CN106887465B (en) | manufacturing method of trench type double-layer gate MOSFET | |
| JPS6148792B2 (en) | ||
| KR20110018510A (en) | Semiconductor device and method for manufacturing the same | |
| JPH02271620A (en) | Manufacture of semiconductor device | |
| CN101800172A (en) | Manufacturing method of self-aligned polysilicon floating gate | |
| US20210013036A1 (en) | Method and system for fabricating a semiconductor device | |
| CN101819934B (en) | Method for forming TiSi2 layer on doped polysilicon trench of device | |
| CN104347378A (en) | Preparing method of trench gate applied to trench type MOS (metal oxide semiconductor) device | |
| JPH08129952A (en) | Manufacture of field emission type electron gun | |
| CN104241133A (en) | Manufacturing method of power MOS field-effect transistor with trench type source electrode structure | |
| CN104241356A (en) | DMOS device and manufacturing method thereof | |
| CN104779162B (en) | A kind of method for improving trench VDMOS device gate oxide breakdown voltage | |
| US20170207320A1 (en) | Consumption of the channel of a transistor by sacrificial oxidation | |
| CN109378271B (en) | Preparation method of patterned metal film layer, thin film transistor and display substrate | |
| KR100945925B1 (en) | Method for forming saddle Fin type transistor | |
| CN116759308A (en) | Preparation method of gate oxide layer, gate oxide layer and trench type field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |