CN104241133A - Manufacturing method of power MOS field-effect transistor with trench type source electrode structure - Google Patents
Manufacturing method of power MOS field-effect transistor with trench type source electrode structure Download PDFInfo
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- CN104241133A CN104241133A CN201310314819.0A CN201310314819A CN104241133A CN 104241133 A CN104241133 A CN 104241133A CN 201310314819 A CN201310314819 A CN 201310314819A CN 104241133 A CN104241133 A CN 104241133A
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- 230000005669 field effect Effects 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 33
- 238000001039 wet etching Methods 0.000 claims abstract description 27
- 238000001312 dry etching Methods 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 72
- 239000007864 aqueous solution Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 230000007797 corrosion Effects 0.000 claims description 15
- 238000005260 corrosion Methods 0.000 claims description 15
- 239000007788 liquid Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 11
- 238000001020 plasma etching Methods 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000010884 ion-beam technique Methods 0.000 claims description 5
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005265 energy consumption Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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Abstract
The invention relates to a manufacturing method of a power MOS field-effect transistor with a trench type source electrode structure. The manufacturing processes of photoetching, etching and metal layer depositing are sequentially adopted in a source electrode contact area in a unit cell array; according to the manufacturing process of etching of the source electrode contact area in the unit cell array, a photoetching pattern of the same time serves as a mask and dry etching and wet etching are combined, so that a source electrode metal layer makes contact with a transverse contact platform on the top of a source electrode area and a longitudinal contact side surface at the side portion of the source electrode area. According to the manufacturing method of the power MOS field-effect transistor, the contact area between the source electrode metal layer and the source electrode area is increased, so that the contact resistance of the source electrode metal is lowered, the energy consumption is reduced, and the performance of a device is improved.
Description
Technical field
The present invention relates to the manufacturing process of MOS field effect tube, particularly with the method for making MOS field effect tube of trenched source structure.Described MOS field effect tube and mos field effect transistor, metal-oxide-semiconductor field effect transistor, MOSFET.
Background technology
In the performance index of MOS field effect tube, conducting resistance (Rdson) is a very important parameter, its size is directly connected to the energy loss size of device (referring to MOS field effect tube), and reducing along with device size, the importance of conducting resistance is just more outstanding, and the magnitude relationship of conducting resistance is to the quality of device performance.
In theory during MOS field effect tube work, its conducting resistance and energy loss linear, energy loss during the larger devices switch of conducting resistance is larger, therefore people are when Design and manufacture MOS field effect tube, all wish to reduce conducting resistance as much as possible, to reduce the energy loss of device.
The conducting resistance of MOS field effect tube is made up of a few parts such as epilayer resistance, channel resistance, Metal Contact resistance, wherein said Metal Contact resistance comprises: source metal contact resistance, drain metal contacts resistance etc., therefore reduces source metal contact resistance and effectively can reduce conducting resistance.
In existing MOS field effect tube device, the way of contact of source metal and source area has two kinds: the first, source metal in device unit cell contacts with the chain-wales of source area upper surface, the contact-making surface of source metal and source area is only confined to the area of this chain-wales, if increase the area of chain-wales, the area of device will be made to increase, thus increase the cost of device or affect the performance of device; The second, the source metal in device unit cell relies on the sidewall contact of source electrode groove and source area, and the contact-making surface of source metal and source area is only the area of the sidewall of source area.The contact area that these two kinds of ways of contact can provide is all less, and therefore equivalent contact resistance is comparatively large, is unfavorable for reducing the conducting resistance of device and improving the reliability of device.
Along with the aggravation of market competition, the requirement controlled semiconductor device manufacturing cost is also more and more higher, how under the prerequisite not increasing manufacturing cost, can improving device performance (as specific on-resistance (Specific Rdson), AC parameter, DC parameter etc.) be the striving direction of enterprise and production firm, therefore go out a kind of low cost and high performance MOS field effect tube device is the main problem that relevant enterprise faces by Design and manufacture.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide the method for making MOS field effect tube with trenched source structure, the contact area of source metal and source area (N+ or P+) is increased by a kind of mode of low cost, thus reduce the source metal contact resistance of MOS field effect tube, reduce energy loss, improve device performance.
For reaching above object, the technical scheme that the present invention takes is:
With the method for making MOS field effect tube of trenched source structure, it is characterized in that: photoetching, etching and deposited metal manufacture craft are adopted successively to the source contact area in unit cell array, and be for mask with a same litho pattern to the etching of the source contact area in unit cell array, the compound mode of dry etching+wet etching is adopted to carry out, the lateral contact platform making source metal simultaneously contact top, source area contacts side with the longitudinal direction of source area sidepiece, and described compound mode is:
The first step, dry method longitudinally etches insulating medium layer 8, source area oxide layer 11 and the first interarea continuously, forms source contact area groove 10;
Second step, wet method horizontal etching insulative dielectric layer 8 and source area oxide layer 11 simultaneously, form the lateral contact platform at source electrode top;
Or described compound mode is:
The first step, dry method longitudinally etches insulating medium layer 8 and source area oxide layer 11 continuously;
Second step, wet method horizontal etching insulative dielectric layer 8 and source area oxide layer 11 simultaneously, form the lateral contact platform at source electrode top;
3rd step, dry method is etching the first interarea longitudinally, forms source contact area groove 10.
On the basis of technique scheme, described MOS field effect tube is N or P type groove-type power metal-oxide-semiconductor field effect transistor, or is N or P type plane formula MOS field effect tube, or is igbt.
On the basis of technique scheme, with source contact area litho pattern for mask, when adopting dry etching method, longitudinally etch insulating medium layer 8, source area oxide layer 11 and the first interarea continuously, the second position, conduction type doped region below etching depth to the first conduction type doped region, form source contact area groove 10, the side direction of this source contact area groove 10 is formed with the contact side with the first conduction type doped region, and the bottom of this source contact area groove 10 is formed with the contact bottom surface with the second conduction type doped region;
With source contact area litho pattern for mask, when adopting wet etching method, the while of laterally, etching insulative dielectric layer 8 and source area oxide layer 11, form the lateral contact platform at the first top, conduction type doped region.
On the basis of technique scheme, for N-type metal-oxide-semiconductor field effect transistor, the first conduction type refers to N-type, and the second conduction type refers to P type; For P type metal-oxide-semiconductor field effect transistor, the first conduction type refers to P type, and the second conduction type refers to N-type.
On the basis of technique scheme, the source area oxide layer under insulating medium layer produces laterally cavity, and in wet etching course, the corrosion rate of wet etching liquid to insulating medium layer is more than or equal to the corrosion rate to source area oxide layer.
On the basis of technique scheme, be more than or equal to corrosion rate to source area oxide layer to meet the corrosion rate of wet etching liquid to insulating medium layer, described wet etching liquid adopts hydrofluoric acid aqueous solution or the buffered hydrofluoric acid aqueous solution.
On the basis of technique scheme, described hydrofluoric acid aqueous solution is made up of hydrofluoric acid and water, and wherein the mass concentration of hydrofluoric acid is 2% ~ 45%,
The described buffered hydrofluoric acid aqueous solution is made up of hydrofluoric acid, ammonium fluoride and water, and wherein the mass concentration of hydrofluoric acid is 0.091% ~ 12%.
On the basis of technique scheme, described insulating medium layer 8 can be boron-phosphorosilicate glass, phosphorosilicate glass or silicon dioxide.
On the basis of technique scheme, after described source area oxide layer 11 includes the first conductive type impurity ion implantation, by the oxide layer that formed at the first conduction type doped region upper surface during high temperature knot and remaining grid oxygen oxide layer, this oxide layer is the silicon dioxide layer of doping, and impurity is the first conductive type impurity.
On the basis of technique scheme, dry etching is: plasma etching, ion beam etching or reactive ion etching method.
Because technique scheme is used, the present invention compared with prior art has following advantages and effect:
1, the present invention only adopts a photoetching and in conjunction with dry etching and wet corrosion technique, the lateral contact platform that source metal just can be made simultaneously to contact top, source area contacts side (see Fig. 1,2) with the longitudinal direction of source area sidepiece, and prior art at least needs to adopt Twi-lithography, by contrast, the present invention obtains in the mode of low cost the effect increasing source metal and source region contact area, thus reduce the source metal contact resistance of MOS field effect tube, reduce energy loss, improve device performance.
2, the present invention adopts wet etching method, laterally etch in insulating medium layer and source area oxide coating process simultaneously, ensure that the lateral encroaching speed of insulating medium layer is more than or equal to the lateral encroaching speed of source area oxide layer by the concentration controlling hydrofluoric acid in wet etching liquid, thus the source area oxide layer below guarantee insulating medium layer does not occur that side direction cavity is (see source area oxide layer 11 position in Fig. 2, side direction cavity is there will be) when the lateral encroaching speed at this position is greater than the corrosion rate of the insulating medium layer 8 of top, source metal is enable to fill source contact area smoothly, especially cavity is not left with the contact of source area oxide layer, in order to avoid produce leakage current to cause component failure.
Accompanying drawing explanation
The present invention has following accompanying drawing:
Fig. 1 is MOS field effect tube generalized section of the present invention;
Fig. 2 is MOS field effect tube source contact area of the present invention manufacturing process principle schematic;
Fig. 3 (a) ~ 3 (g) is the schematic flow sheet adopting the method for the invention to manufacture plane formula MOS field effect tube.
Reference numeral:
1, N-type substrate; 2, N-epitaxial loayer; 3, field oxide; 4, gate oxide; 5, conductive polycrystalline silicon; 6, P-doped region; 7, N+ doped region; 8, insulating medium layer; 9, metal level; 10, source contact area groove; 11, source area oxide layer; 12, source contact area litho pattern (photoresist barrier layer).
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Method for making MOS field effect tube with trenched source structure of the present invention, its technological core is: by a kind of mode of low cost, increase the source metal of source contact area and the contact area of source area (N+ or P+), thus reduce the source metal contact resistance of MOS field effect tube, reduce energy loss.
Manufacture method of the present invention can manufacture with trenched source structure, the device architecture of the source contact area of MOS field effect tube is improved, be applicable to N or P type groove-type power metal-oxide-semiconductor field effect transistor, also N or P type plane formula MOS field effect tube is applicable to, also be applicable to igbt (IGBT) simultaneously, comprising plane formula IGBT and plough groove type IGBT, such as punch (PT type), non-punch (NPT type) and field cut-off type (F-stop type).
Method for making MOS field effect tube with trenched source structure of the present invention, photoetching, etching and deposited metal manufacture craft are adopted successively to the source contact area in unit cell array, and be for mask (namely only adopting a photoetching) with a same litho pattern to the etching of the source contact area in unit cell array, the compound mode of dry etching+wet etching is adopted to carry out, the lateral contact platform making source metal simultaneously contact top, source area contacts side with the longitudinal direction of source area sidepiece, and described compound mode is:
The first step, dry method longitudinally etches insulating medium layer 8, source area oxide layer 11 and the first interarea continuously, forms source contact area groove 10;
Second step, wet method horizontal etching insulative dielectric layer 8 and source area oxide layer 11 simultaneously, form the lateral contact platform at source electrode top;
Or described compound mode is:
The first step, dry method longitudinally etches insulating medium layer 8 and source area oxide layer 11 continuously;
Second step, wet method horizontal etching insulative dielectric layer 8 and source area oxide layer 11 simultaneously, form the lateral contact platform at source electrode top;
3rd step, dry method is etching the first interarea longitudinally, forms source contact area groove 10.
Photoetching and deposited metal all adopt existing known technology to implement, and no longer describe in detail.
On the basis of technique scheme, with source contact area litho pattern for mask, when adopting dry etching method, longitudinally etch insulating medium layer 8, source area oxide layer 11 and the first interarea continuously, the second position, conduction type doped region below etching depth to the first conduction type doped region, form source contact area groove 10, the side direction of this source contact area groove 10 is formed with the contact side with the first conduction type doped region, and the bottom of this source contact area groove 10 is formed with the contact bottom surface with the second conduction type doped region;
With source contact area litho pattern for mask, when adopting wet etching method, the while of laterally, etching insulative dielectric layer 8 and source area oxide layer 11, form the lateral contact platform at the first top, conduction type doped region.
The present invention is applicable to plane formula MOS field effect tube and groove-type power metal-oxide-semiconductor field effect transistor two kinds of structure types, wherein, in both " the first conduction type " and " the second conduction type ", refer to N-type for N-type metal-oxide-semiconductor field effect transistor first conduction type, the second conduction type refers to P type; Just in time contrary for P type metal-oxide-semiconductor field effect transistor, the first conduction type refers to P type, and the second conduction type refers to N-type.The present invention is equally applicable to igbt (IGBT).
On the basis of technique scheme, the source area oxide layer under insulating medium layer produces laterally cavity, and in wet etching course, the corrosion rate of wet etching liquid to insulating medium layer is more than or equal to the corrosion rate to source area oxide layer.
On the basis of technique scheme, be more than or equal to corrosion rate to source area oxide layer to meet the corrosion rate of wet etching liquid to insulating medium layer, described wet etching liquid adopts hydrofluoric acid aqueous solution or the buffered hydrofluoric acid aqueous solution,
Described hydrofluoric acid aqueous solution is made up of hydrofluoric acid and water, and wherein the mass concentration of hydrofluoric acid is 2% ~ 45%,
The described buffered hydrofluoric acid aqueous solution is made up of hydrofluoric acid, ammonium fluoride and water, and wherein the mass concentration of hydrofluoric acid is 0.091% ~ 12%.
On the basis of technique scheme, described insulating medium layer 8 can be boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG) or silicon dioxide (SiO
2).
On the basis of technique scheme, after described source area oxide layer 11 includes the first conductive type impurity ion implantation, by the oxide layer that formed at the first conduction type doped region upper surface during high temperature knot and remaining grid oxygen oxide layer, this oxide layer is the silicon dioxide layer of doping, and impurity is the first conductive type impurity.
On the basis of technique scheme, dry etching take gas as the lithographic method of main medium, wherein, mainly contains plasma etching, ion beam etching and reactive ion etching method.
Plasma etching is filled with reacting gas in vacuum reaction indoor, and power supply energy creates a high-frequency electric field in the reaction chamber, is excited by mist and becomes plasmoid, complete etching by chemical reaction.
Ion beam etching is also ise, it is a kind of physical technology, during etching, wafer is fixed on the indoor negative pole fixture of vacuum reaction, argon gas stream is imported subsequently in reative cell, argon gas is just subject to the effect of the high energy electron line of a pair anode and cathode, is ionized as positively charged upper state, thus is attracted to wafer on negative pole fixture, and be constantly accelerated and bombard the container portion entering exposure, exploding sub-fraction from wafer surface.
Reactive ion etching combines the principle of plasma etching and ion beam etching, similar with plasma etching in system configuration, has ion polishing ability simultaneously.
It is below embodiment.
Embodiment one: a kind of method for making MOS field effect tube with trenched source structure, the feature of the method to source contact area manufacture craft is: with a same litho pattern for mask, adopts dry etching+wet corrosion technique to realize.And the manufacture method of whole device is as shown in Fig. 3 (a) ~ 3 (g), specifically comprise following process steps:
(1) semi-conductor silicon chip with two opposing main faces of N-type is provided, as this semi-conductor silicon chip of Fig. 3 (a) is made up of N-type substrate 1 and N-epitaxial loayer 2.
(2) on the first interarea, form field oxide 3, see Fig. 3 (a).
(3) optionally shelter and etch field oxide 3 and form gate oxide 4, seeing Fig. 3 (b).
(4) on gate oxide 4, form one deck conductive polycrystalline silicon 5, see Fig. 3 (c).
(5) optionally shelter and etching conductive polysilicon 5, make partially conductive polysilicon 5 form grid, see Fig. 3 (d).
(6) using the conductive polycrystalline silicon 5 as grid as self-aligned barrier layers, p type impurity ion implantation is carried out to the first interarea, and form P-doped region 6 by knot, see Fig. 3 (d).
(7) using the conductive polycrystalline silicon 5 as grid as self-aligned barrier layers, N-type impurity ion implantation is carried out to the first interarea, and by knot formation as the N+ doped region 7 of source electrode and the source area oxide layer 11 being positioned at N+ doped region 7 upper surface, described N+ doped region 7 is positioned at the top of inside, P-doped region 6, sees Fig. 3 (d).
(8) deposit insulating medium layer 8, as boron-phosphorosilicate glass (BPSG), is shown in Fig. 3 (e).
(9) the sheltering of electing property on insulating medium layer 8, forms source contact area litho pattern 12, as shown in Figure 2.
(10) with source contact area litho pattern 12 for mask, adopt dry etching method, longitudinally etch insulating medium layer 8, source area oxide layer 11 and the first interarea continuously, see Fig. 2 and Fig. 3 (f), position, P-doped region 6 below etching depth to N+ doped region 7 (its go deep in silicon layer the degree of depth between 0.01um ~ 10um), form source contact area groove 10, the side direction of this groove is formed with the contact side with N+ doped region 7, and bottom is formed with the contact bottom surface with P-doped region 6.
(11) then, also with source contact area litho pattern 12 for mask, adopt wet etching method, laterally simultaneously etching insulative dielectric layer 8 and source area oxide layer 11, be shown in Fig. 2 and Fig. 3 (f), forms the lateral contact platform at top, N+ doped region 7; Described wet etching liquid adopts hydrofluoric acid aqueous solution or the buffered hydrofluoric acid aqueous solution, described hydrofluoric acid aqueous solution is made up of hydrofluoric acid and water, wherein the mass concentration of hydrofluoric acid is 2% ~ 45%, the described buffered hydrofluoric acid aqueous solution is made up of hydrofluoric acid, ammonium fluoride and water, and wherein the mass concentration of hydrofluoric acid is 0.091% ~ 12%.
Such as, when wet etching liquid adopts mass concentration to be hydrofluoric acid (HF) of 49%, need to be diluted with water into hydrofluoric acid aqueous solution, both volume ratios are HF (49%): H
2o=1: 0.1 ~ 1: 30, the mass concentration through (the HF relative density of 49% the is 1.18) hydrofluoric acid that converts is 2% ~ 45%.
For another example, wet etching liquid buffered hydrofluoric acid solution (BOE) [wherein, the mass concentration 1.64% ~ 13.1% of HF; NH
4the mass concentration of F is 29.5% ~ 38.7%] time, need to be diluted with water into the buffered hydrofluoric acid aqueous solution, both volume ratios are BOE:H
2o=1: 0.1 ~ 1: 20, the mass concentration through (BOE relative density the is 1.18) hydrofluoric acid that converts is 0.091% ~ 12%.
Concrete selection when wet etching containing HF concentration in corrosive liquid will ensure that the lateral encroaching speed of corrosive liquid to insulating medium layer is more than or equal to source area oxide layer lateral encroaching speed, avoids source area oxide layer to occur side direction cavity.And this point will be determined according to the material of insulating medium layer and source area oxide layer.General insulating medium layer is boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG) or silicon dioxide (SiO
2).Source area oxide layer is the silicon dioxide of doping.
(12) in insulating medium layer 8 surface and source contact area groove 10, metal level 9 is formed, see Fig. 3 (g), wherein, metal in source contact area is contacted with N+ doped region 7 with the described side that contacts by described contact platform on the one hand simultaneously, is contacted on the other hand by described contact bottom surface with P-doped region 6.
(13) optionally shelter and etching sheet metal 9.
Although above-mentioned example is described with N-type metal-oxide-semiconductor field effect transistor, the present invention is also applicable to P type metal-oxide-semiconductor field effect transistor, and wherein only need to change P into N, N changes P into, is suitable for the metal-oxide-semiconductor field effect transistor that grid is groove structure simultaneously simultaneously.
For MOS field effect tube, it is mainly ensureing under good device performance prerequisite, by reducing the competitiveness manufacturing original raising market of device.A kind of method for making MOS field effect tube with trenched source structure provided by the invention, main feature only uses a photoetching and just can reach the effect increasing source contact area in conjunction with dry method and wet-etching technology, and the first conduction type doped region utilizes conductive polycrystalline silicon floor or field silicon oxide layer to be come by ion implantation and knot as self-aligned barrier layers, without the need to additionally increasing photoetching, the manufacturing process of whole like this device only used four mask and has come.By contrast, and conventional power metal-oxide-semiconductor field effect transistor needs more than six times or six times photoetching to complete manufacture, therefore the present invention not only source electrode there is less contact resistance and good device performance, and manufacturing cost is lower.
In addition, the manufacture method of source contact area of the present invention is not limited only to foregoing description, has allowed all distortion; and cause identical with this manufacture method; all in the present invention protects, be equally applicable to IGBT (igbt), no longer illustrate here.
The content be not described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. with the method for making MOS field effect tube of trenched source structure, it is characterized in that: photoetching, etching and deposited metal manufacture craft are adopted successively to the source contact area in unit cell array, and be for mask with a same litho pattern to the etching of the source contact area in unit cell array, the compound mode of dry etching+wet etching is adopted to carry out, the lateral contact platform making source metal simultaneously contact top, source area contacts side with the longitudinal direction of source area sidepiece, and described compound mode is:
The first step, dry method longitudinally etches insulating medium layer (8), source area oxide layer (11) and the first interarea continuously, forms source contact area groove (10);
Second step, wet method horizontal etching insulative dielectric layer (8) and source area oxide layer (11) simultaneously, form the lateral contact platform at source electrode top;
Or described compound mode is:
The first step, dry method longitudinally etches insulating medium layer (8) and source area oxide layer (11) continuously;
Second step, wet method horizontal etching insulative dielectric layer (8) and source area oxide layer (11) simultaneously, form the lateral contact platform at source electrode top;
3rd step, dry method is etching the first interarea longitudinally, forms source contact area groove (10).
2. as claimed in claim 1 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: described MOS field effect tube is N or P type groove-type power metal-oxide-semiconductor field effect transistor, or be N or P type plane formula MOS field effect tube, or be igbt.
3. as claimed in claim 1 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: with source contact area litho pattern for mask, when adopting dry etching method, longitudinally etch insulating medium layer (8) continuously, source area oxide layer (11) and the first interarea, the second position, conduction type doped region below etching depth to the first conduction type doped region, form source contact area groove (10), the side direction of this source contact area groove (10) is formed with the contact side with the first conduction type doped region, the bottom of this source contact area groove (10) is formed with the contact bottom surface with the second conduction type doped region,
With source contact area litho pattern for mask, when adopting wet etching method, the while of laterally, etching insulative dielectric layer (8) and source area oxide layer (11), form the lateral contact platform at the first top, conduction type doped region.
4., as claimed in claim 3 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: for N-type metal-oxide-semiconductor field effect transistor, the first conduction type refers to N-type, and the second conduction type refers to P type; For P type metal-oxide-semiconductor field effect transistor, the first conduction type refers to P type, and the second conduction type refers to N-type.
5. as claimed in claim 1 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: the source area oxide layer under insulating medium layer produces laterally cavity, in wet etching course, the corrosion rate of wet etching liquid to insulating medium layer is more than or equal to the corrosion rate to source area oxide layer.
6. as claimed in claim 5 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: be more than or equal to corrosion rate to source area oxide layer to meet the corrosion rate of wet etching liquid to insulating medium layer, described wet etching liquid adopts hydrofluoric acid aqueous solution or the buffered hydrofluoric acid aqueous solution.
7., as claimed in claim 6 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: described hydrofluoric acid aqueous solution is made up of hydrofluoric acid and water, wherein the mass concentration of hydrofluoric acid is 2% ~ 45%,
The described buffered hydrofluoric acid aqueous solution is made up of hydrofluoric acid, ammonium fluoride and water, and wherein the mass concentration of hydrofluoric acid is 0.091% ~ 12%.
8., as claimed in claim 1 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: described insulating medium layer (8) can be boron-phosphorosilicate glass, phosphorosilicate glass or silicon dioxide.
9. as claimed in claim 1 with the method for making MOS field effect tube of trenched source structure, it is characterized in that: after described source area oxide layer (11) includes the first conductive type impurity ion implantation, by the oxide layer that formed at the first conduction type doped region upper surface during high temperature knot and remaining grid oxygen oxide layer, this oxide layer is the silicon dioxide layer of doping, and impurity is the first conductive type impurity.
10., as claimed in claim 1 with the method for making MOS field effect tube of trenched source structure, it is characterized in that, dry etching is: plasma etching, ion beam etching or reactive ion etching method.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107452712A (en) * | 2016-05-31 | 2017-12-08 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN113658866A (en) * | 2021-07-08 | 2021-11-16 | 深圳天狼芯半导体有限公司 | Preparation method of power device and power device |
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2013
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107452712A (en) * | 2016-05-31 | 2017-12-08 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN107452712B (en) * | 2016-05-31 | 2021-07-27 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN113658866A (en) * | 2021-07-08 | 2021-11-16 | 深圳天狼芯半导体有限公司 | Preparation method of power device and power device |
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