CN107808904A - Double bracket shape grid-control two-way switch tunneling transistor and its manufacture method - Google Patents
Double bracket shape grid-control two-way switch tunneling transistor and its manufacture method Download PDFInfo
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- CN107808904A CN107808904A CN201711046024.0A CN201711046024A CN107808904A CN 107808904 A CN107808904 A CN 107808904A CN 201711046024 A CN201711046024 A CN 201711046024A CN 107808904 A CN107808904 A CN 107808904A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
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- 238000009413 insulation Methods 0.000 claims description 11
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- 238000001259 photo etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
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- 230000003068 static effect Effects 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 description 4
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- 239000013078 crystal Substances 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
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- 230000033228 biological regulation Effects 0.000 description 1
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- 239000002019 doping agent Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The present invention relates to a kind of double bracket shape grid-control two-way switch tunneling transistor and its manufacture method, device of the present invention has bracket grid and symmetrical architectural feature, with stronger grid control ability and by adjusting the interchangeable electrode voltage of source and drain the second interchangeable area of class impurity heavy doping source and drain can be controlled to be used as source region or drain region, change tunnelling current direction.The advantages of present invention has low speed paper tape reader static power disspation and reverse leakage current, stronger grid control ability, low subthreshold swing and can realize two-way switch function.In contrast to common MOSFETs types device, more excellent switching characteristic is realized using tunneling effect；In contrast to common tunneling field-effect transistor, the present invention has the interchangeable bi-directional symmetrical switching characteristic of source and drain not available for common tunneling field-effect transistor, therefore is adapted to popularization and application.
Description
Technical field
The present invention relates to super large-scale integration manufacturing field, and in particular to one kind is applied to low power consumption integrated circuit system
The double bracket shape grid-control two-way switch tunneling transistor and its manufacture method with low current leakage made.
Background technology
The elementary cell MOSFETs of integrated circuit can become less and less according to the requirement of Moore's Law, size, therewith
What is come is not only that difficulty in manufacturing process is deepened, various ill effects also highlighting all the more.Nowadays IC design
Itself produces the limitation of the physical mechanism of electric current when used MOSFETs types device is due to its work, and its subthreshold swing is not
60mV/dec can be less than.And common tunneling field-effect transistor as switching-type device in use, using carrier in semiconductor
Conduction mechanism of the tunneling effect as electric current can occur between band, its subthreshold swing will be substantially better than MOSFETs type devices
The 60mv/dec limit.However, common tunneling field-effect transistor source region and drain region use the impurity of different conduction-types, it is this non-
Symmetrical structure feature causes it can not functionally substitute the MOSFETs type devices with symmetrical structure feature completely.With N-type tunnel
Exemplified by wearing field-effect transistor, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential, then tunnelling
Field-effect transistor will be in the conduction state all the time, and the size of conducting electric current is no longer able to be well controlled by gate electrode
And regulation, this causes the switching characteristic of whole tunneling field-effect transistor to fail.
The content of the invention
Goal of the invention：
In order to effectively combine Asia low with MOSFETs type devices source electrode, the interchangeable and common tunneling field-effect transistor of drain electrode is utilized
The advantages of threshold value amplitude of oscillation amplitude of oscillation, solving MOSFETs type device subthreshold swings can not reduce and common tunneling field-effect transistor
Can only be as the deficiency of single-way switch, the present invention proposes a kind of double bracket shape grid-control two-way switch tunneling transistor and its manufacturer
Method.The transistor has logic function and is currently based on the completely compatible advantageous feature of MOSFETs integrated circuits, source and drain both ends knot
The symmetry of structure allows it to have by exchanging the function of realizing that source and drain bi-directional symmetrical switchs to source electrode and the voltage of drain electrode
The interchangeable two-way switch characteristic of source-drain electrode, additionally there is forward and reverse electric current than high and low subthreshold swing, high forward conduction
The working characteristics such as electric current.
Technical scheme：
The present invention is achieved through the following technical solutions：
A kind of double bracket shape grid-control two-way switch tunneling transistor, the silicon substrate comprising SOI wafer, it is characterised in that：SOI wafer
Silicon substrate above be SOI wafer insulated substrate layer, the top of the insulated substrate layer of SOI wafer is monocrystalline silicon thin film, first
The interchangeable intrinsic region a of class impurity heavily doped region, source and drain, the interchangeable intrinsic region b of source and drain, the second class impurity heavy doping source and drain are interchangeable
Area a, the interchangeable area b of the second class impurity heavy doping source and drain, grid electrode insulating floor, the portion of bracket gate electrode and insulating medium barrier layer
Subregion；Wherein, first kind impurity heavily doped region is located at the center section of monocrystalline silicon thin film, and the second class impurity heavy doping source and drain can
It is thin positioned at first kind impurity heavily doped region both sides monocrystalline silicon respectively to exchange area a and the second interchangeable area b of class impurity heavy doping source and drain
The middle body of film, the interchangeable area a of the second class impurity heavy doping source and drain and the second interchangeable area b of class impurity heavy doping source and drain bottom
The upper surface of the insulated substrate layer of portion surface and SOI wafer contacts with each other；The interchangeable intrinsic region a of source and drain and source and drain are interchangeable intrinsic
Area b is located at the exterior lateral area for not carried out intentional doping process at left and right sides of monocrystalline silicon thin film respectively, respectively to the second class
The interchangeable area a of impurity heavy doping source and drain and the second interchangeable area b of class impurity heavy doping source and drain front and rear side and outside form three faces
Parcel；
Grid electrode insulating layer is insulating material, rectangular to be centered around monocrystalline silicon thin film surrounding, with monocrystalline silicon thin film and the first kind
The lateral wall of impurity heavily doped region contacts with each other, and intermediate region outer surface and the insulation of the grid electrode insulating layer of front and rear sides are situated between
Matter barrier layer contacts with each other, and the remainder of the outer surface of grid electrode insulating layer contacts with each other with gate electrode；
Gate electrode is made up of metal material or polycrystalline silicon material, the left and right sides portion with the front and rear sides surface of grid electrode insulating layer
Point and left and right sides surface contact with each other, i.e., gate electrode with the surrounding outer surface of grid electrode insulating layer except positioned at front and rear
Part outside the outer surface to be contacted with each other with insulating medium barrier layer of the intermediate region of both side surface contacts with each other, grid electricity
Pole overlooks viewing and forms a pair of double bracket shapes, and left and right ends three bread of formation of grid electrode insulating layer are wrapped up in；Grid electrode insulating
Layer forms insulation barrier between gate electrode and monocrystalline silicon thin film；Gate electrode intrinsic region a only interchangeable to source and drain and source and drain can be mutual
Changing intrinsic region b has an obvious field-effect control action, and other regions to monocrystalline silicon thin film and positioned at monocrystalline silicon thin film central portion
The first kind impurity heavily doped region divided is without obvious control action；Monocrystalline silicon thin film, first kind impurity heavily doped region, source and drain are interchangeable
The interchangeable intrinsic region b of intrinsic region a, source and drain, the interchangeable area a of the second class impurity heavy doping source and drain and the second class impurity heavy doping source and drain
Interchangeable area b is combined into a rectangle domain structure jointly；Monocrystalline silicon thin film, first kind impurity heavily doped region, source and drain are interchangeable intrinsic
SI semi-insulation medium resistance on the interchangeable intrinsic region b of area a, source and drain, grid electrode insulating floor, bracket gate electrode and insulated substrate floor
The upper surface of barrier is the remainder of insulating medium barrier layer, and the interchangeable electrode a of source and drain is located at the second class impurity heavy-doped source
Interchangeable area a top is leaked, and forms good Ohmic contact therewith；It is heavily doped that the interchangeable electrode b of source and drain is located at the second class impurity
The miscellaneous interchangeable area b of source and drain top, and good Ohmic contact is formed therewith；The interchangeable electrode a of source and drain and the interchangeable electricity of source and drain
Pole b outer surface is in contact with insulating medium barrier layer respectively, and exhausted each other by the barrier effect of insulating medium barrier layer
Edge；Whole transistor arrangement positioned at the part of first kind impurity heavily doped region both sides be in symmetrical structure each other, can be in source and drain
The interchangeable electrode a and interchangeable electrode b of source and drain realizes same output characteristics in the case of symmetrically exchanging.
A kind of manufacture method of the double bracket shape grid-control two-way switch tunneling transistor, it is characterised in that：
Its manufacturing step is as follows：
Step 1：One SOI wafer is provided, bottom is the silicon substrate of SOI wafer, is insulated substrate layer above silicon substrate,
The upper surface of insulated substrate layer is monocrystalline silicon thin film, and by ion implanting or diffusion technique, the monocrystalline silicon above SOI wafer is thin
The intermediate region doping of film, preliminarily forms first kind impurity heavily doped region；
Step 2：Part monocrystalline silicon thin film and first kind impurity heavily doped region are removed by photoetching, etching technics, in SOI wafer
It is upper further to form monocrystalline silicon thin film and first kind impurity heavily doped region；
Step 3：By the technique such as aoxidizing or depositing, etch, in the outside shape of monocrystalline silicon thin film and first kind impurity heavily doped region
Into grid electrode insulating layer；
Step 4：By depositing technics, the superstructure electrode insulation medium formed in step 3, after planarizing surface, lead to
Over etching technique, only retain the dielectric on the outside of the center section of grid electrode insulating layer front and rear sides, preliminarily form insulation and be situated between
Matter barrier layer；
Step 5：By depositing technics, in the upper surface of remaining insulated substrate layer, be close to grid electrode insulating layer, deposit metal or
Polysilicon, gate electrode is formed after planarizing surface；
Step 6：By ion implantation technology, the intermediate region of the monocrystalline silicon thin film of the left and right sides is doped, forms second
The interchangeable area a of class impurity heavy doping source and drain and the second interchangeable area b of class impurity heavy doping source and drain；
Step 7：By oxidation or depositing technics, dielectric, planarization are deposited in the upper surface for the structure that step 6 is formed
Again by photoetching, etching technics behind surface, the interchangeable area a of the second class impurity heavy doping source and drain and the second class impurity heavy doping source and drain
Performed etching above interchangeable area b, and form through hole, expose the interchangeable area a of the second class impurity heavy doping source and drain and the second class
The interchangeable area b of impurity heavy doping source and drain upper surface is to ultimately form the remainder of insulating medium barrier layer, then to formation
Metal to through hole is injected in through hole to be completely filled, and the interchangeable electrode a of source and drain and the interchangeable electricity of source and drain are formed after planarizing surface
Pole b
Advantage and effect：
The invention has the advantages that and beneficial effect：
1. the symmetrical interchangeable two-way switch characteristic of source and drain：
Device of the present invention is a kind of double bracket shape grid-control two-way switch tunneling transistor, in monocrystalline silicon thin film 1 close to grid electricity
The part of the both sides of pole insulating barrier 7 has tunneling structure independent of each other respectively, because device has bilateral symmetry, in grid electricity
Under the control action of pole 8, the both sides of monocrystalline silicon thin film 1 top is in the near surface contacted with grid electrode insulating layer 7 while tunnel occurs
Wear, the second class impurity heavy-doped source is controlled by the voltage for adjusting the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain
Leak the interchangeable area b 6 of the interchangeable class impurity heavy doping source and drain of area a 5 and second and be used as source region or drain region, therefore tunnelling electricity can be changed
Direction is flowed, realizes source and drain of the invention symmetrically interchangeable two-way switch characteristic.
2. low subthreshold swing：
Because the present invention is the tunneling mechanism based on tunneling field-effect transistor, and symmetrical double bracket grid structure is used, due to position
Yu Yuan, leakage side bracket gate electrode intrinsic region a 3 interchangeable to the source and drain and interchangeable intrinsic region b of source and drain respectively in three directions
4 three bread of formation are wrapped up in, and have outstanding gate electrode control ability, under the control action of gate electrode 8 so that energy band is in identical
It is easier to bend under gate voltage, obtains bigger electric-field intensity so that tunneling efficiency increases, compared to MOSFETs type devices
Part and common tunneling field-effect transistor, can obtain lower subthreshold swing.
3. low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio：
Exist when between the interchangeable area a 5 of the second class impurity heavy doping source and drain, the second interchangeable area b 6 of class impurity heavy doping source and drain
During electrical potential difference, and when gate electrode 8 is in subthreshold value or reverse-biased, due to first kind impurity heavily doped region 2 respectively with the second class
The interchangeable area a 5 of impurity heavy doping source and drain, the second interchangeable area b 6 of class impurity heavy doping source and drain have opposite impurity type, because
This certainty of first kind impurity heavily doped region 2 and the interchangeable class impurity heavy doping of area a 5 or second of the second class impurity heavy doping source and drain
One of interchangeable area b 6 of source and drain is in reverse-biased, and the certainty of first kind impurity heavily doped region 2 and the second class impurity weight
Portion of monocrystalline silicon thin film 1 be present between the interchangeable interchangeable area b 6 of class impurity heavy doping source and drain of area a 5 or second of doped source and drain,
Therefore device, which has, preferably suppresses the ability that the tunnelling current caused by field strength is too strong significantly increases.In other words,
A kind of impurity heavily doped region 2 is due to by the control of gate electrode 8, can not effectively block the second class impurity heavy doping source and drain interchangeable
The conducting of majority carrier between the interchangeable area b 6 of class impurity heavy doping source and drain of area a 5 or second.Therefore the present invention has low
The advantages of quiescent dissipation, low reverse leakage current and high forward and reverse electric current ratio.
Brief description of the drawings
Fig. 1 is the top view of double bracket shape grid-control two-way switch tunneling transistor of the present invention；
Fig. 2 is the profile along dotted line A of double bracket shape grid-control two-way switch tunneling transistor of the present invention；
Fig. 3 is the profile along dotted line B of double bracket shape grid-control two-way switch tunneling transistor of the present invention；
Fig. 4 is the top view of step 1；
Fig. 5 is the profile along dotted line A of step 1；
Fig. 6 is the profile along dotted line B of step 1；
Fig. 7 is the top view of step 2；
Fig. 8 is the profile along dotted line A of step 2；
Fig. 9 is the profile along dotted line B of step 2；
Figure 10 is the top view of step 3；
Figure 11 is the profile along dotted line A of step 3；
Figure 12 is the profile along dotted line B of step 3；
Figure 13 is the top view of step 4；
Figure 14 is the profile along dotted line A of step 4；
Figure 15 is the profile along dotted line B of step 4；
Figure 16 is the top view of step 5；
Figure 17 is the profile along dotted line A of step 5；
Figure 18 is the profile along dotted line B of step 5；
Figure 19 is the top view of step 6；
Figure 20 is the profile along dotted line A of step 6；
Figure 21 is the profile along dotted line B of step 6；
Figure 22 is the profile along dotted line C of step 6；
Figure 23 is the top view of step 7；
Figure 24 is the profile along dotted line A of step 7；
Figure 25 is the profile along dotted line B of step 7.
Description of reference numerals：
1st, monocrystalline silicon thin film；2nd, first kind impurity heavily doped region；3rd, the interchangeable intrinsic region a of source and drain；4th, the interchangeable intrinsic region of source and drain
b；5th, the second interchangeable area a of class impurity heavy doping source and drain；6th, the second interchangeable area b of class impurity heavy doping source and drain；7th, gate electrode is exhausted
Edge layer；8th, gate electrode；9th, the interchangeable electrode a of source and drain；10th, the interchangeable electrode b of source and drain；11st, insulated substrate layer；12nd, silicon substrate；
13rd, insulating medium barrier layer.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
As shown in Figure 1, Figure 2 and Figure 3, a kind of double bracket shape grid-control two-way switch tunneling transistor, the silicon substrate comprising SOI wafer
12, the top of silicon substrate 12 of SOI wafer is the insulated substrate layer 11 of SOI wafer, and the top of the insulated substrate layer 11 of SOI wafer is
Monocrystalline silicon thin film 1, first kind impurity heavily doped region 2, the interchangeable intrinsic region a 3 of source and drain, the interchangeable intrinsic region b 4, second of source and drain
The interchangeable area a 5 of class impurity heavy doping source and drain, the interchangeable area b 6 of the second class impurity heavy doping source and drain, grid electrode insulating floor 7, include
The subregion of number gate electrode 8 and insulating medium barrier layer 13；Wherein, first kind impurity heavily doped region 2 is located at monocrystalline silicon thin film 1
Center section, the interchangeable interchangeable area b 6 of class impurity heavy doping source and drain of area a 5 and second of the second class impurity heavy doping source and drain divide
Not Wei Yu the both sides monocrystalline silicon thin film 1 of first kind impurity heavily doped region 2 middle body, the second class impurity heavy doping source and drain is interchangeable
The upper table of the interchangeable area b 6 of class impurity heavy doping source and drain of area a 5 and second lower surface and the insulated substrate floor 11 of SOI wafer
Face contacts with each other；
The interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain is located at left and right sides of monocrystalline silicon thin film not respectively
The exterior lateral area of intentional doping process is carried out, it is miscellaneous to the second interchangeable classes of area a 5 and second of class impurity heavy doping source and drain respectively
The interchangeable area b 6 of matter heavy doping source and drain front and rear side and outside forms three bread and wrapped up in；
Grid electrode insulating layer 7 is insulating material, rectangular to be centered around the surrounding of monocrystalline silicon thin film 1, with monocrystalline silicon thin film 1 and first
The lateral wall of class impurity heavily doped region 2 contacts with each other, the intermediate region outer surface of the grid electrode insulating layer 7 of front and rear sides with absolutely
Edge dielectric barrier 13 contacts with each other, and the remainder of the outer surface of grid electrode insulating layer 7 contacts with each other with gate electrode 8；
Gate electrode 8 is made up of metal material or polycrystalline silicon material, the left and right sides part with the front and rear sides surface of grid electrode insulating layer 7
And left and right sides surface contacts with each other, i.e., gate electrode 8 with the surrounding outer surface of grid electrode insulating layer 7 except positioned at front and rear
Part outside the outer surface to be contacted with each other with insulating medium barrier layer 13 of the intermediate region of both side surface contacts with each other, grid
Electrode 8 overlooks viewing and forms a pair of double bracket shapes, and left and right ends three bread of formation of grid electrode insulating layer 7 are wrapped up in；Gate electrode
Insulating barrier 7 forms insulation barrier between gate electrode 8 and monocrystalline silicon thin film 1；The intrinsic region a 3 only interchangeable to source and drain of gate electrode 8
There is an obvious field-effect control action with the interchangeable intrinsic region b 4 of source and drain, and other regions to monocrystalline silicon thin film 1 and positioned at monocrystalline
The first kind impurity heavily doped region 2 of the middle body of silicon thin film 1 is without obvious control action；Monocrystalline silicon thin film 1, first kind impurity are heavily doped
Miscellaneous area 2, the interchangeable intrinsic region a 3 of source and drain, the interchangeable intrinsic region b 4 of source and drain, the second interchangeable area a 5 of class impurity heavy doping source and drain
A rectangle domain structure is combined into jointly with the second interchangeable area b 6 of class impurity heavy doping source and drain；Monocrystalline silicon thin film 1, the first kind are miscellaneous
The interchangeable intrinsic region a 3 of matter heavily doped region 2, source and drain, the interchangeable intrinsic region b 4 of source and drain, grid electrode insulating layer 7, bracket gate electrode 8
And the remainder that the upper surface of the SI semi-insulation dielectric barrier 13 on insulated substrate layer 11 is insulating medium barrier layer 13,
The interchangeable electrode a 9 of source and drain is located at the second interchangeable area a 5 of class impurity heavy doping source and drain top, and forms good Europe therewith
Nurse contacts；The interchangeable electrode b 10 of source and drain is located at the second interchangeable area b 6 of class impurity heavy doping source and drain top, and is formed therewith
Good Ohmic contact；The interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain outer surface respectively with dielectric
Barrier layer 13 is in contact, and insulated from each other by the barrier effect of insulating medium barrier layer 13.Whole transistor arrangement is located at
The part of the both sides of first kind impurity heavily doped region 2 is in symmetrical structure each other, can be mutual in the interchangeable electrode a 9 of source and drain and source and drain
Change in the case that electrode b 10 is symmetrically exchanged and realize same output characteristics.
The present invention provides a kind of double bracket shape grid-control two-way switch tunneling transistor, has symmetrical architectural feature,
Control the second class impurity heavy doping source and drain can by the voltage for adjusting the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain
Exchange the interchangeable area b 6 of the class impurity heavy doping source and drain of area a 5 and second and be used as source region or drain region, change tunnelling current direction, make
Device realizes the symmetrical interchangeable characteristic of source and drain of bidirectional tunneling conducting.
By first kind impurity heavily doped region 2 be N-type impurity exemplified by, when the interchangeable area a 5 of the second class impurity heavy doping source and drain,
When electrical potential difference be present between the second interchangeable area b 6 of class impurity heavy doping source and drain, and when gate electrode 8 is in negative pressure reverse-biased,
By gate electrode field-effect function influence, the interchangeable area a 5 of the second class impurity heavy doping source and drain can be to the interchangeable intrinsic region a 3 of source and drain
Offer hole, the interchangeable area b 6 of the second class impurity heavy doping source and drain can provide hole to the interchangeable intrinsic region b 4 of source and drain, therefore
Hole accumulation can be produced in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain so that source and drain is interchangeable intrinsic
Area a 3 and the interchangeable intrinsic region b 4 of source and drain now show p-type state, and the hole accumulated causes the interchangeable intrinsic region a of source and drain
The 3 and interchangeable intrinsic region b 4 of source and drain resistance decreases in the presence of gate electrode 8（I.e. source region, drain region are in low resistive state）, but
Now because the interchangeable intrinsic region a 3 of the source and drain for showing p-type feature is with being now that the first kind impurity heavily doped region 2 of N-type is leaking
Reverse-biased PN junction structure is formed under the voltage of source, and because first kind impurity heavily doped region 2 is not controlled by gate electrode 8, thus
Its conductivity type will not be changed due to the change of the voltage of gate electrode 8, therefore transistor is under reverse-biased, it is reverse-biased due to existing
PN junction structure, high resistant blocking state is integrally presented in transistor；The voltage being applied in gate electrode 8 is gradually increasing from negative voltage
To flat-band voltage, the second interchangeable area a 5 of class impurity heavy doping source and drain will not be provided greatly to the interchangeable intrinsic region a 3 of source and drain
Amount hole, the second interchangeable area b 6 of class impurity heavy doping source and drain will not provide a large amount of holes to the interchangeable intrinsic region b 4 of source and drain,
Simultaneously because now field strength is relatively low in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain, band curvature degree compared with
It is small, therefore will not also be produced between the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain conduction band and valence band big
Tunelling electrons hole pair is measured, therefore both can not form largely in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain
Hole is accumulated, and also can not form a large amount of electronics accumulations, the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b of source and drain of transistor
4 are in high-impedance state（I.e. source region and drain region are in high-impedance state）, therefore whole transistor does not have obvious electric current and flowed through, device
Part now has outstanding turn-off characteristic and Sub-Threshold Characteristic；The voltage being applied in gate electrode 8 is further by flat-band voltage
Forward bias condition is risen to, now by gate electrode 8 in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain
Effect function influence, it may appear that larger electric-field intensity and stronger band curvature, therefore obvious tunnel-effect can occur so that source
Leak and a large amount of electron hole pairs are formed in the interchangeable intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain, wherein as source region one end
Hole caused by the interchangeable intrinsic region of source and drain can discharge via the interchangeable area of the second class impurity heavy doping source and drain at the end, be produced
Raw electrons flow to the interchangeable intrinsic region of source and drain as drain region one end via first kind impurity heavily doped region 2, and as leakage
The valence band hole as caused by tunnel-effect occurs compound in the interchangeable intrinsic region of source and drain of area one end.And as drain region one end
Conduction band electron can be via the second class impurity heavy doping as drain region as caused by tunnel-effect in the interchangeable intrinsic region of source and drain
The interchangeable area of source and drain, it is compound with the generation of its valence band hole, continuous conducting electric current is formed by above-mentioned physical process.Due to tunnel
Concentration of electron-hole pairs caused by effect can gradually rise as gate electrode 8 is applied in the rising of voltage, when tunnel is imitated
When answering caused concentration of electron-hole pairs increase to a certain extent, transistor transits to forward conduction shape by sub-threshold status
State.
To reach device function of the present invention, the present invention proposes a kind of double bracket shape grid-control two-way switch tunnelling crystal
Pipe, its core texture are characterized as：
To reach device function of the present invention, the present invention proposes a kind of double bracket shape grid-control two-way switch tunnelling crystal
Pipe, its core texture are characterized as：
Device of the present invention is a kind of double bracket shape grid-control two-way switch tunneling transistor, the structure of double bracket grid, works as grid
When electrode 8 is in positively biased state, in contrast to planar structure, the electric-field intensity near gate electrode corner region can be added
By force, the probability for causing to produce carrier increases under equal gate voltage so that subthreshold swing has declined, forward conduction electric current
Increase；Device of the present invention is a kind of double bracket shape grid-control two-way switch tunneling transistor, first kind impurity heavy doping
The both sides of the part of insulating medium barrier layer 13 of area 2 and its top are in symmetrical structure.First kind impurity heavily doped region 2 and the second class
The interchangeable area a 5 of impurity heavy doping source and drain, first kind impurity heavily doped region 2 and the second interchangeable area b of class impurity heavy doping source and drain
6 have opposite impurity type respectively.When the gate electrode to both sides applies backward voltage simultaneously, in the top of monocrystalline silicon thin film 1
Both sides and the near surface that grid electrode insulating layer 7 contacts have accumulated largely with the second class impurity heavily doped region majority carrier type
Identical carrier, these are with the second class impurity heavily doped region majority carrier type identical carrier in drain electrode voltage
The interchangeable intrinsic region of source and drain is flowed through under effect and reaches first kind impurity heavily doped region 2, and in first kind impurity heavily doped region 2 and the
The majority carrier of a kind of impurity heavily doped region（It is opposite with conduction type）Generation is compound, due to first kind impurity heavily doped region 2
For high-dopant concentration region, it is sufficient to by these and the second class impurity heavily doped region majority current-carrying from the interchangeable intrinsic region of source and drain
Subtype identical carrier almost completely it is compound fall, and due to the interchangeable intrinsic region of source and drain as source region side and the first kind
Reverse-biased high-impedance state is between impurity heavily doped region 2, therefore now will not produce obvious electric current on source and drain direction and produce,
This structure significantly reduces the reverse leakage current of tunnelling type field-effect transistor, and it is higher just that device is obtained
Reverse current ratio.Due to symmetrical structure possessed by device of the present invention, by controlling the interchangeable electrode a 9 of source and drain and source and drain
It is interchangeable that interchangeable electrode b 10 switches the interchangeable class impurity heavy doping source and drain of area a 5 and second of the second class impurity heavy doping source and drain
Area b 6 is used as source region or drain region, can't influence the output characteristics of device, therefore can realize such as the source of MOSFETs devices
Leak interchangeable two-way switch characteristic.Grid electrode insulating layer 7 is the insulation material layer for producing tunnelling current.
A kind of tool of the unit of double bracket shape grid-control two-way switch tunneling transistor proposed by the invention in SOI wafer
Body manufacturing technology steps are as follows：
Step 1：As shown in Figure 4, Figure 5 and Figure 6, there is provided a SOI wafer, bottom are the silicon substrate 12 of SOI wafer, and silicon serves as a contrast
It is insulated substrate layer 11 above bottom, the upper surface of insulated substrate layer 11 is monocrystalline silicon thin film 1, passes through ion implanting or diffusion work
Skill, the intermediate region doping of the monocrystalline silicon thin film 1 above SOI wafer, preliminarily forms first kind impurity heavily doped region 2；
Step 2：As shown in Figure 7, Figure 8 and Figure 9, part monocrystalline silicon thin film 1 is removed by photoetching, etching technics and the first kind is miscellaneous
Matter heavily doped region 2, monocrystalline silicon thin film 1 and first kind impurity heavily doped region 2 are further formed in SOI wafer；
Step 3：As shown in Figure 10, Figure 11 and Figure 12, by the technique such as aoxidizing or depositing, etch, in monocrystalline silicon thin film 1 and
The outside of a kind of impurity heavily doped region 2 forms grid electrode insulating layer 7；
Step 4：As shown in Figure 13, Figure 14 and Figure 15, by depositing technics, the superstructure electrode formed in step 3 is exhausted
Edge medium, after planarizing surface, by etching technics, on the outside of the center section for only retaining the front and rear sides of grid electrode insulating layer 7
Dielectric, preliminarily form insulating medium barrier layer 13；
Step 5：As shown in Figure 16, Figure 17 and Figure 18, by depositing technics, in the upper surface of remaining insulated substrate layer 11, it is close to
Grid electrode insulating layer 7, metal or polysilicon are deposited, gate electrode 8 is formed after planarizing surface；
Step 6：As shown in Figure 19, Figure 20, Figure 21 and Figure 22, by ion implantation technology, to the monocrystalline silicon thin film of the left and right sides
1 intermediate region is doped, and forms the interchangeable class impurity heavy doping source and drain of area a 5 and second of the second class impurity heavy doping source and drain
Interchangeable area a 6；
Step 7：As shown in Figure 23, Figure 24 and Figure 25, by oxidation or depositing technics, in the upper of the structure that step 6 is formed
Surface deposition dielectric, planarize surface after again by photoetching, etching technics, it is interchangeable to the second class impurity heavy doping source and drain
The interchangeable area b 6 of class impurity heavy doping source and drain of area a 5 and second top performs etching, and forms through hole, and it is miscellaneous to expose the second class
The interchangeable interchangeable area b 6 of class impurity heavy doping source and drain of area a 5 and second of matter heavy doping source and drain upper surface is exhausted to ultimately form
The remainder of edge dielectric barrier 13, then inject metal to through hole into the through hole of formation and be completely filled, planarize surface
The interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain is formed afterwards.
Claims (2)
1. a kind of double bracket shape grid-control two-way switch tunneling transistor, the silicon substrate comprising SOI wafer（12）, it is characterised in that：
The silicon substrate of SOI wafer（12）Top is the insulated substrate layer of SOI wafer（11）, the insulated substrate layer of SOI wafer（11）It is upper
Side is monocrystalline silicon thin film（1）, first kind impurity heavily doped region（2）, the interchangeable intrinsic region a of source and drain（3）, the interchangeable intrinsic region of source and drain
b（4）, the second interchangeable area a of class impurity heavy doping source and drain（5）, the second interchangeable area b of class impurity heavy doping source and drain（6）, gate electrode
Insulating barrier（7）, bracket gate electrode（8）And insulating medium barrier layer（13）Subregion；
Wherein, first kind impurity heavily doped region（2）Positioned at monocrystalline silicon thin film（1）Center section, the second class impurity heavy-doped source
Leak interchangeable area a（5）With the second interchangeable area b of class impurity heavy doping source and drain（6）It is located at first kind impurity heavily doped region respectively（2）
Both sides monocrystalline silicon thin film（1）Middle body, the second interchangeable area a of class impurity heavy doping source and drain（5）It is heavily doped with the second class impurity
The miscellaneous interchangeable area b of source and drain（6）Lower surface and SOI wafer insulated substrate layer（11）Upper surface contact with each other；
The interchangeable intrinsic region a of source and drain（3）With the interchangeable intrinsic region b of source and drain（4）It is located at monocrystalline silicon thin film respectively（1）The left and right sides is not
The exterior lateral area of intentional doping process is carried out, respectively to the second interchangeable area a of class impurity heavy doping source and drain（5）It is miscellaneous with the second class
The interchangeable area b of matter heavy doping source and drain（6）Front and rear side and outside formed three bread wrap up in；
Grid electrode insulating layer（7）It is rectangular to be centered around monocrystalline silicon thin film for insulating material（1）Surrounding, with monocrystalline silicon thin film（1）
With first kind impurity heavily doped region（2）Lateral wall contact with each other, the grid electrode insulating layer of front and rear sides（7）Intermediate region outside
Side surface and insulating medium barrier layer（13）Contact with each other, grid electrode insulating layer（7）Outer surface remainder and grid
Electrode（8）Contact with each other；
Gate electrode（8）It is made up of metal material or polycrystalline silicon material, with grid electrode insulating layer（7）Front and rear sides surface left and right
Two side portions and left and right sides surface contact with each other, i.e. gate electrode（8）With grid electrode insulating layer（7）Surrounding outer surface
Except the intermediate region and insulating medium barrier layer positioned at front and rear sides surface（13）Outside the outer surface to contact with each other
Part contacts with each other, gate electrode（8）Overlook viewing and form a pair of double bracket shapes, to grid electrode insulating layer（7）Left and right ends
Three bread are formed to wrap up in；Grid electrode insulating layer（7）In gate electrode（8）And monocrystalline silicon thin film（1）Between form insulation barrier；Gate electrode
（8）Intrinsic region a only interchangeable to source and drain（3）With the interchangeable intrinsic region b of source and drain（4）There is obvious field-effect control action, and to list
Polycrystal silicon film（1）Other regions and positioned at monocrystalline silicon thin film（1）The first kind impurity heavily doped region of middle body（2）Without obvious
Control action；Monocrystalline silicon thin film（1）, first kind impurity heavily doped region（2）, the interchangeable intrinsic region a of source and drain（3）, source and drain it is interchangeable
Intrinsic region b（4）, the second interchangeable area a of class impurity heavy doping source and drain（5）With the second interchangeable area b of class impurity heavy doping source and drain（6）
A rectangle domain structure is combined into jointly；Monocrystalline silicon thin film（1）, first kind impurity heavily doped region（2）, the interchangeable intrinsic region a of source and drain
（3）, the interchangeable intrinsic region b of source and drain（4）, grid electrode insulating layer（7）, bracket gate electrode（8）And insulated substrate layer（11）On
SI semi-insulation dielectric barrier（13）Upper surface be insulating medium barrier layer（13）Remainder, the interchangeable electrode a of source and drain
（9）Positioned at the second interchangeable area a of class impurity heavy doping source and drain（5）Top, and form good Ohmic contact therewith；Source and drain can
Staggered poles b（10）Positioned at the second interchangeable area b of class impurity heavy doping source and drain（6）Top, and form good ohm therewith
Contact；The interchangeable electrode a of source and drain（9）With the interchangeable electrode b of source and drain（10）Outer surface respectively with insulating medium barrier layer
（13）It is in contact, and passes through insulating medium barrier layer（13）Barrier effect it is insulated from each other；Whole transistor arrangement positioned at the
A kind of impurity heavily doped region（2）The part of both sides is in symmetrical structure each other, can be in the interchangeable electrode a of source and drain（9）Can with source and drain
Staggered poles b（10）Same output characteristics is realized in the case of symmetrical exchange.
A kind of 2. manufacture method of double bracket shape grid-control two-way switch tunneling transistor as claimed in claim 1, it is characterised in that：
Its manufacturing step is as follows：
Step 1：A SOI wafer is provided, bottom is the silicon substrate of SOI wafer（12）, it is insulated substrate above silicon substrate
Layer（11）, insulated substrate layer（11）Upper surface be monocrystalline silicon thin film（1）, by ion implanting or diffusion technique, to SOI wafer
The monocrystalline silicon thin film of top（1）Intermediate region doping, preliminarily form first kind impurity heavily doped region（2）；
Step 2：Part monocrystalline silicon thin film is removed by photoetching, etching technics（1）With first kind impurity heavily doped region（2）,
Monocrystalline silicon thin film is further formed in SOI wafer（1）With first kind impurity heavily doped region（2）；
Step 3：By the technique such as aoxidizing or depositing, etch, in monocrystalline silicon thin film（1）With first kind impurity heavily doped region（2）'s
Outside forms grid electrode insulating layer（7）；
Step 4：By depositing technics, the superstructure electrode insulation medium formed in step 3, after planarizing surface, lead to
Over etching technique, only retain grid electrode insulating layer（7）Dielectric on the outside of the center section of front and rear sides, preliminarily form insulation
Dielectric barrier（13）；
Step 5：By depositing technics, in remaining insulated substrate layer（11）Upper surface, be close to grid electrode insulating layer（7）, deposit
Metal or polysilicon, gate electrode is formed after planarizing surface（8）；
Step 6：By ion implantation technology, to the monocrystalline silicon thin film of the left and right sides（1）Intermediate region be doped, formed
The second interchangeable area a of class impurity heavy doping source and drain（5）With the second interchangeable area b of class impurity heavy doping source and drain（6）；
Step 7：By oxidation or depositing technics, dielectric, planarization are deposited in the upper surface for the structure that step 6 is formed
Pass through photoetching, etching technics, the second interchangeable area a of class impurity heavy doping source and drain behind surface again（5）With the second class impurity heavy doping
The interchangeable area b of source and drain（6）Top perform etching, and form through hole, expose the second interchangeable area a of class impurity heavy doping source and drain
（5）With the second interchangeable area b of class impurity heavy doping source and drain（6）Upper surface to ultimately form insulating medium barrier layer（13）Its
Remaining part point, then inject metal to through hole into the through hole of formation and be completely filled, form the interchangeable electricity of source and drain after planarizing surface
Pole a（9）With the interchangeable electrode b of source and drain（10）.
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| CN104485354A (en) * | 2014-12-08 | 2015-04-01 | 沈阳工业大学 | SOI (Silicon on Insulator) substrate folding grid insulating tunneling enhanced transistor and manufacturing method thereof |
| CN105390531A (en) * | 2015-10-27 | 2016-03-09 | 北京大学 | Method for preparing tunneling field effect transistor |
| US20170213836A1 (en) * | 2015-03-31 | 2017-07-27 | Stmicroelectronics, Inc. | Vertical gate-all-around tfet |
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| CN104485354A (en) * | 2014-12-08 | 2015-04-01 | 沈阳工业大学 | SOI (Silicon on Insulator) substrate folding grid insulating tunneling enhanced transistor and manufacturing method thereof |
| US20170213836A1 (en) * | 2015-03-31 | 2017-07-27 | Stmicroelectronics, Inc. | Vertical gate-all-around tfet |
| CN105390531A (en) * | 2015-10-27 | 2016-03-09 | 北京大学 | Method for preparing tunneling field effect transistor |
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