CN107819029B - Potential barrier regulation type H-shaped grid-controlled bidirectional tunneling transistor and manufacturing method thereof - Google Patents
Potential barrier regulation type H-shaped grid-controlled bidirectional tunneling transistor and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The device has the structural characteristics of an H-shaped gate electrode, a barrier adjusting gate and bilateral symmetry, has stronger gate control capability, and can control a metal source-drain interchangeable area to be used as a source area or a drain area by adjusting the voltage of the source-drain interchangeable electrode so as to change the tunneling current direction. The invention has the advantages of low static power consumption, reverse leakage current, stronger grid control capability, low subthreshold swing and capability of realizing the function of bidirectional switch. Compared with the common Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), the device realizes more excellent switching characteristic by utilizing the tunneling effect; compared with the common tunneling field effect transistor, the bidirectional symmetrical switch has the bidirectional symmetrical switch characteristic that the common tunneling field effect transistor does not have source and drain interchangeable, so that the bidirectional symmetrical switch is suitable for popularization and application.
Description
Technical Field
The invention relates to the field of manufacturing of super-large-scale integrated circuits, in particular to a potential barrier regulation type H-shaped gate-controlled bidirectional tunneling transistor with low leakage current and suitable for manufacturing of low-power-consumption integrated circuits and a manufacturing method thereof.
Background
The basic unit MOSFETs of integrated circuits are becoming smaller and smaller in size according to moore's law, and not only are difficulties in manufacturing process deepened, but various adverse effects are becoming more and more prominent. The mosfet devices used in integrated circuit designs today cannot have a subthreshold swing below 60mV/dec due to the physical limitations of their own current generation during operation. When the common tunneling field effect transistor is used as a switch-type device, the tunneling effect of current carriers between semiconductor energy bands is used as a conduction mechanism of current, and the subthreshold swing is obviously superior to the 60mv/dec limit of an MOSFET device. However, the source region and the drain region of the ordinary tunneling field effect transistor adopt impurities with different conductivity types, and the asymmetric structural characteristics cause that the ordinary tunneling field effect transistor cannot completely replace the MOSFETs devices with symmetric structural characteristics in function. Taking the N-type tunneling field effect transistor as an example, if the source and the drain are interchanged, that is, the drain is at a low potential and the source is at a high potential, the tunneling field effect transistor will be always in a conducting state, and the magnitude of the conducting current can no longer be well controlled and adjusted depending on the gate electrode, which makes the switching characteristic of the whole tunneling field effect transistor invalid.
Disclosure of Invention
The purpose of the invention is as follows:
in order to effectively combine and utilize the advantages of source electrode and drain electrode interchangeability of the MOSFETs and low subthreshold swing of the common tunneling field effect transistor and solve the defects that the subthreshold swing of the MOSFETs cannot be reduced and the common tunneling field effect transistor can only be used as a one-way switch, the invention provides a barrier regulation type H-shaped grid-control bidirectional tunneling transistor and a manufacturing method thereof. The transistor has the advantage that the logic function is completely compatible with the current integrated circuit based on the MOSFETs, the source-drain two-end structure symmetry enables the transistor to realize the function of source-drain bidirectional symmetrical switch through voltage interchange of the source electrode and the drain electrode, namely the transistor has the bidirectional switch characteristic that the source-drain electrode is interchangeable, and in addition, the transistor also has the working characteristics of high forward-reverse current ratio, low subthreshold swing, high forward-direction conducting current and the like.
The technical scheme is as follows:
the invention is realized by the following technical scheme:
a potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor comprises a silicon substrate of an SOI wafer, a substrate insulating layer of the SOI wafer is arranged above the silicon substrate of the SOI wafer, a monocrystalline silicon film, a potential barrier regulation grid, a grid electrode insulating layer and partial regions of an insulating medium barrier layer are arranged above the substrate insulating layer of the SOI wafer, the monocrystalline silicon film has the geometrical characteristic of a concave shape and is characterized in that the impurity concentration is lower than 1016cm-3The monocrystalline silicon semiconductor material of (1), wherein gate electrode insulating layers are attached to the inner side surface and the front and rear outer side surfaces of a groove-shaped structure formed by the monocrystalline silicon film; the heavily doped source/drain interchangeable region a and the heavily doped source/drain interchangeable region b are formed by doping the middle parts above the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film, and the peak concentration of impurities is not lower than 1018cm-3(ii) a The front and back surfaces and the inner side surface of the heavily doped source-drain interchangeable region a and the source-drain can mutuallyThe intrinsic regions a are mutually contacted and surrounded by three surfaces of the intrinsic regions a; the front surface, the back surface and the inner side surface of the heavily doped source-drain interchangeable region b are mutually contacted with the source-drain interchangeable intrinsic region b and are surrounded by the three surfaces of the heavily doped source-drain interchangeable region b; the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b are respectively positioned in the inner side regions which are not subjected to the intentional doping process and have impurity concentration lower than 10 at the upper ends of the vertical parts at the two sides of the groove-shaped structure of the monocrystalline silicon film16cm-3The single crystal silicon semiconductor material of (a); the monocrystalline silicon film, the source-drain interchangeable intrinsic region a, the source-drain interchangeable intrinsic region b, the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b jointly form a groove-shaped structure; the gate electrode insulating layers are positioned on the upper surface and the front and back surfaces of the horizontal part at the bottom of the groove-shaped structure formed by the monocrystalline silicon film and the inner side surfaces and the front and back surfaces of the vertical parts at two sides of the groove-shaped structure of the monocrystalline silicon film; the H-shaped gate electrode is made of metal materials or polycrystalline silicon materials, three surfaces of the inner side surface and the front and back surfaces of the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film are wrapped, the SOI wafer is overlooked, the H-shaped gate electrode is in an H shape of English capital letter along the source-drain direction, the H-shaped gate electrode and the groove-shaped structure of the monocrystalline silicon film are insulated with each other through a gate electrode insulating layer, the H-shaped gate electrode only has a field effect control effect on the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film, and has no obvious field effect control effect on the lower areas of the vertical parts at two sides and the bottom horizontal; the barrier control gate is made of metal materials or polycrystalline silicon materials, is positioned on the upper surface and the front and back surfaces of the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon film, forms three-surface wrapping on the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon film, and is insulated and isolated from the monocrystalline silicon film through a gate electrode insulating layer, the barrier control gate only has a field effect control function on the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon film, and has no obvious field effect control function on the upper parts of the two side vertical parts of the groove-shaped structure formed by the monocrystalline silicon film; an H-shaped gate electrode is located below the inner side of the groove-shaped structure formed by the monocrystalline silicon filmA partial region with an insulating medium blocking layer is arranged between the surface and the barrier control gate, and the H-shaped gate electrode and the barrier control gate are insulated and isolated from each other through the insulating medium blocking layer; the source-drain interchangeable electrode a is made of metal materials and is positioned above the heavily doped source-drain interchangeable region a; the source-drain interchangeable electrode b is also made of metal materials and is positioned above the heavily doped source-drain interchangeable region b, and the three electrodes, namely the source-drain interchangeable electrode a, the source-drain interchangeable electrode b and the H-shaped gate electrode, are insulated from each other through an insulating medium barrier layer; the left side and the right side of the barrier control gate are of a symmetrical structure, and the same output characteristic can be realized under the condition that the source-drain interchangeable electrode a and the source-drain interchangeable electrode b are symmetrically interchanged.
The specific manufacturing steps of the preparation method of the barrier regulation type H-shaped grid-control bidirectional tunneling transistor are as follows:
the method comprises the following steps: providing an SOI wafer, wherein the lowest part of the SOI wafer is a silicon substrate of the SOI wafer, a substrate insulating layer is arranged on the silicon substrate, a monocrystalline silicon thin film is arranged on the upper surface of the substrate insulating layer, the monocrystalline silicon thin film on the SOI wafer is etched through photoetching or etching technology, the monocrystalline silicon thin films on the front side, the rear side and the middle part of the area are removed, and the monocrystalline silicon thin film with groove-shaped structural characteristics is formed;
step two: forming gate electrode insulating layers on the front and back outer side surfaces of a groove-shaped structure formed by the monocrystalline silicon film, the inner side surfaces of the vertical parts at two sides of the groove and the upper surface of the horizontal part at the bottom of the groove through oxidation or deposition and etching processes;
step three: depositing an insulating medium above the SOI wafer, flattening until the surface exposes the monocrystalline silicon film, and preliminarily forming an insulating medium barrier layer;
step four: etching partial insulating medium barrier layers which are formed in the third step and are positioned on the front surface and the rear surface of the horizontal part at the bottom of the monocrystalline silicon film groove structure until the gate electrode insulating layer is exposed, and further forming the insulating medium barrier layers;
step five: depositing metal or polysilicon on the SOI wafer by a deposition process, flattening the surface until the monocrystalline silicon film is exposed, and preliminarily forming a potential barrier regulation gate;
step six: etching off an insulating medium blocking layer above a horizontal part at the bottom of a groove structure formed by a monocrystalline silicon film by an etching process until a gate electrode insulating layer is exposed, depositing metal or polycrystalline silicon above an SOI wafer by a deposition process, flattening the surface until the monocrystalline silicon film is exposed, and further forming a potential barrier regulating gate;
step seven: etching the upper region of the barrier control gate formed in the sixth step by an etching process to further form the barrier control gate;
step eight: depositing an insulating medium above the SOI wafer, flattening the surface until the monocrystalline silicon film is exposed, and further forming an insulating medium barrier layer;
step nine: carrying out partial etching on the partial insulating medium barrier layer formed in the step eight by photoetching or etching technology, depositing metal or polysilicon above the SOI wafer, and flattening the surface until the monocrystalline silicon film is exposed to form an H-shaped gate electrode;
step ten: doping the middle outer parts of the upper surfaces of the vertical parts on the two sides of the groove structure formed by the monocrystalline silicon film through an ion implantation process to form a heavily doped source-drain interchangeable region a and a heavily doped source-drain interchangeable region b;
step eleven: depositing an insulating medium above the SOI wafer through a deposition process to form an insulating medium barrier layer of the rest part; and after the surface is flattened, removing the insulating medium barrier layer above the heavily doped source-drain interchangeable area a and the heavily doped source-drain interchangeable area b through an etching process until the upper surfaces of the heavily doped source-drain interchangeable area a and the heavily doped source-drain interchangeable area b are exposed, injecting metal into the etched through hole through a deposition process until the through hole is completely filled, and finally flattening the surface to form a source-drain interchangeable electrode a and a source-drain interchangeable electrode b.
The advantages and effects are as follows:
the invention has the following advantages and beneficial effects:
1. source and drain symmetric interchangeable bidirectional switch characteristics;
the device is a potential barrier regulation type H-shaped grid control bidirectional tunneling transistor, the left end and the right end of a monocrystalline silicon film are respectively provided with mutually independent tunneling structures, the device is provided with a bilateral symmetry structure, tunneling occurs at the left end and the right end of the monocrystalline silicon film near the surface contacting with a grid electrode insulating layer under the control action of an H-shaped grid electrode, the device forms forward conduction and reverse blocking by combining the regulation action of the potential barrier regulation and control gate on the middle part of the monocrystalline silicon film, and the heavily doped source-drain interchangeable area a and the heavily doped source-drain interchangeable area b are controlled to be used as a source area or a drain area by regulating the voltage of a source-drain interchangeable electrode a and a source-drain interchangeable electrode b, so that the tunneling current direction can be changed, and the source-drain symmetric interchangeable bidirectional switching characteristic of.
2. A low sub-threshold swing;
because the band-band tunneling effect is used as the conduction mechanism of the field effect transistor, under the control action of the H-shaped grid electrode, the energy band is easier to bend under the same grid voltage, the tunneling current is adjusted, and the sub-threshold swing amplitude is lower than that of an MOSFET device.
3. Low static power consumption, low reverse leakage current and high forward-reverse current ratio;
taking the conduction type as an N type as an example, the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b are doped in a P type at the moment, when a potential difference exists between the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b, and when the H-shaped gate electrode is in a subthreshold or reverse bias state, because the barrier control gate always works in a forward bias state, the potentials of the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b positioned at two sides of the monocrystalline silicon film are lower than the potential of the control part of the barrier control gate at the middle part of the monocrystalline silicon film, holes accumulated in the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b and holes in the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b under the control of the field effect of the H-shaped gate electrode cannot form a barrier through the part controlled by, compared with the common MOSFETs or tunnel field effect transistor structure, a region with stronger field intensity between the drain electrode and the gate electrode does not exist, namely a large number of electron-hole pairs formed by the tunnel effect are not formed, and due to the auxiliary control function of the barrier regulating gate, the potential barrier formed in the middle part of the monocrystalline silicon film can effectively block the formation of hole current between the heavily doped source-drain interchangeable region a and the heavily doped source-drain interchangeable region b and between the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b. Therefore, the invention has the advantages of low static power consumption, low reverse leakage current and high forward-reverse current ratio.
Drawings
FIG. 1 is a top view of a barrier modulated H-gate bidirectional tunneling transistor according to the present invention;
FIG. 2 is a cross-sectional view along the dotted line A of a barrier-modulated H-gate bidirectional tunneling transistor according to the present invention;
FIG. 3 is a cross-sectional view along the dotted line B of a barrier-modulated H-gate bidirectional tunneling transistor according to the present invention;
FIG. 4 is a top view of step one;
FIG. 5 is a cross-sectional view along dotted line A of step one;
FIG. 6 is a cross-sectional view taken along dotted line B of step one;
FIG. 7 is a cross-sectional view taken along dashed line C of step one;
FIG. 8 is a top view of step two;
FIG. 9 is a cross-sectional view taken along dotted line A of step two;
FIG. 10 is a cross-sectional view taken along the dashed line B in step two;
FIG. 11 is a cross-sectional view taken along dotted line C of step two;
FIG. 12 is a cross-sectional view taken along the dashed line D in step two;
FIG. 13 is a cross-sectional view taken along the dashed line E in step two;
FIG. 14 is a top view of step three;
FIG. 15 is a cross-sectional view taken along dotted line A of step three;
FIG. 16 is a cross-sectional view taken along dotted line B of step three;
FIG. 17 is a cross-sectional view taken along dotted line C of step three;
FIG. 18 is a cross-sectional view taken along dotted line D of step three;
FIG. 19 is a cross-sectional view taken along dotted line E of step three;
FIG. 20 is a top view of step four;
FIG. 21 is a cross-sectional view taken along dotted line A of step four;
FIG. 22 is a cross-sectional view taken along dotted line B of step four;
FIG. 23 is a top view of step five;
FIG. 24 is a cross-sectional view taken along dotted line A of step five;
FIG. 25 is a cross-sectional view taken along dotted line B of step five;
FIG. 26 is a top view of step six;
FIG. 27 is a cross-sectional view taken along dotted line A for step six;
FIG. 28 is a cross-sectional view taken along dotted line B for step six;
FIG. 29 is a cross-sectional view taken along dotted line C of step six;
FIG. 30 is a top view of step seven;
FIG. 31 is a cross-sectional view taken along dotted line A of step seven;
FIG. 32 is a cross-sectional view taken along dotted line B of step seven;
FIG. 33 is a cross-sectional view taken along dotted line C of step seven;
FIG. 34 is a top view of step eight;
FIG. 35 is a cross-sectional view taken along dotted line A of step eight;
FIG. 36 is a cross-sectional view taken along dotted line B of step eight;
FIG. 37 is a cross-sectional view taken along dashed line C of step eight;
FIG. 38 is a top view of step nine;
FIG. 39 is a cross-sectional view taken along dotted line A of step nine;
FIG. 40 is a cross-sectional view taken along dotted line B of step nine;
FIG. 41 is a cross-sectional view taken along dotted line C of step nine;
FIG. 42 is a top view of step ten;
FIG. 43 is a cross-sectional view taken along dotted line A of step ten;
FIG. 44 is a cross-sectional view taken along dashed line B of step ten;
FIG. 45 is a top view of step eleven;
FIG. 46 is a cross-sectional view taken along dotted line A of step eleven;
fig. 47 is a sectional view along a broken line B of step eleven.
Description of reference numerals:
1. a single crystal silicon thin film; 2. a barrier control gate; 3. the source and the drain can exchange an intrinsic region a; 4. the source and the drain can exchange the intrinsic region b; 5. heavily doped source-drain interchangeable region a; 6. heavily doped source-drain interchangeable region b; 7. a gate electrode insulating layer; 8. an H-shaped gate electrode; 9. the source-drain interchangeable electrode a; 10. a source-drain interchangeable electrode b; 11. a substrate insulating layer; 12. a silicon substrate; 13. an insulating dielectric barrier layer.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
as shown in FIG. 1, FIG. 2 and FIG. 3, a barrier-modulated H-shaped gate-controlled bidirectional tunneling transistor comprises a silicon substrate 12 of an SOI wafer, a substrate insulating layer 11 of the SOI wafer is arranged above the silicon substrate 12 of the SOI wafer, a monocrystalline silicon thin film 1, a barrier-modulated gate 2, a gate electrode insulating layer 7 and partial regions of an insulating medium barrier layer 13 are arranged above the substrate insulating layer 11 of the SOI wafer, the monocrystalline silicon thin film 1 has a concave-shaped geometrical characteristic and has an impurity concentration lower than 1016cm-3The monocrystalline silicon semiconductor material of (1), the inner side surface and the front and back outer side surfaces of the groove-shaped structure formed by the monocrystalline silicon film are attached with gate electrode insulating layers (7); the heavily doped source/drain interchangeable region a5 and the heavily doped source/drain interchangeable region b6 are formed by doping the middle parts of the vertical parts at the two sides of the groove-shaped structure formed by the monocrystalline silicon film 1, and the peak concentration of impurities is not lower than 1018cm-3(ii) a The front surface, the back surface and the inner side surface of the heavily doped source-drain interchangeable region a5 are mutually contacted with the source-drain interchangeable intrinsic region a3 and are surrounded by the three surfaces; the front surface, the back surface and the inner side surface of the heavily doped source-drain interchangeable region b6 are in contact with the source-drain interchangeable intrinsic region b 4 and are surrounded by the three surfaces; the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4 are respectively positioned in the inner side regions which are not subjected to the intentional doping process and are at the upper ends of the vertical parts at the two sides of the groove-shaped structure of the monocrystalline silicon film 1, and the impurity concentration of the inner side regions is lower than 1016cm-3The single crystal silicon semiconductor material of (a); the monocrystalline silicon film 1, the source-drain interchangeable intrinsic region a3, the source-drain interchangeable intrinsic region b 4, the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 jointly form a groove-shaped structure; the gate electrode insulating layers 7 are positioned on the upper surface and the front and back surfaces of the horizontal part at the bottom of the groove-shaped structure formed by the monocrystalline silicon film 1 and the inner side surfaces and the front and back surfaces of the vertical parts at two sides of the groove-shaped structure of the monocrystalline silicon film 1; the H-shaped gate electrode 8 is made of metal materials or polycrystalline silicon materials, three surfaces of the inner side surface and the front and back surfaces of the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film 1 are wrapped, the SOI wafer is overlooked, the H-shaped gate electrode 8 is in an H shape of English capital letter along the source-drain direction, the H-shaped gate electrode 8 and the groove-shaped structure of the monocrystalline silicon film 1 are insulated with each other through a gate electrode insulating layer 7, the H-shaped gate electrode 8 only has a field effect control effect on the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film 1, and has no obvious field effect control effect on the lower areas and the bottom horizontal part areas of the vertical parts at two; the barrier control grid 2 is made of metal materials or polycrystalline silicon materials, is positioned on the upper surface and the front and back surfaces of the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon film 1, forms three-surface wrapping on the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon film 1, and is insulated and isolated from the monocrystalline silicon film 1 through a grid electrode insulating layer 7, the barrier control grid 2 only has a field effect control function on the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon film 1, and has no obvious field effect control function on the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film 1; the H-shaped gate electrode 8 is positioned in a partial area with an insulating medium barrier layer 13 between the lower surface of the part of the inner side of the groove-shaped structure formed by the monocrystalline silicon film 1 and the barrier control gate 2, and the H-shaped gate electrode 8 and the barrier control gate 2 are insulated and isolated from each other through the insulating medium barrier layer 13; the source-drain interchangeable electrode a 9 is made of metal materials and is positioned above the heavily doped source-drain interchangeable region a 5; the source/drain interchangeable electrode b10 is also made of a metal material and is located in the heavily doped source/drain interchangeable region b6The source-drain interchangeable electrode a 9, the source-drain interchangeable electrode b10 and the H-shaped gate electrode 8 are insulated from each other by an insulating dielectric barrier layer 13; the left side and the right side of the barrier control gate 2 are in a symmetrical structure, and the same output characteristics can be realized under the condition that the source-drain interchangeable electrode a 9 and the source-drain interchangeable electrode b10 are symmetrically interchanged.
The invention provides a potential barrier regulation type H-shaped grid-controlled bidirectional tunneling transistor which has structural characteristics of left-right symmetry, wherein a heavily doped source-drain interchangeable region a5 and a heavily doped source-drain interchangeable region b6 are controlled to serve as a source region or a drain region by regulating the voltages of a source-drain interchangeable electrode a 9 and a source-drain interchangeable electrode b10, and the tunneling current direction is changed, so that the device realizes the source-drain symmetric interchangeable characteristic of bidirectional tunneling conduction. Taking the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 as P-type impurities as an example, when a potential difference exists between the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6, and when the H-shaped gate electrode 8 is in a negative pressure reverse bias state, influenced by the action of the H-shaped gate field effect, the heavily doped source-drain interchangeable region a5 will provide holes for the source-drain interchangeable intrinsic region a3, and the heavily doped source-drain interchangeable region b6 will provide holes for the source-drain interchangeable intrinsic region b 4, so that hole accumulation will occur in both the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4, so that the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4 both show a P-type state at this time, and the accumulated holes will make the resistance values of the source-drain interchangeable region a3 and the source-drain interchangeable intrinsic region b 4 decrease under the, namely, the source region and the drain region are both in a low resistance state, but because the barrier control gate 2 always applies a forward voltage, a potential barrier is formed for holes in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4 on both sides, and the holes in the heavily doped source-drain interchangeable area a5 and the heavily doped source-drain interchangeable area b6 on the two sides also form a potential barrier, under the influence of the forward voltage field effect applied by the barrier control grid 2, the middle part of the monocrystalline silicon film 1 controlled by the barrier control grid 2 can present an N-type semiconductor state, so that the source-drain interchangeable intrinsic region a3 showing P-type characteristics and the middle part of the monocrystalline silicon thin film 1 which is N-type at this time form a reverse-biased PN junction structure under the action of drain-source voltage, therefore, when the H-shaped gate electrode 8 is in a negative-pressure reverse-biased state, the transistor is in a high-resistance blocking state as the whole due to the reverse-biased PN junction structure in the transistor; along with the gradual rise of the applied voltage of the H-shaped gate electrode 8 from the negative voltage to the vicinity of the flat band voltage, the heavily doped source-drain interchangeable region a5 does not provide a large number of holes for the source-drain interchangeable intrinsic region a3, the heavily doped source-drain interchangeable region b6 does not provide a large number of holes for the source-drain interchangeable intrinsic region b 4, and simultaneously, because the field strength in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4 is low and the energy band bending degree is small, a large number of tunneling electron hole pairs are not generated between the conduction band and the valence band of the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4, so that a large number of holes and a large number of electrons are not accumulated in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4, and the source-drain interchangeable region a3 and the source-drain interchangeable intrinsic region b 4 of the transistor are both, namely, the source region and the drain region are in a high-resistance state, so that the whole transistor does not have obvious current flowing through, and the device has excellent turn-off characteristics and subthreshold characteristics; as the voltage applied to the H-shaped gate electrode 8 further increases from the flat band voltage to the forward bias state, the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4 are influenced by the field effect of the H-shaped gate electrode 8, and a large electric field strength and a strong band bending occur, thus, a significant tunneling effect occurs, so that a large number of electron-hole pairs are formed in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4, wherein holes generated by the source-drain interchangeable intrinsic region serving as one end of the source region are discharged through the heavily doped source-drain interchangeable region at the end, and generated electrons flow to the source-drain interchangeable intrinsic region serving as one end of the drain region through the N-type region formed at the middle part of the monocrystalline silicon thin film 1 controlled by the barrier control gate 2, recombination occurs with valence band holes generated by tunneling in the source-drain interchangeable intrinsic region, which is one end of the drain region. Conduction band electrons generated by the tunneling effect in the source-drain interchangeable intrinsic region serving as one end of the drain region are recombined with valence band holes of the heavily doped source-drain interchangeable region serving as the drain region, and continuous conduction current is formed through the physical process. The concentration of electron-hole pairs generated by the tunneling effect gradually increases with the increase in the voltage applied to the H-shaped gate electrode 8, and when the concentration of electron-hole pairs generated by the tunneling effect increases to a certain degree, the transistor transitions from the subthreshold state to the forward conduction state.
The device has structural characteristics of bilateral symmetry in the source-drain direction, so that the potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor is different from a common tunneling field effect transistor, and the source region and the drain region of the potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor can realize an interchange function.
In order to achieve the device function, the invention provides a potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor, which is characterized in that:
the device is a potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor, and two sides of the potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor are of symmetrical structures. The middle part of the monocrystalline silicon thin film 1 is controlled by the barrier control gate 2, and by setting the barrier control gate at a specific fixed voltage value, a barrier is formed for majority carriers in the heavy-doped source/drain interchangeable region, and the magnitude of leakage current in reverse bias and subthreshold states is suppressed. The middle part of the monocrystalline silicon film 1 controlled by the barrier control gate 2, the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 have carrier types with opposite polarities. Due to the symmetrical structure of the device, the heavily doped source-drain interchangeable area a5 and the heavily doped source-drain interchangeable area b6 are controlled to be used as a source area or a drain area by controlling the source-drain interchangeable electrode a 9 and the source-drain interchangeable electrode b10, so that the source-drain interchangeable bidirectional switch characteristic of the device is realized.
The device is a potential barrier regulation type H-shaped gate control bidirectional tunneling transistor, has an H-shaped gate electrode structure, is in mutual contact with the outer side surface of a gate electrode insulating layer 7, forms three-side surrounding on the gate electrode insulating layer 7, presents the characteristic of an English capital letter H-shaped structure when viewed from top, has obvious field effect control effect on the upper parts of two side vertical parts of a groove-shaped structure formed by a monocrystalline silicon film 1, namely a source-drain interchangeable intrinsic region a3 and a source-drain interchangeable intrinsic region b 4, and has the effect that when an H-shaped gate electrode 8 is in a forward bias state, compared with a plane structure, the electric field intensity near the corner region of the H-shaped gate electrode 8 is enhanced, so that the probability of generating carriers in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b 4 is increased under the same gate voltage, and the subthreshold swing amplitude is reduced, The forward conduction current increases;
the invention provides a method for preparing a potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor, which comprises the following specific manufacturing steps:
the method comprises the following steps: as shown in fig. 4, 5, 6 and 7, providing an SOI wafer, wherein a silicon substrate 12 of the SOI wafer is arranged at the lowest part, a substrate insulating layer 11 is arranged on the silicon substrate, and a monocrystalline silicon thin film 1 is arranged on the upper surface of the substrate insulating layer 11, etching the monocrystalline silicon thin film 1 on the SOI wafer through a photoetching or etching process, and removing the monocrystalline silicon thin films 1 on the front side, the rear side and the middle part of the area to form the monocrystalline silicon thin film 1 with the groove-shaped structural feature;
step two: as shown in fig. 8, 9, 10, 11, 12 and 13, a gate electrode insulating layer 7 is formed on the front and rear outer side surfaces of the groove-shaped structure formed by the single crystal silicon thin film 1, the inner side surfaces of the vertical portions at both sides of the groove, and the upper surface of the horizontal portion at the bottom of the groove by oxidation or deposition, etching process;
step three: as shown in fig. 14, fig. 15, fig. 16, fig. 17, fig. 18 and fig. 19, an insulating medium is deposited above the SOI wafer, and is planarized until the surface exposes the monocrystalline silicon thin film 1, and an insulating medium blocking layer 13 is preliminarily formed;
step four: as shown in fig. 20, fig. 21 and fig. 22, etching the partial insulating dielectric barrier layer 13 formed in step three and located on the front and back surfaces of the horizontal part at the bottom of the groove structure of the monocrystalline silicon thin film 1 until the gate electrode insulating layer 7 is exposed, and further forming the insulating dielectric barrier layer 13;
step five: as shown in fig. 23, 24 and 25, a deposition process is performed to deposit metal or polysilicon on the SOI wafer, the surface is planarized until the single crystal silicon thin film 1 is exposed, and the barrier adjusting gate 2 is preliminarily formed;
step six: as shown in fig. 26, fig. 27, fig. 28 and fig. 29, the insulating dielectric barrier layer 13 above the horizontal portion of the bottom of the groove structure formed by etching the monocrystalline silicon thin film 1 by an etching process is firstly etched to expose the gate electrode insulating layer 7, metal or polysilicon is deposited above the SOI wafer by a deposition process, the surface is planarized to expose the monocrystalline silicon thin film 1, and further the barrier adjusting gate 2 is formed;
step seven: as shown in fig. 30, fig. 31, fig. 32, and fig. 33, the region above the barrier modulation gate 2 formed in the sixth step is etched by an etching process, and the barrier modulation gate 2 is further formed;
step eight: as shown in fig. 34, fig. 35, fig. 36 and fig. 37, a deposition process of depositing an insulating dielectric over the SOI wafer to planarize the surface until the single crystal silicon thin film 1 is exposed, and further forming an insulating dielectric barrier layer 13;
step nine: as shown in fig. 38, 39, 40 and 41, by a photolithography or etching process, a part of the insulating dielectric barrier layer 13 formed in step eight is partially etched, and then metal or polysilicon is deposited on the SOI wafer, so as to planarize the surface until the single crystal silicon thin film 1 is exposed, thereby forming an H-shaped gate electrode 8;
step ten: as shown in fig. 42, 43 and 44, by the ion implantation process, the middle outer portion of the upper surface of the vertical portions on both sides of the groove structure formed by the single crystal silicon thin film 1 is doped to form a heavily doped source drain interchangeable region a5 and a heavily doped source drain interchangeable region b 6;
step eleven: as shown in fig. 45, 46 and 47, an insulating medium is deposited on the SOI wafer through a deposition process to form the remaining part of the insulating medium barrier layer 13; after the surface is flattened, the insulating medium barrier layer 13 above the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 is removed through an etching process until the upper surfaces of the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 are exposed, then metal is injected into the through hole formed through etching through a deposition process until the through hole is completely filled, and finally the surface is flattened to form a source-drain interchangeable electrode a 9 and a source-drain interchangeable electrode b 10.
Claims (2)
1. A barrier-regulated H-shaped gate-controlled bidirectional tunneling transistor comprises an SOI crystalA round silicon substrate (12), characterized in that: a substrate insulating layer (11) of the SOI wafer is arranged above a silicon substrate (12) of the SOI wafer, partial regions of a monocrystalline silicon film (1), a potential barrier regulating gate (2), a gate electrode insulating layer (7) and an insulating medium barrier layer (13) are arranged above the substrate insulating layer (11) of the SOI wafer, and the monocrystalline silicon film (1) has the geometrical characteristic of a concave shape and has the impurity concentration lower than 1016cm-3The monocrystalline silicon semiconductor material, wherein gate electrode insulating layers (7) are attached to the inner side surface and the front and rear outer side surfaces of a groove-shaped structure formed by the monocrystalline silicon thin film (1); the heavily doped source/drain interchangeable region a (5) and the heavily doped source/drain interchangeable region b (6) are formed by doping the middle parts above the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon film (1), and the peak concentration of impurities is not lower than 1018cm-3(ii) a The front surface, the back surface and the inner side surface of the heavily doped source-drain interchangeable region a (5) are mutually contacted with the source-drain interchangeable intrinsic region a (3) and are surrounded by the three surfaces; the front surface, the back surface and the inner side surface of the heavily doped source-drain interchangeable region b (6) are mutually contacted with the source-drain interchangeable intrinsic region b (4) and are surrounded by the three surfaces of the heavily doped source-drain interchangeable region b; the source-drain interchangeable intrinsic region a (3) and the source-drain interchangeable intrinsic region b (4) are respectively positioned in the inner side regions which are not subjected to the intentional doping process and are at the upper ends of the vertical parts at the two sides of the groove-shaped structure of the monocrystalline silicon film (1), and the impurity concentration of the inner side regions is lower than 1016cm-3The single crystal silicon semiconductor material of (a); the monocrystalline silicon film (1), the source-drain interchangeable intrinsic region a (3), the source-drain interchangeable intrinsic region b (4), the heavily doped source-drain interchangeable region a (5) and the heavily doped source-drain interchangeable region b (6) jointly form a groove-shaped structure; the gate electrode insulating layers (7) are positioned on the upper surface and the front and back surfaces of the horizontal part at the bottom of the groove-shaped structure formed by the monocrystalline silicon film (1) and the inner side surfaces and the front and back surfaces of the vertical parts at two sides of the groove-shaped structure of the monocrystalline silicon film (1); the H-shaped gate electrode (8) is made of metal material or polycrystalline silicon material, three surfaces of the inner side surface and the front and back surfaces of the upper part of the vertical part at two sides of the groove-shaped structure formed by the monocrystalline silicon film (1) are wrapped, the SOI wafer is overlooked, and the H-shaped gate electrode (8) is in English along the source-drain directionWriting a letter H shape, wherein the H-shaped gate electrode (8) and the groove-shaped structure of the monocrystalline silicon thin film (1) are insulated from each other through a gate electrode insulating layer (7), the H-shaped gate electrode (8) only has a field effect control effect on the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon thin film (1), and has no obvious field effect control effect on the lower regions of the vertical parts at two sides and the bottom horizontal part region of the groove-shaped structure formed by the monocrystalline silicon thin film (1); the barrier control grid (2) is made of metal materials or polycrystalline silicon materials, is positioned on the upper surface and the front and back surfaces of the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon thin film (1), wraps three sides of the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon thin film (1), and is insulated and isolated from the monocrystalline silicon thin film (1) through a gate electrode insulating layer (7), the barrier control grid (2) only has a field effect control function on the bottom horizontal part of the groove-shaped structure formed by the monocrystalline silicon thin film (1), and has no obvious field effect control function on the upper parts of the vertical parts at two sides of the groove-shaped structure formed by the monocrystalline silicon thin film (1); the H-shaped gate electrode (8) is positioned in a partial region with an insulating medium barrier layer (13) between the lower surface of the part of the inner side of the groove-shaped structure formed by the monocrystalline silicon thin film (1) and the potential barrier regulation gate (2), and the H-shaped gate electrode (8) and the potential barrier regulation gate (2) are isolated from each other in an insulating way through the insulating medium barrier layer (13); the source-drain interchangeable electrode a (9) is made of metal materials and is positioned above the heavily doped source-drain interchangeable area a (5); the source-drain interchangeable electrode b (10) is also made of metal materials and is positioned above the heavily doped source-drain interchangeable region b (6), and the three electrodes, namely the source-drain interchangeable electrode a (9), the source-drain interchangeable electrode b (10) and the H-shaped gate electrode (8), are insulated from each other through an insulating medium barrier layer (13); the left side and the right side of the barrier control gate (2) are of a symmetrical structure, and the same output characteristic can be realized under the condition that the source-drain interchangeable electrode a (9) and the source-drain interchangeable electrode b (10) are symmetrically interchanged.
2. A preparation method of a potential barrier regulation type H-shaped grid-control bidirectional tunneling transistor is characterized by comprising the following steps:
the manufacturing steps are as follows:
the method comprises the following steps: providing an SOI wafer, wherein the silicon substrate (12) of the SOI wafer is arranged at the bottommost part, a substrate insulating layer (11) is arranged on the upper surface of the silicon substrate (12), a monocrystalline silicon thin film (1) is arranged on the upper surface of the substrate insulating layer (11), and the monocrystalline silicon thin film (1) on the upper part of the SOI wafer is etched through photoetching or etching technology to remove the monocrystalline silicon thin films (1) on the front side, the rear side and the middle part of the area so as to form the monocrystalline silicon thin film (1) with the groove-shaped structural feature;
step two: forming a gate electrode insulating layer (7) on the front and back outer side surfaces of a groove-shaped structure formed by the monocrystalline silicon film (1), the inner side surfaces of vertical parts at two sides of the groove and the upper surface of a horizontal part at the bottom of the groove through oxidation or deposition and etching processes;
step three: depositing an insulating medium above the SOI wafer, flattening until the surface exposes the monocrystalline silicon film (1), and preliminarily forming an insulating medium barrier layer (13);
step four: etching partial insulating medium barrier layers (13) formed in the third step and positioned on the front surface and the rear surface of the horizontal part at the bottom of the groove structure of the monocrystalline silicon film (1) until the gate electrode insulating layer (7) is exposed, and further forming the insulating medium barrier layers (13);
step five: depositing metal or polysilicon on the SOI wafer through a deposition process, flattening the surface until the monocrystalline silicon film (1) is exposed, and preliminarily forming a potential barrier regulating gate (2);
step six: etching off an insulating medium barrier layer (13) above a horizontal part at the bottom of a groove structure formed by a monocrystalline silicon film (1) by an etching process until a gate electrode insulating layer (7) is exposed, depositing metal or polycrystalline silicon above an SOI wafer by a deposition process, flattening the surface until the monocrystalline silicon film (1) is exposed, and further forming a potential barrier regulating gate (2);
step seven: etching the upper area of the barrier control gate (2) formed in the sixth step by an etching process to further form the barrier control gate (2);
step eight: depositing an insulating medium above the SOI wafer through a deposition process, flattening the surface until the monocrystalline silicon thin film (1) is exposed, and further forming an insulating medium barrier layer (13);
step nine: etching part of the insulating medium barrier layer (13) formed in the step eight by photoetching or etching process, depositing metal or polysilicon above the SOI wafer, and flattening the surface until the monocrystalline silicon thin film (1) is exposed to form an H-shaped gate electrode (8);
step ten: doping the middle outer parts of the upper surfaces of the vertical parts on the two sides of the groove structure formed by the monocrystalline silicon film (1) by an ion implantation process to form a heavily doped source-drain interchangeable region a (5) and a heavily doped source-drain interchangeable region b (6);
step eleven: depositing an insulating medium above the SOI wafer through a deposition process to form an insulating medium barrier layer (13) of the rest part; and after the surface is flattened, removing the insulating medium barrier layer (13) above the heavily doped source-drain interchangeable region a (5) and the heavily doped source-drain interchangeable region b (6) by an etching process until the upper surfaces of the heavily doped source-drain interchangeable region a (5) and the heavily doped source-drain interchangeable region b (6) are exposed, injecting metal into the etched through hole by a deposition process until the through hole is completely filled, and finally flattening the surface to form a source-drain interchangeable electrode a (9) and a source-drain interchangeable electrode b (10).
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Effective date of registration: 20201224 Address after: Susong Xinqu Photoelectric Technology Co., Ltd., Jiumiao village, Qianling Township, Susong County, Anqing City, Anhui Province Patentee after: Susong Xinqu Photoelectric Technology Co., Ltd Address before: 110870 No. 111 Shenyang West Road, Shenyang economic and Technological Development Zone, Liaoning Patentee before: SHENYANG University OF TECHNOLOGY |