CN107819029A - A kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor and its manufacture method - Google Patents
A kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor and its manufacture method Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
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- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 7
- 235000008429 bread Nutrition 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 239000010408 film Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000010276 construction Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 7
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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Abstract
The present invention relates to a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor and its manufacture method, device of the present invention has H-shaped gate electrode, potential barrier regulation grid and symmetrical architectural feature, with stronger grid control ability and by adjusting the interchangeable electrode voltage of source and drain the interchangeable area of metal source and drain can be controlled to be used as source region or drain region, change tunnelling current direction.The advantages of present invention has low speed paper tape reader static power disspation, reverse leakage current, stronger grid control ability, low subthreshold swing and can realize two-way switch function.In contrast to common MOSFETs types device, more excellent switching characteristic is realized using tunneling effect；In contrast to common tunneling field-effect transistor, the present invention has the interchangeable bi-directional symmetrical switching characteristic of source and drain not available for common tunneling field-effect transistor, therefore is adapted to popularization and application.
Description
Technical field
The present invention relates to super large-scale integration manufacturing field, and in particular to one kind is applied to low power consumption integrated circuit system
The potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor and its manufacture method with low current leakage made.
Background technology
The elementary cell MOSFETs of integrated circuit can become less and less according to the requirement of Moore's Law, size, therewith
What is come is not only that difficulty in manufacturing process is deepened, various ill effects also highlighting all the more.Nowadays IC design
Itself produces the limitation of the physical mechanism of electric current when used MOSFETs types device is due to its work, and its subthreshold swing is not
60mV/dec can be less than.And common tunneling field-effect transistor as switching-type device in use, using carrier in semiconductor
Conduction mechanism of the tunneling effect as electric current can occur between band, its subthreshold swing will be substantially better than MOSFETs type devices
The 60mv/dec limit.However, common tunneling field-effect transistor source region and drain region use the impurity of different conduction-types, it is this non-
Symmetrical structure feature causes it can not functionally substitute the MOSFETs type devices with symmetrical structure feature completely.With N-type tunnel
Exemplified by wearing field-effect transistor, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential, then tunnelling
Field-effect transistor will be in the conduction state all the time, and the size of conducting electric current is no longer able to be well controlled by gate electrode
And regulation, this causes the switching characteristic of whole tunneling field-effect transistor to fail.
The content of the invention
Goal of the invention：
In order to effectively combine Asia low with MOSFETs type devices source electrode, the interchangeable and common tunneling field-effect transistor of drain electrode is utilized
The advantages of threshold value amplitude of oscillation, solution MOSFETs type device subthreshold swings can not reduce can only with common tunneling field-effect transistor
As the deficiency of single-way switch, the present invention proposes a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor and its manufacture method.
The transistor has logic function and is currently based on the completely compatible advantageous feature of MOSFETs integrated circuits, source and drain two-end structure
Symmetry allow its by source electrode and drain electrode voltage exchange realize source and drain bi-directional symmetrical switch function, i.e., with source
The interchangeable two-way switch characteristic of drain electrode, additionally with forward and reverse electric current than high and low subthreshold swing, high forward conduction electricity
The working characteristics such as stream.
Technical scheme：
The present invention is achieved through the following technical solutions：
A kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, the silicon substrate comprising SOI wafer, on the silicon substrate of SOI wafer
Side is the insulated substrate layer of SOI wafer, and the top of the insulated substrate layer of SOI wafer is monocrystalline silicon thin film, potential barrier regulation and control grid, grid electricity
The subregion of pole insulating barrier and insulating medium barrier layer, monocrystalline silicon thin film have concave geometric properties, are that impurity is dense
Degree is less than 1016cm-3Single-crystal semiconductor material, groove type structure inner surface that monocrystalline silicon thin film is formed with it is front and rear outer
Has grid electrode insulating layer in side surface；The interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain are respectively by monocrystalline
The upper middle portion of the both sides vertical component for the groove type structure that silicon thin film is formed adulterates to be formed, and impurity peak concentration is not low
In 1018cm-3；The interchangeable area a of heavy doping source and drain front and rear surfaces and inner surface contact with each other with the interchangeable intrinsic region a of source and drain,
And by thirdly face surrounds；The interchangeable area b of heavy doping source and drain front and rear surfaces and inner surface and the interchangeable intrinsic region b of source and drain are mutual
Contact, and by thirdly face surrounds；The interchangeable intrinsic region a of the source and drain and interchangeable intrinsic region b of source and drain is recessed positioned at monocrystalline silicon thin film respectively
The inside region for not carried out intentional doping process of the both sides vertical component upper end of bathtub construction, is less than for impurity concentration
1016cm-3Single-crystal semiconductor material；It is the interchangeable intrinsic region a of monocrystalline silicon thin film, source and drain, the interchangeable intrinsic region b of source and drain, heavily doped
The miscellaneous interchangeable area a and interchangeable area b of heavy doping source and drain of source and drain has collectively constituted a groove type structure；Grid electrode insulating layer is located at
The upper surface for the groove type structural base horizontal component that monocrystalline silicon thin film is formed and front and rear surfaces and monocrystalline silicon thin film groove
The inner surface and front and rear surfaces of shape structure both sides vertical component；H-shaped gate electrode is made up of metal material or polycrystalline silicon material, right
The inner surface and front and rear surfaces of the upper section of the both sides vertical component for the groove type structure that monocrystalline silicon thin film is formed are formed
Three bread are wrapped up in, and overlook SOI wafer, H-shaped gate electrode is in English capitalization H shape, H-shaped gate electrode and monocrystalline silicon along source and drain direction
Insulated from each other by grid electrode insulating layer between thin-film groove shape structure, H-shaped gate electrode is only formed recessed to monocrystalline silicon thin film
The upper section of the both sides vertical component of bathtub construction has field-effect control action, the groove type formed to monocrystalline silicon thin film
The lower zone of the both sides vertical component of structure and bottom horizontal portion region do not have obvious field-effect control action；Potential barrier is adjusted
Control grid are made up of metal material or polycrystalline silicon material, the groove type structural base horizontal component formed positioned at monocrystalline silicon thin film
Upper surface and front and rear surfaces, the groove type structural base horizontal component formed to monocrystalline silicon thin film forms three bread and wrapped up in, and leads to
Cross grid electrode insulating layer and monocrystalline silicon thin film is insulated from each other isolates, the groove type that potential barrier regulation and control grid are only formed to monocrystalline silicon thin film
Structural base horizontal component has field-effect control action, the both sides vertical component of the groove type structure formed to monocrystalline silicon thin film
Upper section there is no obvious field-effect control action；H-shaped gate electrode is located at the groove type structure that monocrystalline silicon thin film is formed
There is the subregion of insulating medium barrier layer, H-shaped gate electrode between the lower surface of part on the inside of groove and potential barrier regulation and control grid
Isolate between regulating and controlling grid with potential barrier by the way that insulating medium barrier layer is insulated from each other；The interchangeable electrode a of source and drain is made up of metal material,
Positioned at the interchangeable area a of heavy doping source and drain top；The interchangeable electrode b of source and drain is also made up of metal material, positioned at heavy doping source and drain
Pass through between interchangeable area b top, the interchangeable electrode a of source and drain, the interchangeable electrode b of source and drain and H-shaped gate electrode these three electrodes
Insulating medium barrier layer is insulated from each other；The left and right sides of potential barrier regulation and control grid is in symmetrical structure, can be in the interchangeable electrode a of source and drain and source
Leak in the case that interchangeable electrode b is symmetrically exchanged and realize same output characteristics.
A kind of specific manufacturing step of potential barrier controlling type H-shaped grid-control bidirectional tunneling crystal tube preparation method is as follows：
Step 1：One SOI wafer is provided, bottom is the silicon substrate of SOI wafer, is insulated substrate layer above silicon substrate,
The upper surface of insulated substrate layer is monocrystalline silicon thin film, and by photoetching or etching technics, the monocrystalline silicon thin film above SOI wafer enters
Row etching, removes front and rear sides and the subregional monocrystalline silicon thin film of pars intermedia, forms the monocrystalline with groove type architectural feature
Silicon thin film；
Step 2：By aoxidizing or depositing, etching technics, the outside table before and after the groove type structure that monocrystalline silicon thin film is formed
The overhead surface of the inner surface and bottom portion of groove horizontal component of face and groove both sides vertical component forms grid electrode insulating layer；
Step 3：Dielectric is deposited above SOI wafer, surface is planarized to and exposes monocrystalline silicon thin film, preliminarily forms insulation
Dielectric barrier；
Step 4：By etching technics, to being located at monocrystalline silicon thin film groove structure bottom horizontal portion formed in step 3
The SI semi-insulation dielectric barriers of front and rear surfaces perform etching to exposing grid electrode insulating layer, further form dielectric resistance
Barrier；
Step 5：By depositing technics, metal or polysilicon are deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon
Film, preliminarily form potential barrier regulation and control grid；
Step 6：First pass through the top that etching technics etches away groove structure bottom horizontal portion that monocrystalline silicon thin film is formed
Insulating medium barrier layer is depositing metal or polysilicon by depositing technics to grid electrode insulating layer is exposed above SOI wafer,
Planarization surface further forms potential barrier regulation and control grid to monocrystalline silicon thin film is exposed；
Step 7：The upper area for the potential barrier regulation and control grid that step 6 is formed is etched away by etching technics, further forms gesture
Build regulation and control grid；
Step 8：Depositing technics, deposits dielectric above SOI wafer, and planarization surface enters one to monocrystalline silicon thin film is exposed
Step forms insulating medium barrier layer；
Step 9：By photoetching or etching technics, part is carried out to the SI semi-insulation dielectric barrier formed in step 8
Etching, then metal or polysilicon are deposited above SOI wafer, planarization surface forms H-shaped grid electricity to monocrystalline silicon thin film is exposed
Pole；
Step 10：By ion implantation technology, the both sides vertical component upper surface for the groove structure that monocrystalline silicon thin film is formed
Middle Outboard Sections are doped, and form the interchangeable area a and interchangeable area b of heavy doping source and drain of heavy doping source and drain；
Step 11：By depositing technics, dielectric is deposited above SOI wafer, forms the dielectric resistance of remainder
Barrier；Removed after planarizing surface by etching technics above the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain
Insulating medium barrier layer to exposing the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain upper surface, then pass through
Injection metal to through hole is completely filled in the through hole that depositing technics is formed to etching, finally handles surface planarisation, is formed
The interchangeable electrode a of the source and drain and interchangeable electrode b of source and drain.
Advantage and effect：
The invention has the advantages that and beneficial effect：
1. the symmetrical interchangeable two-way switch characteristic of source and drain；
Device of the present invention is potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, and the left and right ends of monocrystalline silicon thin film are distinguished
With tunneling structure independent of each other, because device has bilateral symmetry, under the control action of H-shaped gate electrode, monocrystalline
Silicon thin film left and right ends are in the near surface contacted with grid electrode insulating layer while tunnelling occurs, and regulate and control grid to monocrystalline with reference to potential barrier
The regulating and controlling effect of silicon thin film center section potential, device is set to form forward conduction and reversely stop, it is interchangeable by adjusting source and drain
The interchangeable area a of electrode a and the interchangeable electrode b of source and drain voltage control heavy doping source and drain and the interchangeable area b conducts of heavy doping source and drain
Source region or drain region, therefore tunnelling current direction can be changed, realize source and drain of the invention symmetrically interchangeable two-way switch characteristic.
2. low subthreshold swing；
Because the present invention is the conduction mechanism by the use of band-to-band-tunneling effect as field-effect transistor, in the control of H-shaped gate electrode grid
Making under using so that energy band is easier to bend under identical gate voltage, adjusts the size of tunnelling current, compared to
MOSFETs types device can obtain lower subthreshold swing.
3. low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio；
So that conductivity type is N-type as an example, the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain now mix for p-type
It is miscellaneous, when electrical potential difference be present between the interchangeable area a of heavy doping source and drain, the interchangeable area b of heavy doping source and drain, and at H-shaped gate electrode
In subthreshold value or reverse-biased, because potential barrier regulation and control grid always work at positively biased state, the source and drain positioned at monocrystalline silicon thin film both sides
Interchangeable intrinsic region a and the interchangeable intrinsic region b of source and drain potential are regulated and controled gate control less than monocrystalline silicon thin film center section by potential barrier
Partial potential, by the field-effect of H-shaped gate electrode control in the interchangeable intrinsic region a of source and drain and the interchangeable intrinsic region b of source and drain
The hole in the interchangeable area a in hole and heavy doping source and drain and the interchangeable area b of heavy doping source and drain accumulated all can not be by by gesture
That builds regulation and control gate control forms potential barrier in monocrystalline silicon thin film center section, with common MOSFETs or tunnel field-effect transistor
Structure is compared, and both in the absence of the relatively stroke field intensity area domain between drain electrode and gate electrode, that is, can not form largely by tunnel-effect institute shape
Into electron hole pair, and due to potential barrier regulation and control grid auxiliary control action, in the gesture that monocrystalline silicon thin film center section is formed
Base can be effectively blocked between the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain, in the interchangeable intrinsic region of source and drain
The formation of hole current between a and the interchangeable intrinsic region b of source and drain.Therefore the present invention has low speed paper tape reader static power disspation, low reverse leakage
The advantages of electric current and high forward and reverse electric current ratio.
Brief description of the drawings
Fig. 1 is a kind of top view of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor of the present invention；
Fig. 2 is a kind of profile along dotted line A of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor of the present invention；
Fig. 3 is a kind of profile along dotted line B of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor of the present invention；
Fig. 4 is the top view of step 1；
Fig. 5 is the profile along dotted line A of step 1；
Fig. 6 is the profile along dotted line B of step 1；
Fig. 7 is the profile along dotted line C of step 1；
Fig. 8 is the top view of step 2；
Fig. 9 is the profile along dotted line A of step 2；
Figure 10 is the profile along dotted line B of step 2；
Figure 11 is the profile along dotted line C of step 2；
Figure 12 is the profile along dotted line D of step 2；
Figure 13 is the profile along dotted line E of step 2；
Figure 14 is the top view of step 3；
Figure 15 is the profile along dotted line A of step 3；
Figure 16 is the profile along dotted line B of step 3；
Figure 17 is the profile along dotted line C of step 3；
Figure 18 is the profile along dotted line D of step 3；
Figure 19 is the profile along dotted line E of step 3；
Figure 20 is the top view of step 4；
Figure 21 is the profile along dotted line A of step 4；
Figure 22 is the profile along dotted line B of step 4；
Figure 23 is the top view of step 5；
Figure 24 is the profile along dotted line A of step 5；
Figure 25 is the profile along dotted line B of step 5；
Figure 26 is the top view of step 6；
Figure 27 is the profile along dotted line A of step 6；
Figure 28 is the profile along dotted line B of step 6；
Figure 29 is the profile along dotted line C of step 6；
Figure 30 is the top view of step 7；
Figure 31 is the profile along dotted line A of step 7；
Figure 32 is the profile along dotted line B of step 7；
Figure 33 is the profile along dotted line C of step 7；
Figure 34 is the top view of step 8；
Figure 35 is the profile along dotted line A of step 8；
Figure 36 is the profile along dotted line B of step 8；
Figure 37 is the profile along dotted line C of step 8；
Figure 38 is the top view of step 9；
Figure 39 is the profile along dotted line A of step 9；
Figure 40 is the profile along dotted line B of step 9；
Figure 41 is the profile along dotted line C of step 9；
Figure 42 is the top view of step 10；
Figure 43 is the profile along dotted line A of step 10；
Figure 44 is the profile along dotted line B of step 10；
Figure 45 is the top view of step 11；
Figure 46 is the profile along dotted line A of step 11；
Figure 47 is the profile along dotted line B of step 11.
Description of reference numerals：
1st, monocrystalline silicon thin film；2nd, potential barrier regulation and control grid；3rd, the interchangeable intrinsic region a of source and drain；4th, the interchangeable intrinsic region b of source and drain；5th, it is heavily doped
The miscellaneous interchangeable area a of source and drain；6th, the interchangeable area b of heavy doping source and drain；7th, grid electrode insulating layer；8th, H-shaped gate electrode；9th, source and drain is interchangeable
Electrode a；10th, the interchangeable electrode b of source and drain；11st, insulated substrate layer；12nd, silicon substrate；13rd, insulating medium barrier layer.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
As shown in Figure 1, Figure 2 and Figure 3, a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, the silicon lining comprising SOI wafer
Bottom 12, the top of silicon substrate 12 of SOI wafer are the insulated substrate layer 11 of SOI wafer, the top of the insulated substrate layer 11 of SOI wafer
Regulate and control the subregion of grid 2, grid electrode insulating layer 7 and insulating medium barrier layer 13, monocrystalline silicon for monocrystalline silicon thin film 1, potential barrier
Film 1 has concave geometric properties, is less than 10 for impurity concentration16cm-3Single-crystal semiconductor material, monocrystalline silicon thin film 1
The groove type structure inner surface formed has grid electrode insulating layer 7 with front and rear outer surface；The interchangeable area a of heavy doping source and drain
The 5 and interchangeable area b 6 of heavy doping source and drain is respectively by the both sides vertical component of the groove type structure formed to monocrystalline silicon thin film 1
Upper middle portion adulterate to be formed, impurity peak concentration be not less than 1018cm-3；The interchangeable area a's 5 of heavy doping source and drain is front and rear
Surface and inner surface contact with each other with the interchangeable intrinsic region a 3 of source and drain, and by thirdly face surrounds；The interchangeable area of heavy doping source and drain
B 6 front and rear surfaces and inner surface contact with each other with the interchangeable intrinsic region b 4 of source and drain, and by thirdly face surrounds；Source and drain can be mutual
Intrinsic region a 3 and the interchangeable intrinsic region b 4 of source and drain is changed respectively to be located on the both sides vertical component of the groove type structure of monocrystalline silicon thin film 1
The inside region for not carried out intentional doping process at end, is less than 10 for impurity concentration16cm-3Single-crystal semiconductor material；It is single
The interchangeable intrinsic region a 3 of polycrystal silicon film 1, source and drain, the interchangeable intrinsic region b 4 of source and drain, the interchangeable area a 5 of heavy doping source and drain and heavily doped
The miscellaneous interchangeable area b 6 of source and drain has collectively constituted a groove type structure；Grid electrode insulating layer 7 is located at monocrystalline silicon thin film 1 and formed
Groove type structural base horizontal component upper surface and front and rear surfaces and the groove type structure both sides vertical component effect of monocrystalline silicon thin film 1
The inner surface and front and rear surfaces divided；H-shaped gate electrode 8 is made up of metal material or polycrystalline silicon material, to 1 shape of monocrystalline silicon thin film
Into groove type structure both sides vertical component upper section inner surface and front and rear surfaces formed three bread wrap up in, overlook
SOI wafer, H-shaped gate electrode 8 are in English capitalization H shape, H-shaped gate electrode 8 and the groove type of monocrystalline silicon thin film 1 along source and drain direction
Groove type structure insulated from each other by grid electrode insulating layer 7 between structure, that H-shaped gate electrode 8 is only formed to monocrystalline silicon thin film 1
The upper section of both sides vertical component there is field-effect control action, the groove type structure formed to monocrystalline silicon thin film 1
The lower zone of both sides vertical component and bottom horizontal portion region do not have obvious field-effect control action；Potential barrier regulates and controls grid 2
Be made up of metal material or polycrystalline silicon material, the groove type structural base horizontal component formed positioned at monocrystalline silicon thin film 1 it is upper
Surface and front and rear surfaces, the groove type structural base horizontal component formed to monocrystalline silicon thin film 1 forms three bread and wrapped up in, and passes through
Grid electrode insulating layer 7 and the groove that monocrystalline silicon thin film 1 is insulated from each other isolates, and potential barrier regulation and control grid 2 are only formed to monocrystalline silicon thin film 1
Shape structural base horizontal component has field-effect control action, and the both sides of the groove type structure formed to monocrystalline silicon thin film 1 are vertical
Partial upper section does not have obvious field-effect control action；H-shaped gate electrode 8 is located at the groove type that monocrystalline silicon thin film 1 is formed
There is the subregion of insulating medium barrier layer 13, H between the lower surface of part on the inside of the groove of structure and potential barrier regulation and control grid 2
Shape gate electrode 8 is isolated between regulating and controlling grid 2 with potential barrier by the way that insulating medium barrier layer 13 is insulated from each other；The interchangeable electrode a 9 of source and drain
It is made up of metal material, positioned at the interchangeable area a 5 of heavy doping source and drain top；The interchangeable electrode b 10 of source and drain is also by metal material
Form, positioned at the interchangeable area b 6 of heavy doping source and drain top, the interchangeable electrode a 9 of source and drain, the interchangeable electrode b 10 and H of source and drain
It is insulated from each other by insulating medium barrier layer 13 between these three electrodes of shape gate electrode 8；The left and right sides of potential barrier regulation and control grid 2 is in pair
Claim structure, can be realized in the case where the interchangeable electrode a 9 of the source and drain and interchangeable electrode b 10 of source and drain is symmetrically exchanged same defeated
Go out characteristic.
The present invention provides a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, has symmetrical architectural feature,
The interchangeable area a 5 of heavy doping source and drain is controlled by the voltage for adjusting the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain
Area b 6 interchangeable with heavy doping source and drain is used as source region or drain region, changes tunnelling current direction, device is realized that bidirectional tunneling turns on
The symmetrical interchangeable characteristic of source and drain.It is p type impurity with the interchangeable area a 5 of heavy doping source and drain and the interchangeable area b 6 of heavy doping source and drain
Exemplified by, when electrical potential difference be present between the interchangeable area a 5 of heavy doping source and drain, the interchangeable area b 6 of heavy doping source and drain, and work as H-shaped grid
Electrode 8 is in negative pressure reverse-biased, and by H-shaped gate field-effect function influence, the interchangeable meetings of area a 5 of heavy doping source and drain can be mutual to source and drain
Hole can be provided to the interchangeable intrinsic region b 4 of source and drain by changing intrinsic region a 3 and providing the interchangeable area b 6 of hole, heavy doping source and drain, therefore
Hole accumulation can be produced in the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain so that source and drain is interchangeable intrinsic
Area a 3 and the interchangeable intrinsic region b 4 of source and drain now show p-type state, and the hole accumulated causes the interchangeable intrinsic region a of source and drain
The 3 and interchangeable intrinsic region b 4 of source and drain resistance decreases in the presence of H-shaped gate electrode 8, i.e. source region, drain region are in low resistive state,
It is but interchangeable intrinsic to the interchangeable intrinsic region a 3 of source and drain and source and drain of both sides because potential barrier regulation and control grid 2 apply forward voltage all the time
Hole in area b 4 forms potential barrier, and in the interchangeable area a 5 of heavy doping source and drain, the interchangeable area b 6 of heavy doping source and drain to both sides
Hole also form potential barrier, and is applied forward voltage field-effect by potential barrier regulation and control grid 2 and is influenceed, be controlled by potential barrier and regulate and control grid 2
The center section of monocrystalline silicon thin film 1 N-type semiconductor state can be presented so that show the interchangeable intrinsic region a of source and drain of p-type feature
3 form reverse-biased PN junction structure with the center section now for the monocrystalline silicon thin film 1 of N-type under drain-source voltage effect, therefore work as H
Shape gate electrode 8 is in negative pressure reverse-biased, because in transistor internal, there is above-mentioned reverse-biased PN junction structure, transistor are overall
High resistant blocking state is presented；The voltage being applied in H-shaped gate electrode 8 is gradually risen up near flat-band voltage from negative voltage, weight
The interchangeable area a 5 of doped source and drain will not provide a large amount of holes, the interchangeable area b of heavy doping source and drain to the interchangeable intrinsic region a 3 of source and drain
6 will not provide a large amount of holes to the interchangeable intrinsic region b 4 of source and drain, simultaneously because the now interchangeable intrinsic region a 3 of source and drain and source and drain
Field strength is relatively low in interchangeable intrinsic region b 4, and band curvature degree is smaller, therefore also will not be in the interchangeable Hes of intrinsic region a 3 of source and drain
Produce a large amount of tunelling electrons holes pair between the interchangeable intrinsic region b 4 of source and drain conduction band and valence band, therefore in interchangeable of source and drain
Both a large amount of hole accumulations had been can not form in the sign area a 3 and interchangeable intrinsic region b 4 of source and drain, also can not form a large amount of electronics accumulations, crystal
The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain of pipe are in high-impedance state, i.e. source region and drain region is in height
Resistance state, therefore whole transistor does not have obvious electric current and flowed through, device now has outstanding turn-off characteristic and subthreshold value special
Property；The voltage being applied in H-shaped gate electrode 8 further rises to forward bias condition by flat-band voltage, and now source and drain can be mutual
Change in the intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain by the field-effect function influence of H-shaped gate electrode 8, it may appear that larger electric-field strength
Degree and stronger band curvature, therefore obvious tunnel-effect can occur so that the interchangeable intrinsic region a 3 of source and drain and source and drain are interchangeable
A large amount of electron hole pairs are formed in intrinsic region b 4, wherein hole caused by the interchangeable intrinsic region of source and drain as source region one end
It can be discharged via the interchangeable area of heavy doping source and drain at the end, caused electrons are via the monocrystalline controlled by potential barrier regulation and control grid 2
The N-type region domain that the center section of silicon thin film 1 is formed, the interchangeable intrinsic region of source and drain as drain region one end is flowed to, and as leakage
The valence band hole as caused by tunnel-effect occurs compound in the interchangeable intrinsic region of source and drain of area one end.And as drain region one end
Conduction band electron can be interchangeable via the heavy doping source and drain as drain region as caused by tunnel-effect in the interchangeable intrinsic region of source and drain
Area, it is compound with the generation of its valence band hole, continuous conducting electric current is formed by above-mentioned physical process.Due to produced by tunnel-effect
Concentration of electron-hole pairs can be gradually risen as H-shaped gate electrode 8 is applied in the rising of voltage, produced by tunnel-effect
Concentration of electron-hole pairs increase to a certain extent when, transistor transits to forward conduction state by sub-threshold status.
Because device has symmetrical architectural feature on source and drain direction, therefore it is different from common tunneling field-effect
Transistor, a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor proposed by the invention, its source region and drain region can be realized
Exchange function.
To reach device function of the present invention, the present invention proposes that a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling is brilliant
Body pipe, its core texture are characterized as：
Device of the present invention is a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, and both sides are in symmetrical structure.By potential barrier
Regulate and control the center section that grid 2 control monocrystalline silicon thin film 1, by being disposed at specific fixed voltage value, counterweight doped source and drain
The majority carrier in interchangeable area forms potential barrier, suppresses the size of the leakage current under reverse-biased and sub-threshold status.Potential barrier regulates and controls
The center section for the monocrystalline silicon thin film 1 that grid 2 are controlled and the interchangeable area a 5 of heavy doping source and drain, the interchangeable area b 6 of heavy doping source and drain
With opposite polarity carrier type.Due to symmetrical structure possessed by device of the present invention, by controlling source and drain interchangeable
Electrode a 9 and the interchangeable electrode b 10 of source and drain control the interchangeable area a 5 and interchangeable area b 6 of heavy doping source and drain of heavy doping source and drain to make
For source region or drain region, the interchangeable two-way switch characteristic of device source and drain is realized.
Device of the present invention is a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, has the knot of H-shaped gate electrode
Structure, contacted with each other with the outer surface of grid electrode insulating layer 7, and three faces are formed to grid electrode insulating layer 7 and surrounded, overlooking viewing is in
Existing English capitalization H-shaped architectural feature, the top of the both sides vertical component of the groove type structure formed to monocrystalline silicon thin film 1
Part, i.e., intrinsic region a 3 and the interchangeable intrinsic region b 4 of source and drain interchangeable to source and drain have obvious field-effect control action, work as H
When shape gate electrode 8 is in positively biased state, in contrast to planar structure, the electric-field intensity meeting near the corner region of H-shaped gate electrode 8
Strengthened, cause to produce the probability of carrier in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain same
Deng increasing under gate voltage so that subthreshold swing has declined, forward conduction electric current has increased；
A kind of specific manufacturing step of potential barrier controlling type H-shaped grid-control bidirectional tunneling crystal tube preparation method proposed by the invention is such as
Under：
Step 1：As shown in Figure 4, Figure 5, Figure 6 and Figure 7, there is provided a SOI wafer, bottom are the silicon substrate 12 of SOI wafer,
It is insulated substrate layer 11 above silicon substrate, the upper surface of insulated substrate layer 11 is monocrystalline silicon thin film 1, passes through photoetching or etching work
Skill, the monocrystalline silicon thin film 1 above SOI wafer perform etching, and remove front and rear sides and the subregional monocrystalline silicon of pars intermedia is thin
Film 1, form the monocrystalline silicon thin film 1 with groove type architectural feature；
Step 2：As shown in Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12 and Figure 13, by aoxidizing or depositing, etching technics, in monocrystalline
The inner surface and bottom portion of groove of front and rear outer surface and groove the both sides vertical component for the groove type structure that silicon thin film 1 is formed
The overhead surface of horizontal component forms grid electrode insulating layer 7；
Step 3：As shown in Figure 14, Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19, dielectric is deposited above SOI wafer, is put down
Monocrystalline silicon thin film 1 is exposed on smoothization to surface, preliminarily forms insulating medium barrier layer 13；
Step 4：As shown in Figure 20, Figure 21 and Figure 22, by etching technics, to thin positioned at monocrystalline silicon formed in step 3
The SI semi-insulation dielectric barrier 13 of the front and rear surfaces of the groove structure bottom horizontal portion of film 1 performs etching exhausted to gate electrode is exposed
Edge layer 7, further form insulating medium barrier layer 13；
Step 5：As shown in Figure 23, Figure 24 and Figure 25, by depositing technics, metal or polysilicon are deposited above SOI wafer,
Surface is planarized to monocrystalline silicon thin film 1 is exposed, preliminarily forms potential barrier regulation and control grid 2；
Step 6：As shown in Figure 26, Figure 27, Figure 28 and Figure 29, first pass through etching technics and etch away what monocrystalline silicon thin film 1 was formed
The insulating medium barrier layer 13 of the top of groove structure bottom horizontal portion is to grid electrode insulating layer 7 is exposed, by depositing work
Skill deposits metal or polysilicon above SOI wafer, and planarization surface further forms potential barrier and adjusted to monocrystalline silicon thin film 1 is exposed
Control grid 2；
Step 7：As shown in Figure 30, Figure 31, Figure 32 and Figure 33, the potential barrier that step 6 formed is etched away by etching technics and adjusted
The upper area of grid 2 is controlled, further forms potential barrier regulation and control grid 2；
Step 8：As shown in Figure 34, Figure 35, Figure 36 and Figure 37, depositing technics, dielectric is deposited above SOI wafer, it is flat
Change surface to monocrystalline silicon thin film 1 is exposed, further form insulating medium barrier layer 13；
Step 9：As shown in Figure 38, Figure 39, Figure 40 and Figure 41, by photoetching or etching technics, to formed in step 8
SI semi-insulation dielectric barrier 13 carries out partial etching, then metal or polysilicon are deposited above SOI wafer, and planarization surface is extremely
Expose monocrystalline silicon thin film 1, form H-shaped gate electrode 8；
Step 10：As shown in Figure 42, Figure 43 and Figure 44, by ion implantation technology, groove structure that monocrystalline silicon thin film 1 is formed
The middle Outboard Sections of both sides vertical component upper surface be doped, form the interchangeable area a 5 of heavy doping source and drain and heavy doping
The interchangeable area b 6 of source and drain；
Step 11：As shown in Figure 45, Figure 46 and Figure 47, by depositing technics, dielectric, shape are deposited above SOI wafer
Into the insulating medium barrier layer 13 of remainder；The interchangeable area a of heavy doping source and drain is removed by etching technics behind planarization surface
The insulating medium barrier layer 13 of the 5 and interchangeable area b of heavy doping source and drain 6 tops is to exposing the interchangeable area a 5 of heavy doping source and drain and again
Metal is injected in the interchangeable area b 6 of doped source and drain upper surface, then the through hole formed by depositing technics to etching to through hole quilt
It is filled up completely with, finally handles surface planarisation, forms the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain.
Claims (2)
1. a kind of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, the silicon substrate comprising SOI wafer（12）, it is characterised in that：
The silicon substrate of SOI wafer（12）Top is the insulated substrate layer of SOI wafer（11）, the insulated substrate layer of SOI wafer（11）It is upper
Side is monocrystalline silicon thin film（1）, potential barrier regulation and control grid（2）, grid electrode insulating layer（7）And insulating medium barrier layer（13）Part area
Domain, monocrystalline silicon thin film（1）With concave geometric properties, it is less than 10 for impurity concentration16cm-3Single-crystal semiconductor material,
Monocrystalline silicon thin film（1）The groove type structure inner surface formed has grid electrode insulating layer with front and rear outer surface（7）；It is heavily doped
The miscellaneous interchangeable area a of source and drain（5）With the interchangeable area b of heavy doping source and drain（6）Respectively by monocrystalline silicon thin film（1）The groove formed
The upper middle portion of the both sides vertical component of shape structure adulterates to be formed, and impurity peak concentration is not less than 1018cm-3；Heavy-doped source
Leak interchangeable area a（5）Front and rear surfaces and inner surface and the interchangeable intrinsic region a of source and drain（3）Contact with each other, and by thirdly face is enclosed
Around；The interchangeable area b of heavy doping source and drain（6）Front and rear surfaces and inner surface and the interchangeable intrinsic region b of source and drain（4）Contact with each other,
And by thirdly face surrounds；The interchangeable intrinsic region a of source and drain（3）With the interchangeable intrinsic region b of source and drain（4）It is located at monocrystalline silicon thin film respectively
（1）The inside region for not carried out intentional doping process of the both sides vertical component upper end of groove type structure, is that impurity concentration is low
In 1016cm-3Single-crystal semiconductor material；Monocrystalline silicon thin film（1）, the interchangeable intrinsic region a of source and drain（3）, source and drain it is interchangeable intrinsic
Area b（4）, the interchangeable area a of heavy doping source and drain（5）With the interchangeable area b of heavy doping source and drain（6）A groove type knot is collectively constituted
Structure；Grid electrode insulating layer（7）Positioned at monocrystalline silicon thin film（1）The upper surface of the groove type structural base horizontal component formed is with before
Surface and monocrystalline silicon thin film afterwards（1）The inner surface and front and rear surfaces of groove type structure both sides vertical component；H-shaped gate electrode
（8）It is made up of metal material or polycrystalline silicon material, to monocrystalline silicon thin film（1）The both sides vertical component of the groove type structure formed
Upper section inner surface and front and rear surfaces formed three bread wrap up in, overlook SOI wafer, H-shaped gate electrode（8）Along source and drain direction
In English capitalization H shape, H-shaped gate electrode（8）With monocrystalline silicon thin film（1）Pass through grid electrode insulating layer between groove type structure
（7）It is insulated from each other, H-shaped gate electrode（8）Only to monocrystalline silicon thin film（1）The both sides vertical component of the groove type structure formed it is upper
Side part has field-effect control action, to monocrystalline silicon thin film（1）Under the both sides vertical component of the groove type structure formed
Square region and bottom horizontal portion region do not have obvious field-effect control action；Potential barrier regulates and controls grid（2）By metal material or more
Crystal silicon material is formed, positioned at monocrystalline silicon thin film（1）The upper surface of the groove type structural base horizontal component formed and front and rear table
Face, to monocrystalline silicon thin film（1）The groove type structural base horizontal component formed forms three bread and wrapped up in, and passes through grid electrode insulating
Layer（7）With monocrystalline silicon thin film（1）Isolation insulated from each other, potential barrier regulation and control grid（2）Only to monocrystalline silicon thin film（1）The groove type formed
Structural base horizontal component has field-effect control action, to monocrystalline silicon thin film（1）The both sides of the groove type structure formed are vertical
Partial upper section does not have obvious field-effect control action；H-shaped gate electrode（8）Positioned at monocrystalline silicon thin film（1）What is formed is recessed
The lower surface of part on the inside of the groove of bathtub construction and potential barrier regulation and control grid（2）Between there is insulating medium barrier layer（13）Portion
Subregion, H-shaped gate electrode（8）Regulate and control grid with potential barrier（2）Between pass through insulating medium barrier layer（13）Isolation insulated from each other；Source and drain
Interchangeable electrode a（9）It is made up of metal material, positioned at the interchangeable area a of heavy doping source and drain（5）Top；The interchangeable electrode b of source and drain
（10）Also it is made up of metal material, positioned at the interchangeable area b of heavy doping source and drain（6）Top, the interchangeable electrode a of source and drain（9）, source and drain
Interchangeable electrode b（10）With H-shaped gate electrode（8）Pass through insulating medium barrier layer between these three electrodes（13）It is insulated from each other；Gesture
Build regulation and control grid（2）The left and right sides be in symmetrical structure, can be in the interchangeable electrode a of source and drain（9）With the interchangeable electrode b of source and drain（10）It is right
Claim to realize same output characteristics in the case of exchanging.
A kind of 2. preparation method of potential barrier controlling type H-shaped grid-control bidirectional tunneling transistor, it is characterised in that：
Its manufacturing step is as follows：
Step 1：A SOI wafer is provided, bottom is the silicon substrate of SOI wafer（12）, silicon substrate（12）Above be substrate
Insulating barrier（11）, insulated substrate layer（11）Upper surface be monocrystalline silicon thin film（1）, by photoetching or etching technics, to SOI wafer
The monocrystalline silicon thin film of top（1）Perform etching, remove front and rear sides and the subregional monocrystalline silicon thin film of pars intermedia（1）, formed
Monocrystalline silicon thin film with groove type architectural feature（1）；
Step 2：By aoxidizing or depositing, etching technics, in monocrystalline silicon thin film（1）The groove type structure formed it is front and rear outer
The overhead surface of the inner surface and bottom portion of groove horizontal component of side surface and groove both sides vertical component forms grid electrode insulating
Layer（7）；
Step 3：Dielectric is deposited above SOI wafer, surface is planarized to and exposes monocrystalline silicon thin film（1）, preliminarily form absolutely
Edge dielectric barrier（13）；
Step 4：By etching technics, to being located at monocrystalline silicon thin film formed in step 3（1）Groove structure bottom level portion
The SI semi-insulation dielectric barrier for the front and rear surfaces divided（13）Perform etching to exposing grid electrode insulating layer（7）, further formed
Insulating medium barrier layer（13）；
Step 5：By depositing technics, metal or polysilicon are deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon
Film（1）, preliminarily form potential barrier regulation and control（2）；
Step 6：First pass through etching technics and etch away monocrystalline silicon thin film（1）The groove structure bottom horizontal portion formed it is upper
The insulating medium barrier layer of side（13）To grid electrode insulating layer 7 is exposed, metal is being deposited above SOI wafer by depositing technics
Or polysilicon, planarization surface is to exposing monocrystalline silicon thin film（1）, further form potential barrier regulation and control grid（2）；
Step 7：The potential barrier that step 6 formed is etched away by etching technics and regulates and controls grid（2）Upper area, further formed
Potential barrier regulates and controls grid（2）；
Step 8：By depositing technics, dielectric is deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film
（1）, further form insulating medium barrier layer（13）；
Step 9：By photoetching or etching technics, to the SI semi-insulation dielectric barrier formed in step 8（13）Carry out
Partial etching, then metal or polysilicon are deposited above SOI wafer, planarization surface is to exposing monocrystalline silicon thin film（1）, form H
Shape gate electrode（8）；
Step 10：Pass through ion implantation technology, monocrystalline silicon thin film（1）The both sides vertical component upper surface of the groove structure formed
Middle Outboard Sections be doped, form heavy doping source and drain interchangeable area a（5）With the interchangeable area b of heavy doping source and drain（6）；
Step 11：By depositing technics, dielectric is deposited above SOI wafer, forms the dielectric resistance of remainder
Barrier（13）；The interchangeable area a of heavy doping source and drain is removed by etching technics behind planarization surface（5）It is interchangeable with heavy doping source and drain
Area b（6）The insulating medium barrier layer of top（13）To exposing the interchangeable area a of heavy doping source and drain（5）It is interchangeable with heavy doping source and drain
Area b（6）Upper surface, then by depositing technics to etching formed through hole in injection metal to through hole be completely filled, finally
Surface planarisation is handled, forms the interchangeable electrode a of source and drain（9）With the interchangeable electrode b of source and drain（10）.
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| US20040164342A1 (en) * | 2001-08-30 | 2004-08-26 | Micron Technology, Inc. | Integrated circuit memory device and method |
| CN1851903A (en) * | 2005-04-22 | 2006-10-25 | 韩国科学技术院 | Multi-bit non-volatile memory having dual gates, method of manufacturing the same, and multi-bit cell operating method |
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