CN104485353B - Insulated gate tunneling bipolar transistor with U-shaped tunneling insulating layer and manufacturing process - Google Patents
Insulated gate tunneling bipolar transistor with U-shaped tunneling insulating layer and manufacturing process Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention relates to an insulated gate tunneling bipolar transistor with a U-shaped tunneling insulating layer. A gate electrode tunneling current is generated by the U-shaped tunneling insulating layer, and the very sensitive mutual relation between impedance of the tunneling insulating layer and intensity of an internal electric field of the tunneling insulating layer is utilized to enable the U-shaped tunneling insulating layer to implement conversion between a high impedance state and a low impedance state in a very short electric potential change interval of a gate electrode, and thus, compared with the prior art, the insulated gate tunneling bipolar transistor can realize a better switching characteristic; by bipolar amplification, the positive conduction characteristic of a nanoscale insulated gate transistor is obviously improved. The invention also discloses a specific manufacturing method of the insulated gate tunneling bipolar transistor with the U-shaped tunneling insulating layer. Therefore, the working characteristic of a nanoscale integrated circuit unit is obviously improved, and the insulated gate tunneling bipolar transistor and the manufacturing method are suitable for being popularized and applied.
Description
Technical field：
The present invention relates to super large-scale integration manufacture field, is related to a kind of integrated suitable for high-performance superelevation integrated level
The structure and its manufacturing process of the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer of circuit manufacture.
Background technology：
Currently, integrated circuit unit mos field effect transistor (MOSFETs) device channel length
Constantly shorten and result in the deterioration of devices switch characteristic and the obvious increase of quiescent dissipation.Although by improving gate electrode structure
Mode has alleviated can the degeneration of this device performance, but when device size further reduces, the performance of device can be again
Deteriorate.
To solve the problems, such as the physical size limits of MOSFETs devices, it is proposed that tunneling field-effect transistor (TFETs), by
It is potential in it and possesses more preferable switching characteristic and lower power consumption, it is therefore possible to replaces MOSFETs devices and becoming next
For super large-scale integration logical block or memory element.However, in contrast to MOSFETs devices, its inferior position is subthreshold value
Slope is simply locally exceeding MOSFETs devices, and forward conduction electric current very little.
To improve the electrology characteristic of TFETs, current primary solutions are by introducing compound semiconductor, SiGe
Or the narrower material of energy gap such as germanium comes the tunnelling part of generating device, and sub-threshold slope is lifted with this and increases electric conduction
Stream.But such way not only increases production cost, also increases technology difficulty.Additionally, being insulated using high-k
Material can only improve control ability of the grid to electric field distribution in channel as the insulating medium layer between grid and substrate, and not
The tunnelling probability of silicon materials can be inherently improved, therefore for the improvement of the electrology characteristics such as sub-threshold slope conducting electric current has very much
Limit.
The content of the invention：
Goal of the invention
Spy is turned on to be obviously improved the switching characteristic of nanometer-grade IC basic unit device, the forward current of device
Property, the present invention provides a kind of insulation with U-shaped tunneling insulation layer suitable for high-performance superelevation integrated level IC manufacturing
The structure and its manufacturing process of grid tunnelling bipolar transistor.
Technical scheme
The present invention is achieved through the following technical solutions：
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, using the only body silicon wafer comprising monocrystalline substrate 1
Circle is used as generating device substrate, or adopts while the SOI wafer comprising monocrystalline substrate 1 and wafer insulating barrier 2 is used as maker
The substrate of part；Launch site 3, base 4 and collecting zone 5 are located at the monocrystalline substrate 1 of body Silicon Wafer or the wafer insulating barrier of SOI wafer
2 top；Emitter stage 9 is located at the top of launch site 3；Colelctor electrode 10 is located at the top of collecting zone 5；U-shaped conductive layer 6 is located at base
4 top；U-shaped tunneling insulation layer 7 is located at the inner side of U-shaped conductive layer 6；Gate electrode 8 is located at the inner side of U-shaped tunneling insulation layer 7；Resistance
Gear insulating barrier 11 is located between device cell and each electrode between, is made to playing isolation and each electrode between each device cell
With.
To reach device function of the present invention, the present invention proposes a kind of insulated gate tunnel with U-shaped tunneling insulation layer
Bipolar transistor is worn, its core texture is characterized as：
U-shaped tunneling insulation layer 7 is the insulating barrier for producing gate electrode tunnelling current, with English capitalization " u "-shaped
Architectural feature can be silicon dioxide etc. with the insulant compared with low-k, or with more high-k
Insulation material layer, such as：Hafnium oxide, silicon nitride, aluminium sesquioxide etc., but it is not limited only to this.
It is isolated from each other by barrier insulating layer 11 between U-shaped conductive layer 6 and launch site 3 and emitter stage 9；U-shaped conductive layer 6 with
It is isolated from each other by barrier insulating layer 11 between collecting zone 5 and colelctor electrode 10；Pass through between adjacent launch site 3 and collecting zone 5
Barrier insulating layer 11 is isolated from each other；It is isolated from each other by barrier insulating layer 11 between adjacent emitter stage 9 and colelctor electrode 10.
The medial wall of U-shaped conductive layer 6 forms three bread and encloses to the lateral wall of U-shaped tunneling insulation layer 7；The bottom of U-shaped conductive layer 6
Portion forms Ohmic contact with base 4, and U-shaped conductive layer 6 is metal material or has the heavily doped of identical dopant type with base 4
Miscellaneous polysilicon.
Gate electrode 8 is wrapped up in by the bread of inwall three of U-shaped tunneling insulation layer 7, is the electrode that control device is switched on and off.
The doping type of launch site 3 and collecting zone 5 is contrary with base 4.
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, by taking N-type as an example, launch site 3, base 4 and current collection
Area 5 is respectively N areas, P areas and N areas, and its specific operation principle is：When the positively biased of colelctor electrode 10, and gate electrode 8 is in electronegative potential
When, enough electric potential differences are not formed between gate electrode 8 and U-shaped conductive layer 6, now U-shaped tunneling insulation layer 7 is in high resistant shape
State, passes through without obvious tunnelling current, hence in so that cannot form sufficiently large base electric current between base 4 and launch site 3
The insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, i.e. device is driven to be off state；With gate electrode 8 it is electric
That what is pressed gradually rises, and the electric potential difference between gate electrode 8 and U-shaped conductive layer 6 gradually increases so that conductive positioned at gate electrode 8 and U-shaped
Electric field intensity between layer 6 in U-shaped tunneling insulation layer 7 also gradually increases therewith, the electric field intensity in U-shaped tunneling insulation layer 7
When below marginal value, U-shaped tunneling insulation layer 7 still keeps good high-impedance state, the electricity between gate electrode and emitter stage
Potential difference is almost dropped completely between the inner and outer wall both sides of U-shaped tunneling insulation layer 7, is also allowed between base and launch site
Electric potential difference is minimum, therefore base almost flows through without electric current, and therefore device also keeps good off state, and works as U-shaped tunnelling
When electric field intensity in insulating barrier 7 is located at more than marginal value, U-shaped tunneling insulation layer 7 can be produced significantly due to tunneling effect
Tunnelling current, and tunnelling current then can be with the increase of the potential of gate electrode 8 precipitous rising at a terrific speed, and this allows for U
Shape tunneling insulation layer 7 gate electrode it is extremely short potential change interval in low resistance state is rapidly converted into by high-impedance state, when U-shaped tunnelling it is exhausted
Edge layer 7 is in low resistance state, and the resistance that now U-shaped tunneling insulation layer 7 is formed between gate electrode 8 and U-shaped conductive layer 6 is remote little
The resistance formed between U-shaped conductive layer 6 and emitter stage 3, this allows for being defined between base 4 and launch site 3 sufficiently large
Positive bias-voltage, and in the presence of tunneling effect, a large amount of electricity are produced between the inner and outer wall of U-shaped tunneling insulation layer 7
Son is mobile, and as base 4 provides current source, hence in so that defining sufficiently large base electric current between base 4 and launch site 3
The insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, i.e. device is driven to be in opening；
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, using using tunneling insulation layer impedance and tunnelling
Extremely sensitive mutual relation between insulating barrier electric field intensity inside high, inside and outside the side and bottom to U-shaped tunneling insulation layer 7
Thickness and profile height between wall is suitably adjusted, so that it may so that U-shaped tunneling insulation layer 7 is in the extremely short electricity of gate electrode
The conversion between high-impedance state and low resistance state is realized in gesture constant interval, MOSFETs, the TFETs or common in contrast to ordinary construction
Bipolar transistor, it is possible to achieve more precipitous sub-threshold slope, therefore realize more preferable switching characteristic.
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, by insulated gate tunnel produced by U-shaped tunneling insulation layer
The base current that electric current is converted into bipolar transistor is worn, and the amplification characteristic using bipolar transistor is produced to tunneling insulation layer 7
Raw insulation gate tunneling current is amplified, therefore is ensureing that present invention contrast is double in contrast to MOSFETs, TFETs or common
While gated transistors have more excellent switching characteristic, the forward conduction electric current of device has been obviously improved.
Advantage and effect
The invention has the advantages that and beneficial effect：
1. more preferable switching characteristic
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, using using tunneling insulation layer impedance and tunnelling
Extremely sensitive mutual relation between insulating barrier electric field intensity inside high, inside and outside the side and bottom to U-shaped tunneling insulation layer 7
Thickness and profile height between wall is suitably adjusted, so that it may so that U-shaped tunneling insulation layer 7 is in the extremely short electricity of gate electrode
The conversion between high-impedance state and low resistance state is realized in gesture constant interval, in contrast to MOSFETs, TFETs or common bipolar transistor
Pipe, it is possible to achieve more precipitous sub-threshold slope, that is, significantly improve the switching characteristic of nanometer-grade IC unit component.
2. good forward conduction characteristic
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, by insulated gate tunnel produced by U-shaped tunneling insulation layer
The base current that electric current is converted into bipolar transistor is worn, and the amplification characteristic using bipolar transistor is produced to tunneling insulation layer 7
Raw insulation gate tunneling current is amplified, therefore is ensureing that present invention contrast is double in contrast to MOSFETs, TFETs or common
While gated transistors have more excellent switching characteristic, the forward conduction electric current of device has been obviously improved.
Description of the drawings
Fig. 1 is two that insulated gate tunnelling bipolar transistor of the present invention with U-shaped tunneling insulation layer is formed on soi substrates
Dimension structural representation；
Fig. 2 is step one schematic diagram,
Fig. 3 is step 2 schematic diagram,
Fig. 4 is step 3 schematic diagram,
Fig. 5 is step 4 schematic diagram,
Fig. 6 is step 5 schematic diagram,
Fig. 7 is step 6 schematic diagram,
Fig. 8 is step 7 schematic diagram,
Fig. 9 is step 8 schematic diagram,
Figure 10 is step 9 schematic diagram,
Figure 11 is step 10 schematic diagram.
Description of reference numerals：
1st, monocrystalline substrate；2nd, wafer insulating barrier；3rd, launch site；4th, base；5th, collecting zone；6th, U-shaped conductive layer；7th, U-shaped
Tunneling insulation layer；8th, gate electrode；9th, emitter stage；10th, colelctor electrode；11st, barrier insulating layer.
Specific embodiment
Below in conjunction with the accompanying drawings the present invention is described further：
If Fig. 1 is that insulated gate tunnelling bipolar transistor of the present invention with U-shaped tunneling insulation layer is formed on soi substrates
Two-dimensional structure schematic diagram；Specifically include monocrystalline substrate 1；Wafer insulating barrier 2；Launch site 3；Base 4；Collecting zone 5；U-shaped is conductive
Layer 6；U-shaped tunneling insulation layer 7；Gate electrode 8；Emitter stage 9；Colelctor electrode 10；Barrier insulating layer 11.
To reach device function of the present invention, this insulation with U-shaped tunneling insulation layer proposed by the invention
Grid tunnelling bipolar transistor, its core texture is characterized as：
1.U shapes tunneling insulation layer 7 is the insulating barrier for producing gate electrode tunnelling current, with English capitalization " U "
Shape architectural feature, can be silicon dioxide layer, or the insulation material layer with more high-k, such as：Hafnium oxide,
Silicon nitride, aluminium sesquioxide etc., but it is not limited only to this.
The medial wall of 2.U shapes conductive layer 6 forms three bread and encloses to the lateral wall of U-shaped tunneling insulation layer 7, the bottom of U-shaped conductive layer 6
Portion and base 4 form good ohmic and contacts, are good conductive materials, can be metal, or with base 4 with identical
The heavily doped region of dopant type.
3. gate electrode 8 is wrapped up in by the bread of inwall three of U-shaped tunneling insulation layer 7, is the electrode that control device is switched on and off.
4. the doping type of launch site 3 and collecting zone 5 is contrary with base 4.
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, using the only body silicon wafer comprising monocrystalline substrate 1
Circle is used as generating device substrate, or adopts while the SOI wafer comprising monocrystalline substrate 1 and wafer insulating barrier 2 is used as maker
The substrate of part；Launch site 3, base 4 and collecting zone 5 are located at the monocrystalline substrate 1 of body Silicon Wafer or the wafer insulating barrier of SOI wafer
2 top；Emitter stage 9 is located at the top of launch site 3；Colelctor electrode 10 is located at the top of collecting zone 5；U-shaped conductive layer 6 is located at base
4 top；U-shaped tunneling insulation layer 7 is located at the inner side of U-shaped conductive layer 6；Gate electrode 8 is located at the inner side of U-shaped tunneling insulation layer 7；Resistance
Gear insulating barrier 11 is located between device cell and each electrode between, is made to playing isolation and each electrode between each device cell
With.
To reach device function of the present invention, the present invention proposes a kind of insulated gate tunnel with U-shaped tunneling insulation layer
Bipolar transistor is worn, its core texture is characterized as：
U-shaped tunneling insulation layer 7 is the insulating barrier for producing gate electrode tunnelling current, with English capitalization " u "-shaped
Architectural feature can be silicon dioxide etc. with the insulant compared with low-k, or with more high-k
Insulation material layer, such as：Hafnium oxide, silicon nitride, aluminium sesquioxide etc., but it is not limited only to this.
The medial wall of U-shaped conductive layer 6 forms three bread and encloses to the lateral wall of U-shaped tunneling insulation layer 7, the bottom of U-shaped conductive layer 6
Good ohmic is formed with base 4 to contact, be good conductive material, be metal material, or there is identical impurity with base 4
The heavily doped polysilicon of type.
Gate electrode 8 is wrapped up in by the bread of inwall three of U-shaped tunneling insulation layer 7, is the electrode that control device is switched on and off.
The doping type of launch site 3 and collecting zone 5 is contrary with base 4.
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, by taking N-type as an example, launch site 3, base 4 and current collection
Area 5 is respectively N areas, P areas and N areas, and its specific operation principle is：When the positively biased of colelctor electrode 10, and gate electrode 8 is in electronegative potential
When, enough electric potential differences are not formed between gate electrode 8 and U-shaped conductive layer 6, now U-shaped tunneling insulation layer 7 is in high resistant shape
State, passes through without obvious tunnelling current, hence in so that cannot form sufficiently large base electric current between base 4 and launch site 3
The insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, i.e. device is driven to be off state；With gate electrode 8 it is electric
That what is pressed gradually rises, and the electric potential difference between gate electrode 8 and U-shaped conductive layer 6 gradually increases so that conductive positioned at gate electrode 8 and U-shaped
Electric field intensity between layer 6 in U-shaped tunneling insulation layer 7 also gradually increases therewith, the electric field intensity in U-shaped tunneling insulation layer 7
When below marginal value, U-shaped tunneling insulation layer 7 still keeps good high-impedance state, the electricity between gate electrode and emitter stage
Potential difference is almost dropped completely between the inner and outer wall both sides of U-shaped tunneling insulation layer 7, is also allowed between base and launch site
Electric potential difference is minimum, therefore base almost flows through without electric current, and therefore device also keeps good off state, and works as U-shaped tunnelling
When electric field intensity in insulating barrier 7 is located at more than marginal value, U-shaped tunneling insulation layer 7 can be produced significantly due to tunneling effect
Tunnelling current, and tunnelling current then can be with the increase of the potential of gate electrode 8 precipitous rising at a terrific speed, and this allows for U
Shape tunneling insulation layer 7 gate electrode it is extremely short potential change interval in low resistance state is rapidly converted into by high-impedance state, when U-shaped tunnelling it is exhausted
Edge layer 7 is in low resistance state, and the resistance that now U-shaped tunneling insulation layer 7 is formed between gate electrode 8 and U-shaped conductive layer 6 is remote little
The resistance formed between U-shaped conductive layer 6 and emitter stage 3, this allows for being defined between base 4 and launch site 3 sufficiently large
Positive bias-voltage, and in the presence of tunneling effect, a large amount of electricity are produced between the inner and outer wall of U-shaped tunneling insulation layer 7
Son is mobile, and as base 4 provides current source, hence in so that defining sufficiently large base electric current between base 4 and launch site 3
The insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, i.e. device is driven to be in opening；
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, using using tunneling insulation layer impedance and tunnelling
Extremely sensitive mutual relation between insulating barrier electric field intensity inside high, inside and outside the side and bottom to U-shaped tunneling insulation layer 7
Thickness and profile height between wall is suitably adjusted, so that it may so that U-shaped tunneling insulation layer 7 is in the extremely short electricity of gate electrode
The conversion between high-impedance state and low resistance state is realized in gesture constant interval, in contrast to MOSFETs, TFETs or common bipolar transistor
Pipe, it is possible to achieve more precipitous sub-threshold slope, that is, significantly improve the switching characteristic of nanometer-grade IC unit component.
Insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer, by insulated gate tunnel produced by U-shaped tunneling insulation layer
The base current that electric current is converted into bipolar transistor is worn, and the amplification characteristic using bipolar transistor is produced to tunneling insulation layer 7
Raw insulation gate tunneling current is amplified, therefore is ensureing that present invention contrast is double in contrast to MOSFETs, TFETs or common
While gated transistors have more excellent switching characteristic, the forward conduction electric current of device has been obviously improved.
The unit and array of the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer proposed by the invention exists
Concrete manufacturing technology steps in SOI wafer are as follows：
Step one, one SOI wafer of offer, the lower section of SOI wafer is the monocrystalline substrate 1 of SOI wafer, SOI wafer
Centre is wafer insulating barrier 2, and the monocrystalline silicon thin film above SOI wafer is used to form launch site 3, base 4 and the collecting zone of device
5, rectangular-shape monocrystal silicon isolated island array as shown in Figure 2 is formed in the SOI wafer for being provided by techniques such as photoetching, etchings
Region, the region is used to further form launch site 3, base 4 and the collecting zone 5 of device；
Step 2, surface is planarized as shown in figure 3, depositing above the wafer after dielectric, preliminarily form stop insulation
Layer 11；
Step 3, as shown in figure 4, by ion implantation technology, in each area of rectangular-shape monocrystal silicon isolated island array
Launch site 3, base 4 and collecting zone 5 are formed on domain, the wherein doping type of base 4 is contrary with launch site 3 and collecting zone 5；
Step 4, as shown in figure 5, deposit metal or heavily doped polysilicon in crystal column surface, and by the beginning of etching technics
Step forms U-shaped conductive layer；
Step 5, surface is planarized after dielectric and is exposed for forming U-shaped as shown in fig. 6, depositing above the wafer
The metal of conductive layer 6 or heavily doped polysilicon；
Step 6, as shown in fig. 7, further forming U-shaped conductive layer 6 by etching technics；
Step 7, as shown in figure 8, tunnelling dielectric is deposited above wafer planarizes surface to exposing U-shaped conductive layer 6
With barrier insulating layer 11, U-shaped tunneling insulation layer 7 is preliminarily formed；
Step 8, as shown in figure 9, further forming U-shaped tunneling insulation layer 7 by etching technics；
Step 9, as shown in Figure 10, deposits metal or heavily doped polysilicon above wafer, and planarization surface is to exposing U
Shape conductive layer 6, U-shaped tunneling insulation layer 7 and barrier insulating layer 11, form gate electrode 8；
Step 10, as shown in figure 11, deposits dielectric further to generate barrier insulating layer 11 above wafer, passes through
Etching technics etches the through hole for forming emitter stage 9 and colelctor electrode 10 in the top of launch site 3 and collecting zone 5, and logical
Metal is injected in hole to produce emitter stage 9 and colelctor electrode 10.
Claims (6)
1. there is the insulated gate tunnelling bipolar transistor of U-shaped tunneling insulation layer, it is characterised in that：Using only comprising monocrystalline substrate
（1）Body Silicon Wafer as generating device substrate, or using including monocrystalline substrate simultaneously（1）With wafer insulating barrier（2）SOI
Substrate of the wafer as generating device；Launch site（3）, base（4）And collecting zone（5）Positioned at the monocrystalline substrate of body Silicon Wafer
（1）Or the wafer insulating barrier of SOI wafer（2）Top, base（4）Positioned at launch site（3）With collecting zone（5）Between；Emitter stage
（9）Positioned at launch site（3）Top；Colelctor electrode（10）Positioned at collecting zone（5）Top；U-shaped conductive layer（6）Positioned at base（4）
Top；U-shaped tunneling insulation layer（7）Positioned at U-shaped conductive layer（6）Inner side；Gate electrode（8）Positioned at U-shaped tunneling insulation layer（7）'s
Inner side；Barrier insulating layer（11）Between device cell and each electrode between；Launch site（3）And collecting zone（5）Doping class
Type and base（4）On the contrary.
2. the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer according to claim 1, it is characterised in that：U
Shape conductive layer（6）With launch site（3）And emitter stage（9）Between pass through barrier insulating layer（11）It is isolated from each other；U-shaped conductive layer（6）
With collecting zone（5）And colelctor electrode（10）Between pass through barrier insulating layer（11）It is isolated from each other；Adjacent launch site（3）With collecting zone
（5）Between pass through barrier insulating layer（11）It is isolated from each other；Adjacent emitter stage（9）With colelctor electrode（10）Between by stop insulation
Layer（11）It is isolated from each other.
3. the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer according to claim 1, it is characterised in that：U
Shape tunneling insulation layer（7）It is the insulating barrier for producing gate electrode tunnelling current, with English capitalization " u "-shaped structure.
4. the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer according to claim 1, it is characterised in that：U
Shape conductive layer（6）Medial wall to U-shaped tunneling insulation layer（7）Lateral wall formed three bread enclose；U-shaped conductive layer（6）Bottom
With base（4）Form Ohmic contact, U-shaped conductive layer（6）It is metal material or same base（4）With identical dopant type
Heavily doped polysilicon.
5. the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer according to claim 1, it is characterised in that：
Gate electrode（8）By U-shaped tunneling insulation layer（7）The bread of inwall three wrap up in, be electrode that control device is switched on and off.
6. a kind of manufacturing process of the insulated gate tunnelling bipolar transistor with U-shaped tunneling insulation layer as claimed in claim 1,
It is characterized in that：The concrete manufacturing technology steps of its unit and array in SOI wafer are as follows：
Step one, one SOI wafer of offer, the lower section of SOI wafer is the monocrystalline substrate of SOI wafer（1）, in SOI wafer
Between be wafer insulating barrier（2）, the monocrystalline silicon thin film above SOI wafer is used to form the launch site of device（3）, base（4）And collection
Electric area（5）, rectangular-shape monocrystal silicon isolated island array region is formed in the SOI wafer for being provided by photoetching, etching technics, should
Region is used to further form the launch site of device（3）, base（4）And collecting zone（5）；
Step 2, deposit above the wafer and planarize surface after dielectric, preliminarily form barrier insulating layer（11）；
Step 3, by ion implantation technology, form launch site on each region of rectangular-shape monocrystal silicon isolated island array
（3）, base（4）And collecting zone（5）, wherein base（4）Doping type will and launch site（3）And collecting zone（5）On the contrary；
Step 4, metal or heavily doped polysilicon are deposited in crystal column surface, and U-shaped conductive layer is preliminarily formed by etching technics
（6）；
Step 5, deposit above the wafer and planarize after dielectric surface and expose for forming U-shaped conductive layer（6）Metal
Or heavily doped polysilicon；
Step 6, U-shaped conductive layer is further formed by etching technics（6）；
Step 7, deposit above wafer tunnelling dielectric and planarize surface to exposing U-shaped conductive layer（6）And barrier insulating layer
（11）, preliminarily form U-shaped tunneling insulation layer（7）；
Step 8, U-shaped tunneling insulation layer is further formed by etching technics（7）；
Step 9, metal or heavily doped polysilicon are deposited above wafer, planarization surface is to exposing U-shaped conductive layer（6）, U-shaped
Tunneling insulation layer（7）And barrier insulating layer（11）, form gate electrode（8）；
Step 10, above wafer dielectric is deposited further generating barrier insulating layer（11）, sent out by etching technics
Penetrate area（3）And collecting zone（5）Top etch for forming emitter stage（9）And colelctor electrode（10）Through hole, and on wafer
Surface deposition metal level, is filled with metal through hole, then metal level is performed etching, and forms emitter stage（9）And colelctor electrode（10）.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861325B1 (en) * | 2002-09-24 | 2005-03-01 | Advanced Micro Devices, Inc. | Methods for fabricating CMOS-compatible lateral bipolar junction transistors |
| CN102412302A (en) * | 2011-10-13 | 2012-04-11 | 北京大学 | Tunneling field-effect transistor for inhibiting bipolar effect and preparation method thereof |
| CN103117306A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Tunnel FET and methods for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861325B1 (en) * | 2002-09-24 | 2005-03-01 | Advanced Micro Devices, Inc. | Methods for fabricating CMOS-compatible lateral bipolar junction transistors |
| CN102412302A (en) * | 2011-10-13 | 2012-04-11 | 北京大学 | Tunneling field-effect transistor for inhibiting bipolar effect and preparation method thereof |
| CN103117306A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Tunnel FET and methods for forming the same |
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