CN103531636B - Source grid leak controls single doping type tunneling transistor altogether - Google Patents
Source grid leak controls single doping type tunneling transistor altogether Download PDFInfo
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- CN103531636B CN103531636B CN201310508661.0A CN201310508661A CN103531636B CN 103531636 B CN103531636 B CN 103531636B CN 201310508661 A CN201310508661 A CN 201310508661A CN 103531636 B CN103531636 B CN 103531636B
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- 230000005641 tunneling Effects 0.000 title claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000010408 film Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000009471 action Effects 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an introduces a collection grid leak to control single doping type tunneling transistor altogether, source electrode and drain electrode with semiconductive thin film in addition to contacting, also it is attached respectively to close on the top of the insulating medium layer of source electrode and drain electrode both sides, makes it that there is certain control action to the source electrode of semiconductive thin film and the electric field and Carrier Profile of drain electrode part respectively.When device works, backward voltage is applied to source electrode；Forward voltage is applied to drain electrode；And by adjusting the voltage of gate electrode, the semiconductive thin film area compared with low energy gap width that has below gate electrode is set to realize exhausting for carrier, virtual PIN junction is realized with this, this technical barrier that common tunneling transistor can occur to spread again for the heavy doping PIN junction under deep nanoscale among heat treatment process is avoided, source-drain contact resistance can also be reduced by adjusting the voltage of source electrode and drain electrode.
Description
Technical field
The present invention relates to super large-scale integration manufacturing field, relates generally to a kind of superelevation integrated level that is applied to and integrates electricity
The source grid leak co- controlling type list doping type tunneling field-effect transistor of road manufacture.
Background technology
PIN-type tunneling field-effect transistor (TFETs), it is wide by introducing the forbidden bands such as compound semiconductor, SiGe or germanium
The tunnelling part that narrower material carrys out generating device is spent, and is used as gate electrode Jie by introducing the megohmite insulant of high-k
Matter layer, contrast INVENTIONConventional metal-oxide semiconductor field effect transistor（MOSFETs）, PIN-type tunneling field-effect transistor possesses
More preferable switching characteristic and lower power consumption, therefore MOSFETs devices can be substituted and turn into ultra-large integrated electricity of future generation
Road logic unit or memory cell.
Yet among the process of heat treatment, the P areas or N areas of heavy doping can occur to spread again, therefore, with device
The continuous diminution of part size, want to realize PIN structural under tens or more than ten nanometer of size, for doping process and Re Chu
The requirement of science and engineering skill is high.
The content of the invention
Goal of the invention
To solve the above problems, the present invention proposes one kind using source electrode, gate electrode and drain electrode co- controlling come real
The existing single doping type tunneling field-effect transistor that need not generate physics PIN structural, effectively prevent common tunneling transistor pair
This technical barrier spread again can occur among heat treatment process for the heavy doping PIN junction under deep nanoscale.
Technical scheme
The present invention is achieved through the following technical solutions：
One introduces a collection grid leak controls single doping type tunneling transistor, including SOI wafer silicon substrate, SOI wafer silicon substrate top altogether
For SOI wafer insulating barrier, it is characterised in that：It is semiconductive thin film above SOI wafer insulating barrier, is at the upper side of semiconductive thin film
Source electrode, opposite side are drain electrode, and centre is insulating medium layer, close to source electrode position between semiconductive thin film and insulating medium layer
It is low energy gap width semiconductive thin film area to put place；It is zone isolation dielectric, insulating medium layer and layer above insulating medium layer
Between isolate dielectric between be gate electrode.
Source electrode is also attached to closing on for grid electrode insulating dielectric layer in addition to the source electrode portion with semiconductive thin film is connected
The top of source electrode side.
In addition to drain electrode is connected except the drain electrode part with semiconductive thin film, be also attached to insulating medium layer closes on drain electrode one
The top of side.
Insulating medium layer is silica or the dielectric with high-k.
Low energy gap width semiconductive thin film area is the semi-conducting material with low energy gap width.
Low energy gap width semiconductive thin film area is germanium, SiGe or carborundum.
Advantage and effect
The invention has the advantages that and beneficial effect：
Because single doping type tunneling field-effect transistor proposed by the invention need not generate common tunneling transistor
PIN structural, but virtual PIN structural is generated under the co- controlling by source electrode, gate electrode and drain electrode, thus avoid general
Logical tunneling transistor can occur to spread again for the heavy doping PIN junction under deep nanoscale among heat treatment process
This technical barrier.
Brief description of the drawings
Fig. 1 is single doping type tunneling field-effect thin film transistor (TFT) of this introduces a collection grid leak co- controlling of the invention in SOI substrate
The two-dimensional structure schematic diagram of upper formation.The tunnelling part of raceway groove is by taking SiGe as an example in figure.
Fig. 2 to Fig. 9 is the single doping type tunneling field-effect thin film transistor (TFT) for preparing this introduces a collection grid leak co- controlling of the invention
And its concrete technology flow process figure of array.
Reference is said：
1st, source electrode；2nd, semiconductive thin film；3rd, low energy gap width semiconductive thin film area；4th, drain electrode；5th, insulating medium layer；
6th, gate electrode；7th, zone isolation dielectric；8th, SOI wafer insulating barrier；9th, SOI wafer silicon substrate.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
The present invention is that one kind need not generate physics PIN junction using source electrode, gate electrode and drain electrode co- controlling to realize
Single doping type tunneling field-effect transistor of structure.Described tunneling field-effect transistor, it need to only generate single doping of p-type or N-type
Structure, by using the Carrier Profile class of the co- controlling semiconductive thin film regional of source electrode, gate electrode and drain electrode
The method of type realizes virtual PIN junction, therefore avoids common tunneling transistor for the heavy doping PIN under deep nanoscale
This technical barrier spread again can occur among heat treatment process for knot.
This introduces a collection grid leak of the invention controls single doping type tunneling transistor, including SOI wafer silicon substrate 9, SOI wafer silicon lining altogether
The top of bottom 9 is SOI wafer insulating barrier 8, it is characterised in that：The top of SOI wafer insulating barrier 8 is semiconductive thin film 2, semiconductive thin film
2 upper sides are source electrode 1, and opposite side is drain electrode 4, and centre is insulating medium layer 5, semiconductive thin film 2 and insulating medium layer 5
Between close to source electrode opening position be low energy gap width semiconductive thin film area 3；The top of insulating medium layer 5 is situated between for zone isolation insulation
Matter 7, it is gate electrode 6 between insulating medium layer 5 and zone isolation dielectric 7.
For source electrode 1 in addition to being connected with the source electrode portion of semiconductive thin film 2, be also attached to insulating medium layer 5 closes on source
The top of pole side, make the electric field of its source electrode portion to semiconductor silicon film 2 and Carrier Profile that there is certain control action.
Backward voltage is applied to source electrode 1 when device works, the semiconductor silicon film 2 for so closing on the side of source electrode 1 forms hole
Inversion layer, the backward voltage by adjusting source electrode 1 are sized so that the concentration of hole inversion layer is much larger than doping concentration, and with this
Virtual heavy doping P areas are realized, while reduce the size that semiconductor silicon film 2 closes on the source resistance of source electrode side.
In addition to drain electrode 4 is connected except the drain electrode part with semiconductive thin film 2, be also attached to insulating medium layer 5 closes on leakage
The top of pole side, the electric field and Carrier Profile for making its drain electrode part to semiconductive thin film 2 have certain control action.
Forward voltage is applied to drain electrode 4 when device works, the semiconductor silicon film 2 for so closing on the side of drain electrode 4 forms electronics product
Tired layer, the forward voltage by adjusting drain electrode 4 are sized so that the concentration of electron accumulation layer is much larger than doping concentration, and with this reality
Now virtual heavy doping N areas, while reduce the size that semiconductor silicon film 2 closes on the drain resistance of drain electrode side.
By adjusting the voltage applied on gate electrode 6 so that the low energy gap width semiconductor film positioned at the lower section of gate electrode 6
Film area 3 realizes exhausting for carrier, and virtual intrinsic region is realized with this.By making with the co- controlling of source electrode 1 and drain electrode 4
With realizing virtual P-I-N structures.The energy in low energy gap width semiconductive thin film area 3 is adjusted by adjusting the voltage of gate electrode 6
With degree of crook to control the size of tunnelling current.
Above-mentioned insulating medium layer 5 be silica or with high-k dielectric, such as：Hafnium oxide, four nitrogen
Change three silicon or alundum (Al2O3) etc..Source electrode 1, gate electrode 6 and leakage can be strengthened using the higher insulating medium layer 5 of dielectric constant
Electrode 4 is to semiconductive thin film 2 and Electric Field Distribution, Carrier Profile and the band curvature in low energy gap width semiconductive thin film area 3
The control ability of degree.
Above-mentioned low energy gap width semiconductive thin film area 3 is the list with compared with low energy gap width such as germanium, SiGe or carborundum
Brilliant or compound semiconductor materials.
The course of work of the present invention is as follows：
With N extremely examples, when device works, source electrode 1 applies backward voltage, semiconductive thin film 2 is closed on source electrode 1
Side depleted of electrons, and surface formed concentration be more than the doping concentration of semiconductive thin film 2 hole inversion layer；Drain electrode 4 is applied
Add forward voltage, the side electron accumulation for making semiconductive thin film 2 be closed on drain electrode 4, and be more than in surface formation concentration and partly lead
The electron accumulation layer of the doping concentration of body thin film 2；By adjusting the voltage of gate electrode 6, on the N-type semiconductor film 2 singly adulterated
Form virtual P-I-N structures.
When device works, source electrode 1 applies backward voltage, and drain electrode 4 applies forward voltage, makes semiconductive thin film 2
Both ends form hole inversion layer and electron accumulation layer respectively, therefore reduce the size of source and drain resistance respectively.
When the voltage that gate electrode 6 is applied is relatively low, the band curvature degree in low energy gap width semiconductive thin film area 3 compared with
Small, now device is off state；The voltage applied with gate electrode 6 gradually rises, low energy gap width semiconductive thin film
The band curvature degree in area 3 is consequently increased, and tunnelling current also increases therewith；When gate electrode 6 applies high voltage, low energy gap
The band curvature degree in width semiconductive thin film area 3 is violent, and now device is in opening.
Mutual and adjacent position relation between each region for convenience of description, each region is special in schematic diagram and process chart
Sign size does not represent actual size.And example shown in the present invention is only to realize that source grid leak proposed by the invention is controlled altogether singly to mix
One kind in miscellaneous type tunneling transistor.Deformation caused by technique manufacture deviation be considered as the scope of the present invention it
It is interior.
Above-mentioned source grid leak controls the manufacture method of single doping type tunneling transistor altogether, and step is as follows：
As shown in Figure 2, there is provided a SOI substrate, the semiconductive thin film 2 of top is thinned to below 30nm, using photoetching,
The techniques such as etching etch away the part for being used as tunnel transition.
As shown in figure 3, by epitaxial growth and etching technics, low energy gap width semiconductive thin film area 3 is generated, such as：Germanium
SiClx.
As shown in figure 4, further carving the isolated part between unit, and filled out by depositing silica or silicon nitride
Isolated part is filled to form the zone isolation dielectric 7 between unit；Throw the insulating barrier that the top of semiconductive thin film 2 is etched away after putting down
Part.
As shown in figure 5, depositing high dielectric constant dielectric to be to generate insulating medium layer 5, such as：Hafnium oxide, four nitridations
Three silicon or alundum (Al2O3) etc..Ion implanting is carried out to semiconductive thin film 2 to adulterate to form N-type or p-type, and carve above wafer
Eating away part as shown in the figure, for source electrode 1, the generation of drain electrode 4.
As shown in fig. 6, by Metal deposition and etching technics, source electrode 1 and drain electrode 4 are generated.
As shown in fig. 7, deposit silica or silicon nitride, and the part that by etching technics will act as generating gate electrode is gone
Fall.The zone isolation dielectric 7 formed with this between gate electrode 6 and source electrode 1 and drain electrode 4.
As shown in figure 8, gate electrode 6 is generated by depositing polysilicon and etching technics.
As shown in figure 9, the zone isolation dielectric 7 of deposit is in source electrode 1 and the top of drain electrode 4, by etching work
Skill generation source electrode 1, the through hole of drain electrode 4, and metal is injected further to generate source electrode 1 and drain electrode 4.
Claims (4)
1. an introduces a collection grid leak controls single doping type tunneling transistor, including SOI wafer silicon substrate altogether（9）, SOI wafer silicon substrate（9）
Top is SOI wafer insulating barrier（8）, it is characterised in that：SOI wafer insulating barrier（8）Top is semiconductive thin film（2）, semiconductor
Film（2）Upper side is source electrode（1）, opposite side is drain electrode（4）, centre is insulating medium layer（5）, semiconductive thin film
（2）With insulating medium layer（5）Between close to source electrode opening position be low energy gap width semiconductive thin film area（3）；Insulating medium layer
（5）Top is zone isolation dielectric（7）, insulating medium layer（5）With zone isolation dielectric（7）Between be gate electrode
（6）；
Source electrode（1）Remove and semiconductive thin film（2）Source electrode portion connection outside, be also attached to insulating medium layer（5）Close on
The top of source electrode side；
Drain electrode（4）Remove and semiconductive thin film（2）Drain electrode part connection outside, be also attached to insulating medium layer（5）Close on
The top of drain electrode side.
2. source grid leak according to claim 1 controls single doping type tunneling transistor altogether, it is characterised in that：Insulating medium layer
（5）For silica or with high-k dielectric.
3. source grid leak according to claim 1 controls single doping type tunneling transistor altogether, it is characterised in that：Low energy gap width half
Conductor thin film area（3）For the semi-conducting material with low energy gap width.
4. source grid leak according to claim 3 controls single doping type tunneling transistor altogether, it is characterised in that：Low energy gap width half
Conductor thin film area（3）For germanium, SiGe or carborundum.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310508661.0A CN103531636B (en) | 2013-10-25 | 2013-10-25 | Source grid leak controls single doping type tunneling transistor altogether |
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| CN201310508661.0A CN103531636B (en) | 2013-10-25 | 2013-10-25 | Source grid leak controls single doping type tunneling transistor altogether |
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| Publication Number | Publication Date |
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| CN103531636A CN103531636A (en) | 2014-01-22 |
| CN103531636B true CN103531636B (en) | 2017-12-01 |
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| CN104409489B (en) * | 2014-12-08 | 2017-04-26 | 沈阳工业大学 | High-integrated groove insulated gate tunneling bipolar enhancement transistor and manufacture method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355102A (en) * | 2007-07-25 | 2009-01-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
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| US8441000B2 (en) * | 2006-02-01 | 2013-05-14 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
| US20090034355A1 (en) * | 2007-07-30 | 2009-02-05 | Qimonda Ag | Integrated circuit including memory cells with tunnel fet as selection transistor |
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| CN101355102A (en) * | 2007-07-25 | 2009-01-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
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