CN101958344B - Green field effect transistor and manufacturing method thereof - Google Patents
Green field effect transistor and manufacturing method thereof Download PDFInfo
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- CN101958344B CN101958344B CN2009100549499A CN200910054949A CN101958344B CN 101958344 B CN101958344 B CN 101958344B CN 2009100549499 A CN2009100549499 A CN 2009100549499A CN 200910054949 A CN200910054949 A CN 200910054949A CN 101958344 B CN101958344 B CN 101958344B
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Abstract
The invention relates to a green field effect transistor and a manufacturing method thereof, wherein the green field effect transistor comprises a silicon on insulator, a source electrode, a drain electrode and a channel body, wherein the silicon on insulator comprises a silicon substrate as well as a buried oxide layer and top layer silicon which are sequentially located on the silicon substrate; the source electrode and the drain electrode are located in the top layer silicon and isolated from each other and have different doping types; the cylindrical channel body is located between the source electrode and the drain electrode and sequentially comprises a source connector and a pocket injection layer from a cylindrical core to outside, one end of the channel body is connected to the source electrode, and the other end of the channel body is connected to the drain electrode; the source connector is electrically connected with the source electrode, and the pocket injection layer is electrically connected with the drain electrode; and a grid electrode structure located on the surface of the pocket injection layer of the channel body comprises a grid dielectric layer and a grid electrode on the surface of the grid dielectric layer. The green field effect transistor has the advantages of high response speed and sensitive switching characteristic, satisfies the requirements of a small size scaled-down device on reducing energy consumption and avoids generating a series of second-order effects.
Description
Technical field
The present invention relates to a kind of field-effect transistor, relate in particular to a kind of green field effect transistor and manufacturing approach thereof.
Background technology
In the evolution of semiconductor very lagre scale integrated circuit (VLSIC), transistor is under the guiding of cmos device scaled (scaling), and density and performance are followed Moore's Law and obtained ensured sustained development and systematization growth.Yet when semicon industry develops into 45 nanometer nodes or smaller szie; The power consumption of chip and power dissipation density have formed a problem of needing solution badly gradually; Causing the appearance reason of power consumption difficulty is that device density constantly increases, and supply voltage has kept the standard as technologies at different levels with 5V for a long time.Therefore external voltage source scaled (VDD-scaling) has more become the bottleneck of a restriction MOS memory (MOSFET) development.
At present; Someone proposes a kind of like this theory; In MOS memory, use grid bias to induce the restriction that can not receive external voltage source scaled (VDD-scaling) with tunneling effect (band to band-tunneling); Charge carrier need not be crossed over potential barrier but directly realize moving of charge carrier through tunnelling in above-mentioned effect, form electric current, can effectively reduce the energy consumption of device.Based on above-mentioned theory; People such as Chenming Hu are inferior the disclosing through adopting green crystal pipe (Green Transistor) to reduce the scheme of external voltage source in the 14th to 15 beginning of the page of " VLSI Technology; Systems and Applications; 2008.VLSI-TSA 2008.International Symposium on " (international ultra-large type IC technology, system and application (VLSI-TSA) Conference Papers collection in 2008), and article name is " GreenTransistor-A VDD Scaling Path for Future Low Power ICs ".
As shown in Figure 1, the sectional structure chart for above-mentioned green crystal pipe comprises: silicon-on-insulator (SOI) 10, and said silicon-on-insulator 10 comprises substrate 100, oxygen buried layer 110 and top layer silicon 101; Be positioned at gate dielectric layer 106 and gate electrode 107 on the top layer silicon 101 successively, both have constituted the grid structure of green crystal pipe; Said green crystal pipe also comprises source electrode 102, the drain electrode 103 that is positioned at top layer silicon 101, gate dielectric layer 106 both sides, and said source electrode 102 is different with the doping type of drain electrode 103; Also comprise the adjacent pocket implanted layer 104 and shallow doped region 105 that are positioned at top layer silicon 101; Said adjacent pocket implanted layer 104 is corresponding with the position of gate dielectric layer 106 with shallow doped region 105; The doping type of said pocket implanted layer 104 is identical with drain electrode 103, and is electrically connected with drain electrode 103 through shallow doped region 105; The degree of depth of said pocket implanted layer 104 is less than shallow doped region 105, and the bottom of source electrode 102 extend through pocket implanted layers 104 is adjacent with shallow doped region 105.
Be example with P type green crystal pipe (doping type of pocket implanted layer 104 is that the doping type of P type, source electrode 102 is that N type, drain electrode 103 doping type are the P type) below, its operation principle is further introduced.
As shown in Figure 2, be near the energy band diagram the P type pocket implanted layer 104 of P type green crystal pipe, wherein dotted portion is that transistor can be with can be with when solid line is partly opened for transistor when closing.In off position down, when promptly grid did not load bias voltage, conduction band Ec bottom was higher than electromotive force position, valence band Ev top, had very big potential barrier between conduction band Ec and the valence band Ev, and can not produce charge carrier and shift this moment between P type pocket implanted layer 104 and the N type source electrode 102.Under opening, when promptly grid loaded back bias voltage, P type pocket implanted layer 104 electromotive forces reduced, and can be with further to be bent upwards, and made the electromotive force position, top of valence band Ev surpass conduction band Ec bottom, had formed tunnel effect between conduction band Ec and the valence band Ev.In conjunction with shown in Figure 3; When having forward voltage between source electrode 102, the drain electrode 103; The electronics of P type pocket implanted layer 104 will form continuous electron stream to N type source electrode 102 tunnellings; Hole in the P type pocket implanted layer 104 will flow to P type drain electrode 103 via shallow doped region 105 simultaneously, thereby device can be worked.
Mainly rely on a kind of charge carrier conducting different with existing MOS transistor, the electric current of green crystal pipe comprises electronics and hole simultaneously, therefore; Its subthreshold voltage amplitude of oscillation is less, less than 60mV/decade, even can be less than 10mV/decade; And threshold voltage is far below existing MOS transistor; Can be low to moderate 0.2V, the energy consumption under the comparable size is the good selection that dark nano-scale substitutes the MOS transistor device much smaller than existing MOS device.
The notion of green crystal pipe only is in the research of theoretical model at present, does not still have report and be applied to semi-conductive manufacturing process.
Summary of the invention
The problem that the present invention solves provides a kind of green field effect transistor structure, and is compatible mutually with existing C MOS technology, and satisfies the demand that device size cuts down the consumption of energy after scaled.
For addressing the above problem, the invention provides a kind of green field effect transistor, comprising:
Silicon-on-insulator, said silicon-on-insulator comprise silicon base, are positioned at oxygen buried layer and top layer silicon on the silicon base successively;
Being positioned at top layer silicon isolates mutually and different source electrode, the drain electrode of doping type;
Channel body between source electrode, drain electrode, said channel body is cylindrical, and an end connects source electrode, and the other end connects drain electrode, outside the post mind-set, comprises source connector, pocket implanted layer successively; Said source connector is electrically connected with source electrode, and said pocket implanted layer is electrically connected with drain electrode;
Be positioned at the lip-deep grid structure of pocket implanted layer of channel body, comprise the gate electrode on gate dielectric layer and gate dielectric layer surface.
As preferred version, between drain electrode and channel body, also be formed with shallow doped region, the doping type of said shallow doped region is identical with drain electrode, and the doping content that doping content drains is low.
As possibility, said gate dielectric layer is around cylindrical channel body, and the surface of coating pocket implanted layer; Said gate electrode covering gate dielectric layer surface.
As possibility, said channel body section radius scope is that 5-50nm, length range are 5-50nm.
As preferred version, said source electrode, drain electrode and surface gate electrode are formed with dielectric spacer layer.
As possibility, the material of making the pocket implanted layer comprises Si, Ge, SiGe, GaAs, InP, InAs or InGaAs.
The present invention also provides a kind of manufacturing approach of green field effect transistor, comprising:
Silicon-on-insulator is provided, oxygen buried layer and top layer silicon that said silicon-on-insulator comprises silicon base and is positioned at silicon base successively, graphical said top layer silicon forms first source area, first drain region and first channel body;
The said oxygen buried layer of etching makes the channel body bottom of winning unsettled;
First channel body that plasma doping and etching are unsettled forms cylindrical source connector;
The surface of connector forms the pocket implanted layer in said cylindrical source, and said pocket implanted layer doping type is opposite with the source connector;
Surface at the pocket implanted layer forms gate dielectric layer and gate electrode successively;
Said first source area of plasma doping and first drain region form source electrode, drain electrode respectively, and said source electrode is identical with the doping type of source connector, and said drain electrode is identical with pocket implanted layer doping type.
As possibility, the said oxygen buried layer of said etching makes the channel body bottom of winning unsettled, specifically comprises: the downward etching oxygen buried layer in silicon top on insulator, expose the oxygen buried layer of said first channel body bottom; The oxygen buried layer of side direction etching first channel body bottom makes the channel body of winning unsettled.
As possibility; First channel body that said plasma doping and etching are unsettled forms cylindrical source connector, specifically comprises: first channel body is carried out over etching; And then it is firm to carry out high annealing, and said plasma doping carries out before etching or after the etching.
As preferred version, between drain electrode and pocket implanted layer, source connector, form shallow doped region, the doping type of said shallow doped region with drain identically, doping content is lower.
The manufacturing approach of green field effect transistor according to the invention also comprises: at source electrode, drain electrode and surface gate electrode deposition dielectric spacer layer, and etching formation contact hole, draw interconnection line.
Compare with existing green crystal pipe; The channel body of green field effect transistor provided by the present invention forms cylindrical structural, through the opening and closing of making alive oxide-semiconductor control transistors on gate electrode, on the one hand; The subthreshold value amplitude of oscillation is little; Threshold voltage is low, has satisfied the demand that device under the small size cuts down the consumption of energy after scaled, and has avoided the generation of a series of second-order effects; On the other hand, it is strong to have driving force, and response speed is fast, the switching characteristic sensitive characteristics.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purposes, characteristic and advantage of the present invention will be more clear.The parts identical with prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size of layer with the zone.
Fig. 1 is an existing P type green crystal tubular construction model sketch map;
Fig. 2 is an existing P type green crystal mouth of pipe bag implanted layer energy band diagram;
Fig. 3 is an existing P type green crystal pipe opening carrier mobility sketch map;
Fig. 4 is a green field effect transistor cross-sectional view of the present invention;
Fig. 5 is a N type raceway groove green field effect transistor cross-sectional view of the present invention;
Fig. 6 a is the raceway groove physical efficiency band sketch map of N type raceway groove green field effect transistor closed condition;
Fig. 6 b is the raceway groove physical efficiency band sketch map of N type raceway groove green field effect transistor opening;
Fig. 7 is a P type raceway groove green field effect transistor cross-sectional view of the present invention;
Fig. 8 a is the raceway groove physical efficiency band sketch map of P type channel-type green field effect transistor closed condition;
Fig. 8 b is the raceway groove physical efficiency band sketch map of P type channel-type green field effect transistor opening;
Fig. 9 is a green manufacturing method for field effect transistor flow chart of steps according to the invention;
Figure 10 a to Figure 21 is the manufacturing process profile of N type raceway groove green field effect transistor according to the invention.
Embodiment
Known from prior art, the green crystal pipe has lower energy consumption and stable device property under small size, has satisfied the scaled low energy consumption demand of VDD, and on this basis, the present invention provides a kind of new green field effect transistor.
Fig. 4 is a green field effect transistor cross-sectional view provided by the invention.Comprise:
Silicon-on-insulator 10, said silicon-on-insulator comprise silicon base 100, are positioned at oxygen buried layer 110 and top layer silicon 101 on the silicon base 100 successively;
Be positioned at top layer silicon 101 is isolated mutually and doping type is different source electrode 1, drain electrode 2;
Channel body between source electrode 1, drain electrode 2, said channel body is cylindrical, and an end connects source electrode 1, and the other end connects drain electrode 2, outside the post mind-set, comprises source connector 4, pocket implanted layer 3 successively; Said source connector 4 is electrically connected with source electrode 1, and said pocket implanted layer 3 is electrically connected with drain electrode 2.
Be positioned at the pocket implanted layer 3 lip-deep grid structures of channel body, comprise the gate electrode 7 on gate dielectric layer 6 and gate dielectric layer surface.Said gate dielectric layer 6 is around cylindrical channel body, and the surface of coating pocket implanted layer 3; The surface of said gate electrode 7 covering gate dielectric layers 6.
Wherein, the channel length of channel body is relevant with the size of pocket implanted layer 3 and source connector 4, in actual process, can adjust as required; Among the present invention, said channel body section radius scope is that 5-50nm, length range are 5-50nm.
Between drain electrode 2 and channel body, also be formed with shallow doped region 5, the doping type of said shallow doped region 5 with drain 2 identically, drain 2 doping content of doping content is low.The purpose that forms said shallow doped region 5 is further to reduce the especially drain voltage between pocket implanted layer and the drain electrode of channel body, improves pocket implanted layer 3 and the carrier mobility speed that drains between 2 simultaneously.
As preferred version, said source electrode 1, drain electrode 2 and gate electrode 7 surfaces also are formed with the dielectric spacer layer (not shown).
The material of making pocket implanted layer 3 can be Si, Ge, SiGe, GaAs, InP, InAs or InGaAs, with compatible mutually with existing C MOS manufacturing process.
Above-mentioned green field effect transistor shown in Figure 4, its channel type can be divided into N type (pocket implanted layer doping type is the N type) and P type (pocket implanted layer doping type is the P type).
Below with the channel type for the N type is that example is explained its operation principle, please with reference to Fig. 5, be N type raceway groove green field effect transistor cross-sectional view.Wherein, the doping type of pocket implanted layer 203 is the N+ type; The doping type of source electrode 201, source connector 204 is the P+ type; The doping type of drain electrode 202 is the N+ type; The doping type of shallow doped region 205 is the N-type.
Fig. 6 a and Fig. 6 b are that green field effect transistor shown in Figure 5 is in the energy band diagram of closing with opening lower channel body, because channel body is cylindrical, the periphery is the pocket implanted layer, and the post heart is the source connector, and therefore illustrating energy band diagram is symmetrical distribution.In conjunction with the operation principle that N type raceway groove green field effect transistor is discussed below Fig. 5, Fig. 6 a and Fig. 6 b, wherein P+ source electrode 201 ground connection.
At first with reference to Fig. 6 a and Fig. 5; When the voltage Vg of gate electrode 207 is changed to zero or ground connection; The electromotive force position at the valence band Ev top of the pocket implanted layer 203 of N+ type and P+ type source connector 204 is all low than the bottom of conduction band Ec at this moment; Have potential barrier between conduction band Ec and the valence band Ev, between N+ type pocket implanted layer 203 and P+ type source connector 204, tangible carrier mobility can not take place, it is that N type raceway groove green field effect transistor is closed that whole transistor is in off position.
Combine Fig. 6 b and Fig. 6 again, when gate electrode 207 voltage Vg were positive voltage, N+ type pocket implanted layer 203 and being with of P+ type source connector 204 further were bent upwards; After the voltage Vg of gate electrode 207 has surpassed threshold voltage; Band curvature is enough big; Make the near interface of in P+ type source connector 204 and N+ type pocket implanted layer 203; The electromotive force position at valence band Ev top has all surpassed the bottom of conduction band Ec, forms tunnel effect between conduction band Ec and the valence band Ev, and this moment, transistor was in opening.If applying bias between source, drain electrode; Be that the external voltage Vdd of N+ type drain electrode 202 is when being positive voltage; The electronics of P+ type source connector 204 is pocket implanted layer 203 tunnellings of N+ type laterally; And via the shallow doped region 205 of N-type to N+ type drain electrode 202 migrations, and the hole that P+ type source connector 204 is produced is to 201 migrations of P+ type source electrode, above-mentioned two kinds of mobility of charge carrier will will form the electric current of continous-stable in channel body.
Fig. 7 is a P type raceway groove green field effect transistor structure sketch map, and wherein the doping type of pocket implanted layer 303 is the P+ type; The doping type of source electrode 301, source connector 304 is the N+ type; The doping type of drain electrode 302 is the P+ type; The doping type of shallow doped region 305 is the P-type.
Fig. 8 a and Fig. 8 b are that green field effect transistor shown in Figure 7 is in the energy band diagram of closing with opening lower channel body.In conjunction with Fig. 7, Fig. 8 a and Fig. 8 b, the operation principle of P type raceway groove green field effect transistor is discussed, wherein N+ type source electrode 301 ground connection.
At first with reference to Fig. 8 a and Fig. 7; When gate electrode 307 voltage Vg were changed to zero or ground connection, P type raceway groove green field effect transistor was closed, at this moment P+ type pocket implanted layer 303 and N+ type source connector 304; The electromotive force position at valence band Ev top is all low than the bottom of conduction band Ec; Have potential barrier between conduction band Ec and the valence band Ev, between P+ type pocket implanted layer 303 and N+ type source connector 304, tangible carrier mobility can not take place, whole transistor is in off position.
Refer again to Fig. 8 b and Fig. 7, when gate electrode 307 voltage Vg are negative voltage, P+ type pocket implanted layer 303 and N+ type source connector 304 can be with further downwarping; After the voltage Vg of gate electrode 307 has surpassed threshold voltage; Band curvature makes near the contact-making surface of N+ type source connector 304 and P+ type pocket implanted layer 303; The electromotive force position at valence band Ev top surpasses the bottom of conduction band Ec; Form tunnel effect between conduction band Ec and the valence band Ev, this moment, transistor was in opening, if between source electrode 301, drain electrode 302, add forward bias; Be that the external voltage Vdd of P+ type drain electrode 302 is when being negative voltage; The electronics of P+ type pocket implanted layer 303 will be toward N+ type source connector 304 tunnellings and flow to N+ type source electrode 301, and the hole that P+ type pocket implanted layer 303 is produced will be via the shallow doped region 305 of P-type to P+ type drain electrode 302 migrations, above-mentioned two kinds of mobility of charge carrier will will form the electric current of continous-stable in channel body.
Compare with existing green crystal pipe, green field effect transistor of the present invention is made into channel body cylindrical, and the pocket implanted layer is around the connector surface, source of the post heart; In the confined space; Have bigger contact area between the two, therefore have the characteristics that the subthreshold value amplitude of oscillation is little, threshold voltage is low of green crystal pipe on the one hand, satisfy the demand of low-power consumption; Can form bigger source-drain current on the other hand; Have stronger driving force, also be easier to control in use, have response speed and good switching characteristic fast.
For forming the green field effect transistor of said structure, the present invention also provides a kind of manufacturing approach of green field effect transistor.As shown in Figure 9, basic step comprises:
S1, silicon-on-insulator is provided, oxygen buried layer and top layer silicon that said silicon-on-insulator comprises silicon base and is positioned at silicon base successively, graphical said top layer silicon.
Said graphical top layer silicon; Specifically comprise: the zone of confirming to form the green field effect transistor in advance; Use the mask etching top layer silicon,, form corresponding first source area, first drain region and first channel body between first source area and first drain region until exposing oxygen buried layer.
S2, on insulator the downward etching oxygen buried layer in silicon top, expose the oxygen buried layer of said first channel body bottom; The certain thickness oxygen buried layer in side direction etching first channel body bottom forms perforation, makes that said first channel body is unsettled.
First channel body that S3, plasma doping and etching are unsettled forms cylindrical source connector;
The said first unsettled channel body is the irregular cylinder that there are corner angle at the edge; In etching process, the etch rate of the edges and corners at edge is always fast than other positions, therefore the over etching of process certain hour; It is cylindrical that first channel body will be tending towards, and then adopt high annealing further firm.
Said plasma doping can carry out also can after etching, carrying out before etching, and two steps can be used identical mask, finally form cylindrical source connector.The sectional area of said cylindrical source connector is little than first channel body, and concrete size can be selected through the time of controlling said etching.
S4, the surface of connector forms the pocket implanted layer in cylindrical source; Said pocket implanted layer around and coat the surface of source connector; Can pass through extension (EPI) or atomic deposition (ALD) and form, concrete thickness is selected as required, and doping type is opposite with the source connector.
Said pocket implanted layer and source connector constitute cylindrical channel body, and the size of the thickness of pocket implanted layer and bonding pad, source has determined the channel body size.As preferred version, the diameter of formed channel body is not more than the thickness of top layer silicon.
S5, form gate dielectric layer and gate electrode successively on the surface of pocket injection region, said gate dielectric layer around and coat the surface of pocket implanted layer, can be through chemical vapour deposition (CVD) CVD or atomic deposition ALD formation; The surface of said gate electrode wrapped-gate dielectric layer, and fill up the remaining space between gate dielectric layer bottom and the oxygen buried layer, also can form through chemical vapour deposition (CVD) CVD or atomic deposition ALD.
S6, first source area and first drain region are carried out plasma doping respectively, form source electrode and drain electrode, the doping type of said source electrode is identical with the source connector, and the doping type of said drain electrode is identical with the pocket implanted layer.
As possibility, can also earlier first source area and first drain region be carried out plasma doping simultaneously, one of them carries out counter-doping to first source area or first drain region then, and substep forms source region or drain region.
As preferred version, between drain electrode and pocket implanted layer, source connector, also be formed with shallow doped region, the doping type of said shallow doped region with drain identically, doping content is lower.
S7, at source electrode, drain electrode and surface gate electrode deposition dielectric spacer layer, and etching forms contact hole, draws interconnection line.
Below in conjunction with concrete formation process section, the manufacturing approach of green field effect transistor of the present invention is done further to introduce.
To shown in Figure 21, be the manufacturing process profile of N type raceway groove green field effect transistor according to the invention like Figure 10 a.
Like Figure 10 a and Figure 10 b, form silicon-on-insulator 10, oxygen buried layer 110 and top layer silicon 101 that said silicon-on-insulator comprises silicon base 100 and is positioned at silicon base successively, graphical said top layer silicon 101.Said oxygen buried layer 110 materials are silica, and top layer silicon 101 materials are monocrystalline silicon or polysilicon.
Wherein Figure 10 b is the top visual angle from silicon-on-insulator; Figure 10 a is the X-X ' profile among Figure 10 b; Said graphical top layer silicon 101 specifically comprises: confirm to form the zone of green field effect transistor in advance, use mask etching top layer silicon 101; Until exposing oxygen buried layer 110, form corresponding first source area 402, first drain region 401 and first channel body 403 between first source area 402 and first drain region 401.
Like Figure 11 a and Figure 11 b, use mask layer 400 to cover in first source area 402 and first drain region 401; The downward etching oxygen buried layer 110 in silicon 10 tops on insulator then; First channel body 403 plays the mask effect jointly with mask layer 400; After the oxygen buried layer 110 of other parts is etched away certain thickness, will be from the side (be among Figure 11 b Y-Y ' to) expose the oxygen buried layer 110 of said first channel body 403 bottoms.In the present embodiment, the vertical thickness of said oxygen buried layer 110 is enough thick, does not expose bottom silicon 100 and can not be etched.
Like Figure 12 a and 12b, the certain thickness oxygen buried layer 110 along Y-Y ' direction side direction etching first channel body, 403 bottoms forms perforation, makes that said first channel body 403 is unsettled.In the present embodiment; The oxygen buried layer material is a silica, can adopt hydrofluoric acid to carry out wet etching, shown in Figure 12 b; Oxygen buried layer 110 thickness of first channel body, 403 bottoms are the thinnest; And be equivalent to along Y-Y ' can form perforation faster, and remainder oxygen buried layer 110 can't lose too much to etching simultaneously from both sides.
Like Figure 13 a and 13b, be mask with mask layer 400, first channel body 403 is carried out plasma doping, doping type is the P+ type.
Like Figure 14 a and 14b, first channel body 403 is carried out etching, and carry out the firm columniform source connector 404 that forms of high annealing.
Because first channel body 403 has the irregular cylinder of corner angle for the edge, in etching process, the etch rate of the edges and corners at edge is always fast than other positions; Therefore through the over etching of certain hour, it is cylindrical that first channel body will be tending towards, in the present embodiment; First channel body 403 is graphical by top layer silicon 101; Therefore material is consistent, is monocrystalline silicon or polysilicon, can adopt potassium hydroxide solution to carry out wet etching.The parameter of said high annealing can for: temperature 1000～`1200 degree centigrade, under nitrogen or hydrogen environment, high annealing 10～30 minutes.
The described plasma doping step of above-mentioned Figure 13 a also can be carried out after the described etch step of Figure 14 a, and 403 one-tenth of first etching first channel body are cylindrical, carry out plasma doping again, and annealing at last is firmly to form source connector 404.The sectional area of said cylindrical source connector 404 is little than first channel body 403, and concrete size can be selected through the time of controlling said etching.
Shown in figure 15; The surface of connector 404 forms pocket implanted layer 405 in cylindrical source; Said pocket implanted layer 405 around and the surface of the source of coating connector 404; The material of said pocket implanted layer 405 can be Si, Ge, SiGe, GaAs, InP, InAs and InGaAs, can pass through extension (EPI) or atomic deposition (ALD) and form, and carry out plasma doping and make that the doping type of pocket implanted layer 405 is opposite with source connector 404.In the present embodiment, said pocket implanted layer 405 materials are Ge, form through atomic deposition ALD, and doping type is the N+ type.
Said pocket implanted layer 405 and source connector 404 constitute cylindrical channel body, and the size of the thickness of pocket implanted layer and bonding pad, source has determined the channel body size.As preferred version, the diameter of formed channel body is not more than the thickness of top layer silicon.In the present embodiment, the preferred size range of cylindrical channel body is: section radius 5-50nm, length are 5-50nm.
Shown in figure 16, form gate dielectric layer 406 on the surface of pocket injection region 405, said gate dielectric layer 406 centers on and coats pocket implanted layer 405, and material can be silica, can form through chemical vapour deposition (CVD) CVD or atomic deposition ALD.
Shown in figure 17; Surface at gate dielectric layer 406 forms gate electrode 407; Said gate electrode 407 wrapped-gate dielectric layers 406; And fill up the remaining space between gate dielectric layer 406 bottoms and the oxygen buried layer 110, material can be polysilicon, can form through chemical vapour deposition (CVD) CVD or atomic deposition ALD.
In the present embodiment, said gate electrode 407 is wrapped-gate dielectric layer 406 not only, and forms fin type structure on oxygen buried layer 110 surfaces, so that draw interconnection line in the subsequent technique.
Like Figure 18 and shown in Figure 19; Remove mask layer 400; Respectively first source area 402 and first drain region 401 are carried out plasma doping then; Form source electrode 408 and drain 409, the doping type of said source electrode is all the P+ type mutually with source connector 404, and the doping type of said drain electrode is all the N+ type mutually with pocket implanted layer 405.
Like Figure 20, between drain electrode 409 and pocket injection region 405, source connector 404 (being channel body), form shallow doped region 410, the doping type of said shallow doped region 410 with drain identically, doping content is lower.In the present embodiment, mask capable of using oppositely injects near a side of channel body in drain electrode 409, forms the shallow doped region 410 of N-type.
Shown in figure 21, at the surface deposition dielectric spacer layer 412 of source electrode 408, drain electrode 409 and gate electrode 406, and etching formation contact hole, draw interconnection line.In the present embodiment, gate electrode 406 has formed fin type structure on oxygen buried layer 110 surfaces, therefore also is formed with insulative sidewall 411 in gate electrode 406 sides.
The foregoing description is an example with the formation technology of N type raceway groove green field effect transistor, can be applied to the manufacturing of P type raceway groove green field effect transistor equally, and is only distinct on doping type.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (15)
1. a green field effect transistor is characterized in that, comprising:
Silicon-on-insulator, said silicon-on-insulator comprise silicon base, are positioned at oxygen buried layer and top layer silicon on the silicon base successively;
Being positioned at top layer silicon isolates mutually and different source electrode, the drain electrode of doping type;
Channel body between source electrode, drain electrode, said channel body is cylindrical, and an end connects source electrode, and the other end connects drain electrode, outside the post mind-set, comprises source connector, pocket implanted layer successively; Said source connector is electrically connected with source electrode, and said pocket implanted layer is electrically connected with drain electrode, and said source electrode is identical with the doping type of source connector, and said drain electrode is identical with pocket implanted layer doping type;
Be positioned at the lip-deep grid structure of pocket implanted layer of channel body, comprise the gate electrode on gate dielectric layer and gate dielectric layer surface.
2. green field effect transistor as claimed in claim 1 is characterized in that, between drain electrode and channel body, also is formed with shallow doped region, and the doping type of said shallow doped region is identical with drain electrode, and the doping content that doping content drains is low.
3. green field effect transistor as claimed in claim 1 is characterized in that, said gate dielectric layer is around cylindrical channel body, and the surface of coating pocket implanted layer; Said gate electrode covering gate dielectric layer surface.
4. green field effect transistor as claimed in claim 1 is characterized in that, said channel body section radius scope is that 5-50nm, length range are 5-50nm.
5. green field effect transistor as claimed in claim 1 is characterized in that said source electrode, drain electrode and surface gate electrode are formed with dielectric spacer layer.
6. green field effect transistor as claimed in claim 1 is characterized in that, the material of said pocket implanted layer is Si, Ge, SiGe, GaAs, InP, InAs or InGaAs.
7. the manufacturing approach of a green field effect transistor is characterized in that, comprising:
Silicon-on-insulator is provided, oxygen buried layer and top layer silicon that said silicon-on-insulator comprises silicon base and is positioned at silicon base successively, graphical said top layer silicon forms first source area, first drain region and first channel body;
The said oxygen buried layer of etching makes the channel body bottom of winning unsettled;
First channel body that plasma doping and etching are unsettled forms cylindrical source connector;
The surface of connector forms the pocket implanted layer in said cylindrical source, and said pocket implanted layer doping type is opposite with the source connector;
Surface at the pocket implanted layer forms gate dielectric layer and gate electrode successively;
Said first source area of plasma doping and first drain region form source electrode, drain electrode respectively, and said source electrode is identical with the doping type of source connector, and said drain electrode is identical with pocket implanted layer doping type.
8. the manufacturing approach of green field effect transistor as claimed in claim 7 is characterized in that, the said oxygen buried layer of said etching makes the channel body bottom of winning unsettled, specifically comprises:
The downward etching oxygen buried layer in silicon top on insulator exposes the oxygen buried layer of said first channel body bottom;
The oxygen buried layer of side direction etching first channel body bottom makes the channel body of winning unsettled.
9. the manufacturing approach of green field effect transistor as claimed in claim 8; It is characterized in that; Said on insulator the downward etching oxygen buried layer in silicon top adopt the RIE plasma etching industrial, the oxygen buried layer of said side direction etching first channel body bottom predetermined thickness adopts wet-etching technology.
10. the manufacturing approach of green field effect transistor as claimed in claim 7; It is characterized in that; First channel body that said plasma doping and etching are unsettled forms cylindrical source connector, specifically comprises: first channel body is carried out over etching; And then it is firm to carry out high annealing, and said plasma doping carries out before etching or after the etching.
11. the manufacturing approach of green field effect transistor as claimed in claim 7 is characterized in that, said pocket implanted layer forms through extension EPI or atomic deposition ALD, around and the surface of the source of coating connector.
12. the manufacturing approach of green field effect transistor as claimed in claim 7 is characterized in that, said gate dielectric layer and gate electrode can form through chemical vapour deposition (CVD) CVD or atomic deposition ALD.
13. the manufacturing approach of green field effect transistor as claimed in claim 7; It is characterized in that; Said gate dielectric layer centers on and coats the surface of pocket implanted layer, the surface of said gate electrode wrapped-gate dielectric layer, and fill up the remaining space between gate dielectric layer bottom and the oxygen buried layer.
14. the manufacturing approach of green field effect transistor as claimed in claim 7 is characterized in that, also comprises: between drain electrode and pocket implanted layer, source connector, form shallow doped region, the doping type of said shallow doped region with drain identically, doping content is lower.
15. the manufacturing approach of green field effect transistor as claimed in claim 7 is characterized in that, also comprises: at source electrode, drain electrode and surface gate electrode deposition dielectric spacer layer, and etching formation contact hole, draw interconnection line.
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| CN102956486B (en) * | 2011-08-23 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and preparation method thereof |
| CN103474459B (en) * | 2013-09-06 | 2016-01-27 | 北京大学深圳研究生院 | Tunneling field-effect transistor |
| CN104730111A (en) * | 2015-03-27 | 2015-06-24 | 中国科学院上海微系统与信息技术研究所 | Metal-oxide-semiconductor field effect transistor (MOSFET) biosensor based on Si/SiGe/Si quantum well, and preparation method of biosensor |
| CN105390446B (en) * | 2015-11-26 | 2018-10-16 | 上海集成电路研发中心有限公司 | A kind of preparation method of three dimensional CMOS integrated circuits |
| CN105355660B (en) * | 2015-12-11 | 2019-04-23 | 上海集成电路研发中心有限公司 | A kind of tunneling field-effect transistor and its manufacturing method |
| CN108231594B (en) * | 2017-12-21 | 2020-10-02 | 上海集成电路研发中心有限公司 | Manufacturing method of FinFET device |
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