CN107808904B - Double-bracket-shaped grid-control bidirectional switch tunneling transistor and manufacturing method thereof - Google Patents
Double-bracket-shaped grid-control bidirectional switch tunneling transistor and manufacturing method thereof Download PDFInfo
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- 230000005641 tunneling Effects 0.000 title claims abstract description 48
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 28
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- 239000012535 impurity Substances 0.000 claims abstract description 153
- 230000005669 field effect Effects 0.000 claims abstract description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 54
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
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- 238000007254 oxidation reaction Methods 0.000 claims description 6
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- 230000000694 effects Effects 0.000 abstract description 11
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The device has the structural characteristics of a bracket grid and bilateral symmetry, has stronger grid control capability, and can control a second impurity heavy doping source-drain interchangeable area to be used as a source area or a drain area by adjusting the voltage of a source-drain interchangeable electrode so as to change the tunneling current direction. The invention has the advantages of low static power consumption, reverse leakage current, strong grid control capability, low subthreshold swing and capability of realizing the function of bidirectional switch. Compared with the common Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), the device realizes more excellent switching characteristic by utilizing the tunneling effect; compared with the common tunneling field effect transistor, the bidirectional symmetrical switch has the bidirectional symmetrical switch characteristic that the common tunneling field effect transistor does not have source and drain interchangeable, so that the bidirectional symmetrical switch is suitable for popularization and application.
Description
Technical Field
The invention relates to the field of manufacturing of ultra-large scale integrated circuits, in particular to a double-bracket-shaped grid-control bidirectional switch tunneling transistor with low leakage current and suitable for manufacturing low-power-consumption integrated circuits and a manufacturing method thereof.
Background
The basic unit MOSFETs of integrated circuits are becoming smaller and smaller in size according to moore's law, and not only are difficulties in manufacturing process deepened, but various adverse effects are becoming more and more prominent. The mosfet devices used in integrated circuit designs today cannot have a subthreshold swing below 60mV/dec due to the physical limitations of their own current generation during operation. When the common tunneling field effect transistor is used as a switch-type device, the tunneling effect of current carriers between semiconductor energy bands is used as a conduction mechanism of current, and the subthreshold swing is obviously superior to the 60mv/dec limit of an MOSFET device. However, the source region and the drain region of the ordinary tunneling field effect transistor adopt impurities with different conductivity types, and the asymmetric structural characteristics cause that the ordinary tunneling field effect transistor cannot completely replace the MOSFETs devices with symmetric structural characteristics in function. Taking the N-type tunneling field effect transistor as an example, if the source and the drain are interchanged, that is, the drain is at a low potential and the source is at a high potential, the tunneling field effect transistor will be always in a conducting state, and the magnitude of the conducting current can no longer be well controlled and adjusted depending on the gate electrode, which makes the switching characteristic of the whole tunneling field effect transistor invalid.
Disclosure of Invention
The purpose of the invention is as follows:
in order to effectively combine and utilize the advantages of source electrode and drain electrode interchangeability of the MOSFETs and low subthreshold swing amplitude of the common tunneling field effect transistor and solve the defects that the subthreshold swing amplitude of the MOSFETs cannot be reduced and the common tunneling field effect transistor can only be used as a one-way switch, the invention provides a double-bracket-shaped grid-control two-way switch tunneling transistor and a manufacturing method thereof. The transistor has the advantage that the logic function is completely compatible with the current integrated circuit based on the MOSFETs, the source-drain two-end structure symmetry enables the transistor to realize the function of source-drain bidirectional symmetrical switch through voltage interchange of the source electrode and the drain electrode, namely the transistor has the bidirectional switch characteristic that the source-drain electrode is interchangeable, and also has the working characteristics of high forward-reverse current ratio, low subthreshold swing, high forward-direction conducting current and the like.
The technical scheme is as follows:
the invention is realized by the following technical scheme:
a double-bracket-shaped grid-control bidirectional switch tunneling transistor comprises a silicon substrate of an SOI wafer, and is characterized in that: a substrate insulating layer of the SOI wafer is arranged above a silicon substrate of the SOI wafer, and partial regions of a monocrystalline silicon thin film, a first type impurity heavily doped region, a source-drain interchangeable intrinsic region a, a source-drain interchangeable intrinsic region b, a second type impurity heavily doped source-drain interchangeable region a, a second type impurity heavily doped source-drain interchangeable region b, a gate electrode insulating layer, a bracket gate electrode and an insulating medium barrier layer are arranged above the substrate insulating layer of the SOI wafer; the SOI wafer comprises a substrate, a first type impurity heavily doped region, a second type impurity heavily doped source-drain interchangeable region a, a second type impurity heavily doped source-drain interchangeable region b, a second type impurity source-drain interchangeable region a, a second type impurity source-drain interchangeable region b and a SOI wafer, wherein the first type impurity heavily doped region is positioned in the middle of a monocrystalline silicon film; the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b are respectively positioned in outer side regions which are positioned at the left side and the right side of the monocrystalline silicon film and are not subjected to intentional doping process, and three-surface wrapping is respectively formed on the front side, the rear side and the outer side of the second type impurity heavily doped source-drain interchangeable region a and the second type impurity heavily doped source-drain interchangeable region b;
the gate electrode insulating layer is made of an insulator material, surrounds the monocrystalline silicon film in a rectangular shape, is in mutual contact with the monocrystalline silicon film and the outer side wall of the first-class impurity heavily doped region, the outer side surfaces of the middle regions of the gate electrode insulating layer on the front side and the rear side are in mutual contact with the insulating medium blocking layer, and the rest parts of the outer side surfaces of the gate electrode insulating layer are in mutual contact with the gate electrode;
the gate electrode is made of a metal material or a polycrystalline silicon material and is in mutual contact with the left side part and the right side part of the front side surface and the back side surface of the gate electrode insulating layer and the left side surface and the right side surface, namely the gate electrode is in mutual contact with the parts of the peripheral outer side surfaces of the gate electrode insulating layer except the outer side surfaces which are positioned in the middle areas of the front side surface and the back side surface and are in mutual contact with the insulating medium barrier layer, the gate electrode forms a pair of double bracket shapes when viewed from top, and three-; the gate electrode insulating layer forms an insulating barrier between the gate electrode and the monocrystalline silicon thin film; the gate electrode only has obvious field effect control action on the source-drain interchangeable intrinsic region a and the source-drain interchangeable intrinsic region b, and has no obvious control action on other regions of the monocrystalline silicon film and the first-class impurity heavily doped region positioned in the central part of the monocrystalline silicon film; the monocrystalline silicon thin film, the first type impurity heavily doped region, the source-drain interchangeable intrinsic region a, the source-drain interchangeable intrinsic region b, the second type impurity heavily doped source-drain interchangeable region a and the second type impurity heavily doped source-drain interchangeable region b are spliced together to form a rectangular structure; the upper surfaces of a monocrystalline silicon thin film, a first impurity heavily doped region, a source-drain interchangeable intrinsic region a, a source-drain interchangeable intrinsic region b, a gate electrode insulating layer, a bracket gate electrode and a part of insulating medium barrier layer on a substrate insulating layer are the rest parts of the insulating medium barrier layer, and the source-drain interchangeable electrode a is positioned above the second impurity heavily doped source-drain interchangeable region a and forms good ohmic contact with the second impurity heavily doped source-drain interchangeable region a; the source-drain interchangeable electrode b is positioned above the second type impurity heavily-doped source-drain interchangeable region b and forms good ohmic contact with the second type impurity heavily-doped source-drain interchangeable region b; the outer side surfaces of the source-drain interchangeable electrode a and the source-drain interchangeable electrode b are respectively contacted with the insulating medium barrier layer and are insulated from each other through the blocking effect of the insulating medium barrier layer; the parts of the whole transistor structure, which are positioned at the two sides of the first-class impurity heavily-doped region, are in symmetrical structures, so that the same output characteristic can be realized under the condition that the source-drain interchangeable electrode a and the source-drain interchangeable electrode b are symmetrically interchanged.
A manufacturing method of the double-bracket-shaped grid-control bidirectional switch tunneling transistor is characterized in that:
the manufacturing steps are as follows:
the method comprises the following steps: providing an SOI wafer, wherein the lowest part of the SOI wafer is a silicon substrate of the SOI wafer, a substrate insulating layer is arranged on the silicon substrate, a monocrystalline silicon film is arranged on the upper surface of the substrate insulating layer, and the middle region of the monocrystalline silicon film on the SOI wafer is doped through an ion implantation or diffusion process to preliminarily form a first-class impurity heavily doped region;
step two: removing part of the monocrystalline silicon thin film and the first-class impurity heavily-doped region through photoetching and etching processes, and further forming the monocrystalline silicon thin film and the first-class impurity heavily-doped region on the SOI wafer;
step three: forming a gate electrode insulating layer on the outer sides of the monocrystalline silicon thin film and the first impurity heavily doped region through oxidation or deposition and etching processes;
step four: depositing an insulating medium above the structure formed in the third step by a deposition process, and after the surface is flattened, only reserving the insulating medium outside the middle parts of the front side and the rear side of the gate electrode insulating layer by an etching process to preliminarily form an insulating medium barrier layer;
step five: depositing metal or polysilicon on the upper surface of the residual substrate insulating layer and clinging to the gate electrode insulating layer by a deposition process, and flattening the surface to form a gate electrode;
step six: doping the middle regions of the monocrystalline silicon thin films on the left side and the right side through an ion implantation process to form a second type impurity heavily doped source-drain interchangeable region a and a second type impurity heavily doped source-drain interchangeable region b;
step seven: forming an insulating medium on the upper surface of the structure formed in the sixth step through an oxidation or deposition process, flattening the surface, then etching the upper parts of the second type impurity heavily doped source-drain interchangeable region a and the second type impurity heavily doped source-drain interchangeable region b through photoetching and etching processes, forming a through hole, exposing the upper surfaces of the second type impurity heavily doped source-drain interchangeable region a and the second type impurity heavily doped source-drain interchangeable region b to finally form the rest part of the insulating medium barrier layer, then injecting metal into the formed through hole until the through hole is completely filled, and forming a source-drain interchangeable electrode a and a source-drain interchangeable electrode b after flattening the surface
The advantages and effects are as follows:
the invention has the following advantages and beneficial effects:
1. source-drain symmetric interchangeable bidirectional switch characteristics:
the device is a double-bracket-shaped grid-control bidirectional switch tunneling transistor, mutually independent tunneling structures are respectively arranged on the parts, close to two sides of a gate electrode insulating layer 7, of a monocrystalline silicon film 1, tunneling is simultaneously generated near the surface, in contact with the gate electrode insulating layer 7, of the upper parts of two sides of the monocrystalline silicon film 1 under the control action of a gate electrode 8 due to the fact that the device has a bilateral symmetry structure, and the second type impurity heavily doped source-drain interchangeable area a 5 and the second type impurity heavily doped source-drain interchangeable area b 6 are controlled to serve as a source area or a drain area by adjusting the voltage of a source-drain interchangeable electrode a 9 and a source-drain interchangeable electrode b 10, so that the tunneling current direction can be changed, and the source-drain symmetric interchangeable bidirectional switch characteristic of.
2. Low subthreshold swing:
because the invention is based on the tunneling mechanism of the tunneling field effect transistor and adopts a symmetrical double-bracket gate structure, the bracket gate electrode positioned on one side of the source and the drain forms three-surface wrapping on the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 respectively in three directions, thereby having excellent gate electrode control capability, under the control action of the gate electrode 8, the energy band is easier to bend under the same gate voltage, obtaining larger electric field intensity, increasing tunneling efficiency, and obtaining lower subthreshold swing compared with an MOSFETs device and a common tunneling field effect transistor.
3. Low static power consumption, low reverse leakage current and high forward-reverse current ratio:
when a potential difference exists between the second-type impurity heavily doped source-drain interchangeable region a 5 and the second-type impurity heavily doped source-drain interchangeable region b 6, and when the gate electrode 8 is in the subthreshold or reverse bias state, since the first type impurity heavily doped region 2 has opposite impurity types with the second type impurity heavily doped source drain interchangeable region a 5 and the second type impurity heavily doped source drain interchangeable region b 6 respectively, the first-type impurity heavily doped region 2 is necessarily in a reverse bias state with one of the second-type impurity heavily doped source-drain interchangeable region a 5 or the second-type impurity heavily doped source-drain interchangeable region b 6, and a part of the monocrystalline silicon film 1 is necessarily arranged between the first-class impurity heavily-doped region 2 and the second-class impurity heavily-doped source-drain interchangeable region a 5 or the second-class impurity heavily-doped source-drain interchangeable region b 6, therefore, the device has better capability of inhibiting the remarkable increase of the tunneling current caused by the over-strong field intensity. In other words, the first type impurity heavily doped region 2 is not controlled by the gate electrode 8, and thus can effectively block the conduction of majority carriers between the second type impurity heavily doped source-drain interchangeable region a 5 or the second type impurity heavily doped source-drain interchangeable region b 6. Therefore, the invention has the advantages of low static power consumption, low reverse leakage current and high forward-reverse current ratio.
Drawings
FIG. 1 is a top view of a double-bracket gate-controlled bidirectional switch tunneling transistor according to the present invention;
FIG. 2 is a cross-sectional view of a tunneling transistor of a double-bracket-shaped gate-controlled bidirectional switch according to the present invention along the dotted line A;
FIG. 3 is a cross-sectional view of a tunneling transistor with a double-bracket-shaped gate-controlled bidirectional switch along the dotted line B according to the present invention;
FIG. 4 is a top view of step one;
FIG. 5 is a cross-sectional view along dotted line A of step one;
FIG. 6 is a cross-sectional view taken along dotted line B of step one;
FIG. 7 is a top view of step two;
FIG. 8 is a cross-sectional view taken along dotted line A in step two;
FIG. 9 is a cross-sectional view taken along the dashed line B in step two;
FIG. 10 is a top view of step three;
FIG. 11 is a cross-sectional view taken along dotted line A of step three;
FIG. 12 is a cross-sectional view taken along the dashed line B in step three;
FIG. 13 is a top view of step four;
FIG. 14 is a cross-sectional view taken along dotted line A of step four;
FIG. 15 is a cross-sectional view taken along dotted line B of step four;
FIG. 16 is a top view of step five;
FIG. 17 is a cross-sectional view taken along dotted line A of step five;
FIG. 18 is a cross-sectional view taken along dotted line B of step five;
FIG. 19 is a top view of step six;
FIG. 20 is a cross-sectional view taken along dotted line A for step six;
FIG. 21 is a cross-sectional view taken along dotted line B for step six;
FIG. 22 is a cross-sectional view taken along dotted line C for step six;
FIG. 23 is a top view of step seven;
FIG. 24 is a cross-sectional view taken along dotted line A of step seven;
fig. 25 is a cross-sectional view along the broken line B of step seven.
Description of reference numerals:
1. a single crystal silicon thin film; 2. a first type impurity heavily doped region; 3. the source and the drain can exchange an intrinsic region a; 4. the source and the drain can exchange the intrinsic region b; 5. a second type impurity heavily doped source-drain interchangeable region a; 6. a second type impurity heavily doped source-drain interchangeable region b; 7. a gate electrode insulating layer; 8. a gate electrode; 9. the source-drain interchangeable electrode a; 10. a source-drain interchangeable electrode b; 11. a substrate insulating layer; 12. a silicon substrate; 13. an insulating dielectric barrier layer.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
as shown in fig. 1, fig. 2 and fig. 3, a double-bracket-shaped gate-controlled bidirectional switch tunneling transistor comprises a silicon substrate 12 of an SOI wafer, a substrate insulating layer 11 of the SOI wafer is arranged above the silicon substrate 12 of the SOI wafer, and a monocrystalline silicon thin film 1, a first-type impurity heavily doped region 2, a source-drain interchangeable intrinsic region a3, a source-drain intrinsic interchangeable region b4, a second-type impurity heavily doped source-drain interchangeable region a 5, a second-type impurity heavily doped source-drain interchangeable region b 6, a gate electrode insulating layer 7, a bracket gate electrode 8 and a partial region of an insulating medium barrier layer 13 are arranged above the substrate insulating layer 11 of the SOI wafer; the SOI wafer substrate comprises a substrate insulating layer 11, a first type impurity heavily doped region 2, a second type impurity heavily doped source-drain interchangeable region a 5, a second type impurity heavily doped source-drain interchangeable region b 6 and a first type impurity heavily doped source-drain interchangeable region b 6, wherein the first type impurity heavily doped region 2 is located in the middle of the monocrystalline silicon film 1, the second type impurity heavily doped source-drain interchangeable region a 5 and the second type impurity heavily doped source-drain interchangeable region b 6 are located in the middle of the monocrystalline;
the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 are respectively positioned in outer side regions which are not subjected to intentional doping process and are positioned at the left side and the right side of the monocrystalline silicon film, and three surfaces of the second type impurity heavily doped source-drain interchangeable region a 5 and the second type impurity heavily doped source-drain interchangeable region b 6 are respectively wrapped at the front side, the rear side and the outer side;
the gate electrode insulating layer 7 is made of an insulator material, surrounds the monocrystalline silicon film 1 in a rectangular shape, is in contact with the monocrystalline silicon film 1 and the outer side wall of the first impurity heavily doped region 2, the outer side surfaces of the middle regions of the gate electrode insulating layer 7 on the front side and the rear side are in contact with the insulating medium blocking layer 13, and the rest parts of the outer side surfaces of the gate electrode insulating layer 7 are in contact with the gate electrode 8; the gate electrode 8 is made of a metal material or a polycrystalline silicon material, and is in contact with the left and right side portions and the left and right side surfaces of the front and back side surfaces of the gate electrode insulating layer 7, that is, the gate electrode 8 is in contact with the portions of the peripheral outer side surfaces of the gate electrode insulating layer 7 except for the outer side surfaces, which are located in the middle areas of the front and back side surfaces and are in contact with the insulating medium barrier layer 13, the gate electrode 8 forms a pair of double brackets shape when viewed from top, and forms three-side wrapping for the left and right ends of the; the gate electrode insulating layer 7 forms an insulating barrier between the gate electrode 8 and the single crystal silicon thin film 1; the gate electrode 8 only has obvious field effect control action on the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4, but has no obvious control action on other regions of the monocrystalline silicon film 1 and the first impurity heavily doped region 2 positioned in the central part of the monocrystalline silicon film 1; the monocrystalline silicon thin film 1, the first type impurity heavily doped region 2, the source-drain interchangeable intrinsic region a3, the source-drain interchangeable intrinsic region b4, the second type impurity heavily doped source-drain interchangeable region a 5 and the second type impurity heavily doped source-drain interchangeable region b 6 are spliced together to form a rectangular structure; the upper surfaces of a monocrystalline silicon thin film 1, a first impurity heavily doped region 2, a source-drain interchangeable intrinsic region a3, a source-drain interchangeable intrinsic region b4, a gate electrode insulating layer 7, a bracket gate electrode 8 and a part of insulating medium barrier layer 13 on a substrate insulating layer 11 are the rest parts of the insulating medium barrier layer 13, and a source-drain interchangeable electrode a 9 is positioned above a second impurity heavily doped source-drain interchangeable region a 5 and forms good ohmic contact with the second impurity heavily doped source-drain interchangeable region a 5; the source-drain interchangeable electrode b 10 is positioned above the second impurity heavily doped source-drain interchangeable region b 6 and forms good ohmic contact with the second impurity heavily doped source-drain interchangeable region b; the outer side surfaces of the source-drain interchangeable electrode a 9 and the source-drain interchangeable electrode b 10 are respectively in contact with the insulating dielectric barrier layer 13 and are insulated from each other by the blocking action of the insulating dielectric barrier layer 13. The parts of the whole transistor structure, which are positioned at the two sides of the first-class impurity heavily-doped region 2, are in symmetrical structures, so that the same output characteristics can be realized under the condition that the source-drain interchangeable electrode a 9 and the source-drain interchangeable electrode b 10 are symmetrically interchanged.
The invention provides a double-bracket-shaped grid-control bidirectional switch tunneling transistor which has the structural characteristic of bilateral symmetry, a second-type impurity heavily-doped source-drain interchangeable region a 5 and a second-type impurity heavily-doped source-drain interchangeable region b 6 are controlled to be used as a source region or a drain region by adjusting the voltage of a source-drain interchangeable electrode a 9 and a source-drain interchangeable electrode b 10, the tunneling current direction is changed, and the source-drain symmetric interchangeable characteristic of bidirectional tunneling conduction of a device is realized.
Taking the first-type impurity heavily doped region 2 as an N-type impurity as an example, when a potential difference exists between the second-type impurity heavily doped source-drain interchangeable region a 5 and the second-type impurity heavily doped source-drain interchangeable region b 6, and when the gate electrode 8 is in a negative-pressure reverse bias state and is influenced by the effect of the gate electrode field effect, the second-type impurity heavily doped source-drain interchangeable region a 5 provides holes to the source-drain interchangeable intrinsic region a3, and the second-type impurity heavily doped source-drain interchangeable region b 6 provides holes to the source-drain interchangeable intrinsic region b4, so that hole accumulation is generated in both the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4, so that both the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 show a P-type states, and the accumulated holes cause resistance values of the source-drain interchangeable region a3 and the source-drain interchangeable intrinsic region b4 to decrease under the effect of the gate electrode 8 (i, The drain regions are all in a low resistance state), but at this time, a source-drain interchangeable intrinsic region a3 showing a P-type characteristic and the first-type impurity heavily doped region 2 which is N-type at this time form a reverse-biased PN junction structure under drain-source voltage, and because the first-type impurity heavily doped region 2 is not controlled by the gate electrode 8, the conduction type of the transistor cannot be changed due to the change of the voltage of the gate electrode 8, so that the whole transistor is in a high resistance blocking state due to the existence of the reverse-biased PN junction structure under the reverse-biased state of the transistor; along with the gradual rise of the applied voltage of the gate electrode 8 from the negative voltage to the vicinity of the flat band voltage, the second-type impurity heavily-doped source-drain interchangeable region a 5 does not provide a large number of holes for the source-drain interchangeable intrinsic region a3, the second-type impurity heavily-doped source-drain interchangeable region b 6 does not provide a large number of holes for the source-drain interchangeable intrinsic region b4, and simultaneously, because the field strength in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 is low and the band bending degree is small, a large number of electron-hole pairs are not generated between the conduction band and the valence band of the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4, so that a large number of holes and a large number of electrons are not accumulated in the tunneling source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4, and the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 of the transistor are both in a high resistance State), so that no significant current flows through the entire transistor, the device now has excellent turn-off and subthreshold characteristics; with the further increase of the applied voltage from the flat band voltage to the forward bias state of the gate electrode 8, at this time, the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4 are influenced by the field effect of the gate electrode 8, and a large electric field intensity and a strong energy band bending occur, so that an obvious tunnel effect occurs, and a large number of electron-hole pairs are formed in the source-drain interchangeable intrinsic region a3 and the source-drain interchangeable intrinsic region b4, wherein holes generated by the source-drain interchangeable intrinsic region at one end of the source region are discharged through the second impurity heavily doped source-drain interchangeable region at the end, and generated electrons flow to the source-drain interchangeable intrinsic region at one end of the drain region through the first impurity heavily doped region 2 and are recombined with valence band holes generated by the tunnel effect in the source-drain interchangeable intrinsic region at one end of the drain region. Conduction band electrons generated by the tunneling effect in the source-drain interchangeable intrinsic region serving as one end of the drain region are recombined with valence band holes of the second impurity heavily doped source-drain interchangeable region serving as the drain region, and continuous conduction current is formed through the physical process. The concentration of electron-hole pairs generated by the tunneling effect gradually increases with the increase in the voltage applied to the gate electrode 8, and when the concentration of electron-hole pairs generated by the tunneling effect increases to a certain degree, the transistor transits from the subthreshold state to the forward conduction state.
In order to achieve the device function, the invention provides a double-bracket-shaped grid-control bidirectional switch tunneling transistor, which is characterized in that:
in order to achieve the device function, the invention provides a double-bracket-shaped grid-control bidirectional switch tunneling transistor, which is characterized in that:
the device is a double-bracket-shaped grid-control bidirectional switch tunneling transistor, and the structure of a double-bracket grid electrode is that when a grid electrode 8 is in a forward bias state, compared with a plane structure, the electric field intensity near the corner area of the grid electrode is enhanced, so that the probability of generating carriers is increased under the same grid voltage, the subthreshold swing amplitude is reduced, and the forward conduction current is increased; the device is a double-bracket-shaped grid-control bidirectional switch tunneling transistor, and two sides of a first impurity heavily doped region 2 and an insulating medium barrier layer 13 part above the first impurity heavily doped region are of symmetrical structures. The first-class impurity heavily doped region 2 and the second-class impurity heavily doped source-drain interchangeable region a 5, and the first-class impurity heavily doped region 2 and the second-class impurity heavily doped source-drain interchangeable region b 6 are respectively provided with opposite impurity types. When reverse voltage is simultaneously applied to the gate electrodes on the two sides, a large number of carriers of the same type as the majority carriers of the second type impurity heavily doped region are accumulated near the surface, which is in contact with the gate electrode insulating layer 7, on the two sides above the monocrystalline silicon film 1, the carriers of the same type as the majority carriers of the second type impurity heavily doped region flow through the source-drain interchangeable intrinsic region to reach the first type impurity heavily doped region 2 under the action of drain electrode voltage, and are recombined with the majority carriers (opposite to the conductivity type) of the first type impurity heavily doped region 2, because the first type impurity heavily doped region 2 is a high doping concentration region, the carriers of the same type as the majority carriers of the second type impurity heavily doped region from the source-drain interchangeable intrinsic region are almost completely recombined, and because the source-drain interchangeable intrinsic region on the source region side and the first type impurity heavily doped region 2 are in a reverse bias high resistance state, therefore, obvious current generation cannot be generated in the source-drain direction, the reverse leakage current of the tunneling field effect transistor is obviously reduced by the structure, and the device can obtain higher forward-reverse current ratio. Due to the symmetrical structure of the device, the second type impurity heavily doped source-drain interchangeable region a 5 and the second type impurity heavily doped source-drain interchangeable region b 6 are switched to be used as a source region or a drain region by controlling the source-drain interchangeable electrode a 9 and the source-drain interchangeable electrode b 10, so that the output characteristic of the device is not influenced, and the source-drain interchangeable bidirectional switch characteristic like an MOSFET device can be realized. The gate electrode insulating layer 7 is an insulating material layer for generating a tunneling current.
The specific manufacturing process steps of the unit of the double-bracket-shaped grid-control bidirectional switch tunneling transistor on the SOI wafer are as follows:
the method comprises the following steps: as shown in fig. 4, 5 and 6, providing an SOI wafer, wherein a silicon substrate 12 of the SOI wafer is provided at the lowest part, a substrate insulating layer 11 is provided on the silicon substrate, a monocrystalline silicon thin film 1 is provided on the upper surface of the substrate insulating layer 11, and a middle region of the monocrystalline silicon thin film 1 above the SOI wafer is doped by an ion implantation or diffusion process to preliminarily form a first-type impurity heavily doped region 2;
step two: as shown in fig. 7, 8 and 9, removing a part of the monocrystalline silicon thin film 1 and the first-type impurity heavily doped region 2 by photolithography and etching processes, and further forming the monocrystalline silicon thin film 1 and the first-type impurity heavily doped region 2 on the SOI wafer;
step three: as shown in fig. 10, 11 and 12, a gate electrode insulating layer 7 is formed outside the single crystal silicon thin film 1 and the first type impurity heavily doped region 2 by oxidation or deposition, etching process;
step four: as shown in fig. 13, 14 and 15, an insulating medium is deposited above the structure formed in step three by a deposition process, and after the surface is planarized, only the insulating medium outside the middle portions of the front and rear sides of the gate electrode insulating layer 7 is remained by an etching process, and an insulating medium blocking layer 13 is preliminarily formed;
step five: as shown in fig. 16, 17 and 18, a gate electrode 8 is formed by depositing metal or polysilicon on the upper surface of the remaining substrate insulating layer 11 by a deposition process, and then planarizing the surface;
step six: as shown in fig. 19, 20, 21 and 22, the middle regions of the single crystal silicon thin films 1 on the left and right sides are doped by an ion implantation process to form a second impurity heavily doped source-drain interchangeable region a 5 and a second impurity heavily doped source-drain interchangeable region a 6;
step seven: as shown in fig. 23, 24 and 25, an insulating medium is formed on the upper surface of the structure formed in the sixth step through an oxidation or deposition process, the surfaces are planarized, and then photolithography and etching processes are performed to etch the upper portions of the second-type impurity heavily doped source-drain interchangeable region a 5 and the second-type impurity heavily doped source-drain interchangeable region b 6, and a through hole is formed, the upper surfaces of the second-type impurity heavily doped source-drain interchangeable region a 5 and the second-type impurity heavily doped source-drain interchangeable region b 6 are exposed to finally form the rest of the insulating medium barrier layer 13, metal is then injected into the formed through hole until the through hole is completely filled, and a source-drain interchangeable electrode a 9 and a source-drain interchangeable electrode b 10 are formed after the surfaces are planarized.
Claims (2)
1. A double-bracketed gated bidirectional switched tunneling transistor comprising a silicon substrate (12) of an SOI wafer, characterized in that: a substrate insulating layer (11) of the SOI wafer is arranged above a silicon substrate (12) of the SOI wafer, and partial regions of a monocrystalline silicon film (1), a first impurity heavily doped region (2), a source-drain interchangeable intrinsic region a (3), a source-drain interchangeable intrinsic region b (4), a second impurity heavily doped source-drain interchangeable region a (5), a second impurity heavily doped source-drain interchangeable region b (6), a gate electrode insulating layer (7), a bracket gate electrode (8) and an insulating medium barrier layer (13) are arranged above the substrate insulating layer (11) of the SOI wafer;
the SOI wafer substrate comprises a substrate insulating layer (11) and a first type impurity heavily doped region (2), a second type impurity heavily doped source-drain interchangeable region a (5) and a second type impurity heavily doped source-drain interchangeable region b (6), wherein the first type impurity heavily doped region (2) is positioned in the middle of the monocrystalline silicon film (1), the second type impurity heavily doped source-drain interchangeable region a (5) and the second type impurity heavily doped source-drain interchangeable region b (6) are respectively positioned in the central parts of the monocrystalline silicon films (1) on two sides of the first type impurity heavily doped region (2), and the bottom surfaces of the second type impurity heavily doped source-drain interchangeable region a (5) and the second type impurity heavily;
the source-drain interchangeable intrinsic region a (3) and the source-drain interchangeable intrinsic region b (4) are respectively positioned in the outer side regions which are not subjected to the intentional doping process at the left side and the right side of the monocrystalline silicon film (1), and three surfaces of the front side, the back side and the outer side of the second type impurity heavily doped source-drain interchangeable region a (5) and the second type impurity heavily doped source-drain interchangeable region b (6) are respectively wrapped;
the gate electrode insulating layer (7) is made of an insulator material, surrounds the monocrystalline silicon thin film (1) in a rectangular shape, is in mutual contact with the monocrystalline silicon thin film (1) and the outer side wall of the first impurity heavily doped region (2), the outer side surfaces of the middle regions of the front side and the rear side of the gate electrode insulating layer (7) are in mutual contact with the insulating medium blocking layer (13), and the rest parts of the outer side surfaces of the gate electrode insulating layer (7) are in mutual contact with the gate electrode (8);
the gate electrode (8) is made of a metal material or a polycrystalline silicon material and is in mutual contact with the left side part and the right side part of the front side surface and the back side surface of the gate electrode insulating layer (7) and the left side surface and the right side surface, namely the gate electrode (8) is in mutual contact with the outer side surface of the peripheral outer side surface of the gate electrode insulating layer (7) except the outer side surface which is positioned in the middle area of the front side surface and the back side surface and is in mutual contact with the insulating medium barrier layer (13), the gate electrode (8) forms a pair of double bracket shapes when viewed from top, and three sides of the left; the gate electrode insulating layer (7) forms an insulating barrier between the gate electrode (8) and the single crystal silicon thin film (1); the gate electrode (8) only has obvious field effect control action on the source-drain interchangeable intrinsic region a (3) and the source-drain interchangeable intrinsic region b (4), and has no obvious control action on other regions of the monocrystalline silicon film (1) and the first impurity heavily doped region (2) positioned in the central part of the monocrystalline silicon film (1); the structure comprises a monocrystalline silicon thin film (1), a first type impurity heavily doped region (2), a source-drain interchangeable intrinsic region a (3), a source-drain interchangeable intrinsic region b (4), a second type impurity heavily doped source-drain interchangeable region a (5) and a second type impurity heavily doped source-drain interchangeable region b (6) which are spliced together to form a rectangular structure; the upper surfaces of a part of insulating medium barrier layers (13) on a monocrystalline silicon thin film (1), a first type impurity heavily doped region (2), a source-drain interchangeable intrinsic region a (3), a source-drain interchangeable intrinsic region b (4), a gate electrode insulating layer (7), a bracket gate electrode (8) and a substrate insulating layer (11) are the rest parts of the insulating medium barrier layers (13), and a source-drain interchangeable electrode a (9) is positioned above a second type impurity heavily doped source-drain interchangeable region a (5) and forms good ohmic contact with the second type impurity heavily doped source-drain interchangeable region a (5); the source-drain interchangeable electrode b (10) is positioned above the second type impurity heavily-doped source-drain interchangeable region b (6) and forms good ohmic contact with the second type impurity heavily-doped source-drain interchangeable region b; the outer side surfaces of the source-drain interchangeable electrode a (9) and the source-drain interchangeable electrode b (10) are respectively contacted with an insulating medium barrier layer (13) and are insulated from each other through the blocking action of the insulating medium barrier layer (13); the parts of the whole transistor structure, which are positioned at the two sides of the first-class impurity heavily-doped region (2), are in symmetrical structures, and the same output characteristics can be realized under the condition that the source-drain interchangeable electrode a (9) and the source-drain interchangeable electrode b (10) are symmetrically interchanged.
2. A method of manufacturing a double-bracket gate-controlled bidirectional switching tunneling transistor according to claim 1, wherein:
the manufacturing steps are as follows:
the method comprises the following steps: providing an SOI wafer, wherein the silicon substrate (12) of the SOI wafer is arranged at the lowest part, a substrate insulating layer (11) is arranged on the silicon substrate, the upper surface of the substrate insulating layer (11) is a monocrystalline silicon thin film (1), and the middle region of the monocrystalline silicon thin film (1) above the SOI wafer is doped through an ion implantation or diffusion process to preliminarily form a first impurity heavily doped region (2);
step two: removing part of the monocrystalline silicon thin film (1) and the first type impurity heavily doped region (2) through photoetching and etching processes, and further forming the monocrystalline silicon thin film (1) and the first type impurity heavily doped region (2) on the SOI wafer;
step three: forming a gate electrode insulating layer (7) on the outer sides of the monocrystalline silicon thin film (1) and the first impurity heavily doped region (2) through oxidation or deposition and etching processes;
step four: depositing an insulating medium above the structure formed in the third step by a deposition process, and after the surface is flattened, only reserving the insulating medium outside the middle parts of the front side and the rear side of the gate electrode insulating layer (7) by an etching process to preliminarily form an insulating medium barrier layer (13);
step five: through a deposition process, clinging to the gate electrode insulating layer (7) on the upper surface of the residual substrate insulating layer (11), depositing metal or polysilicon, and forming a gate electrode (8) after flattening the surface;
step six: doping the middle regions of the monocrystalline silicon thin films (1) on the left side and the right side through an ion implantation process to form a second type impurity heavily doped source-drain interchangeable region a (5) and a second type impurity heavily doped source-drain interchangeable region b (6);
step seven: and forming an insulating medium on the upper surface of the structure formed in the sixth step through an oxidation or deposition process, etching the upper parts of the second-class impurity heavily-doped source-drain interchangeable region a (5) and the second-class impurity heavily-doped source-drain interchangeable region b (6) through a photoetching and etching process after the surface is flattened, forming a through hole, exposing the upper surfaces of the second-class impurity heavily-doped source-drain interchangeable region a (5) and the second-class impurity heavily-doped source-drain interchangeable region b (6) to finally form the rest part of the insulating medium barrier layer (13), injecting metal into the formed through hole until the through hole is completely filled, and forming a source-drain interchangeable electrode a (9) and a source-drain interchangeable electrode b (10) after the surface is flattened.
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