CN113764531B - Source-drain auxiliary programmable single-gate Schottky barrier transistor and manufacturing method thereof - Google Patents
Source-drain auxiliary programmable single-gate Schottky barrier transistor and manufacturing method thereof Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000005641 tunneling Effects 0.000 claims abstract description 81
- 238000007667 floating Methods 0.000 claims abstract description 68
- 230000002146 bilateral effect Effects 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 42
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 42
- 230000036961 partial effect Effects 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 28
- 239000010408 film Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 25
- 229910045601 alloy Inorganic materials 0.000 claims description 23
- 239000000956 alloy Substances 0.000 claims description 23
- 238000005137 deposition process Methods 0.000 claims description 23
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 230000002829 reductive effect Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000005685 electric field effect Effects 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 230000002457 bidirectional effect Effects 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
Compared with the prior art, the source-drain auxiliary programmable single-gate Schottky barrier transistor has the advantages that the switching control function can be realized only through a single gate electrode, the complexity of a unit structure is simplified, and the interconnection and the integration level of the unit structure are easy to improve. The source-drain auxiliary programmable single-gate Schottky barrier transistor has the structural characteristics of bilateral symmetry in the area below the programming tunneling layer, and the interchangeable electrode a and the interchangeable electrode b can be interchanged with each other, so that the bidirectional switch transmission function is realized. The programmable floating gate of the source-drain auxiliary programmable single-gate Schottky barrier transistor provided by the invention is programmed by applying potential difference between the drain electrode and the source electrode, and the conductivity type can still be recorded and kept for a long time under power failure.
Description
Technical Field
The invention relates to the field of ultra-large scale integrated circuit manufacturing, in particular to a source-drain auxiliary programmable single gate Schottky barrier transistor suitable for manufacturing a low-power integrated circuit and a manufacturing method thereof.
Background
The tunnel transistor is compatible with the CMOS VLSI technology at present and is an alternative technology for the CMOS VLSI MOS field effect transistor due to the advantages of better subthreshold characteristic, lower power consumption and the like. To be compatible with complementary functions of P-type and N-type transistors in CMOS very large scale integrated circuit technology, tunnel transistors are also required to be fabricated with both N-type and P-type. However, both the tunnel transistor and the conventional MOS field effect transistor are realized by doping processes such as N-type impurity and P-type impurity. However, as the integration technology has entered into nanoscale nodes, in order to stabilize the working characteristics of the devices, it is generally required to lengthen the length of the source region and the drain region of the devices, and to adopt a drain light doping technology to reduce the static power consumption of the devices and solve the problems of excessive reverse leakage current, which undoubtedly increases the total size of the devices, so that the actual length of the devices is far greater than the physical gate length of the devices, and if the source region and the drain region of the P-type field effect transistor and the N-type field effect transistor are reduced to the length equivalent to the physical gate length of the P-type field effect transistor, the performance of the devices is seriously degraded or even fails, and the degradation and failure of the basic working performance of the transistors can also cause the abnormal operation or even failure of the related circuits formed by the transistors. On the other hand, the nanoscale transistor based on the doping process needs to be manufactured by forming a steep abrupt junction in an extremely short size, which requires development of a heat treatment process of millisecond level, and thus is disadvantageous in terms of control of production cost, and to solve this problem, a programmable transistor using schottky barrier, which is a field effect transistor whose conductivity type can be controlled by an auxiliary programming gate electrode, requires two external metal wirings for separately controlling the gate electrodes, respectively, the introduction of an additional separately supplied gate electrode, increases difficulty of metal interconnection, and the conductivity type of such programmable transistor cannot be preserved after power-off, and an additional nonvolatile transistor needs to be introduced in an integrated circuit to record its conductivity type, which is disadvantageous in terms of simplifying operation and increasing integration. Meanwhile, unlike a complementary CMOS field effect transistor, a programmable transistor is a field effect transistor that can realize only unidirectional switching.
Disclosure of Invention
The invention aims to provide a source-drain auxiliary programmable single-gate Schottky barrier transistor, which is more compatible with the traditional CMOS technology in order to enable the programmable transistor to simultaneously realize the characteristics of low power consumption and excellent subthreshold of a tunnel transistor; the circuit can work through only one gate electrode, and the circuit interconnection difficulty is remarkably reduced; the programming conductivity type is kept after power failure is realized; the programmable transistor is realized to have bidirectional conduction characteristics like an N-MOS transistor or a P-MOS transistor in a CMOS integrated circuit. The programmable floating gate of the source-drain auxiliary programmable single-gate Schottky barrier transistor can normally work through a single gate electrode, is programmed by applying potential difference between a drain electrode and a source electrode, can still record and keep the conductivity type under power failure, and has a bidirectional switch function.
In order to achieve the above purpose, the present invention provides the following technical solutions: the source-drain auxiliary programmable single gate Schottky barrier transistor comprises a silicon substrate of an SOI wafer and is characterized in that: the SOI wafer comprises a silicon substrate, a substrate insulating layer, a semiconductor film region, an interchangeable electrode a and an interchangeable electrode b, wherein the substrate insulating layer of the SOI wafer is arranged above the silicon substrate of the SOI wafer; the upper part and the side surface of the semiconductor film region, the upper part and the side surface of the inner part region of the interchangeable electrode a and the interchangeable electrode b are gate electrode insulating layers; the programmable floating gate, the gate electrode and the insulating medium layer are arranged above and on the side surface of the gate electrode insulating layer; the semiconductor thin film region is made of semiconductor material, and the interchangeable electrode a and the interchangeable electrode b are made of metal, alloy or metal silicide, are respectively positioned at the left side and the right side of the semiconductor thin film region, and respectively form barrier type contact with the surfaces of the left side and the right side of the semiconductor thin film region, wherein the barrier type contact is provided with a Schottky barrier; the gate electrode insulating layer is made of insulating dielectric materials; the programmable floating gate is made of metal, alloy, polysilicon or silicon nitride material, is positioned above the center of the gate electrode insulating layer and on the side surface of the center of the gate electrode insulating layer, and is insulated and isolated from the gate electrode, the interchangeable electrode a and the interchangeable electrode b through an insulating medium layer; the gate electrode is made of metal, alloy or polysilicon, is positioned on the upper surface and the side surface of the gate electrode insulating layer corresponding to the upper part and the side surface of the two sides of the semiconductor film region, and is insulated and isolated from the gate electrode, the interchangeable electrode a and the interchangeable electrode b through the insulating medium layer; the left side and the right side above the programmable floating gate are respectively contacted with the programming tunneling layer a and the programming tunneling layer b; the left side of the programming tunneling layer a is in contact with the interchangeable electrode a; the right side of the programming tunneling layer b is in contact with the interchangeable electrode b; the thickness between the left and right sides of the programming tunneling layer a is smaller than the thickness between the left and right sides of the programming tunneling layer b.
Compared with the prior art, the invention has the beneficial effects that:
1. the cell structure interconnection is simple and easy to integrate
Compared with the prior art, the source-drain auxiliary programmable single-gate Schottky barrier transistor has the advantages that the switching control function can be realized only through a single gate electrode without additional power supply, the complexity of a unit structure is simplified, and the interconnection and the integration level of the unit structure are easy to improve.
2. The bidirectional switch transmission function can be realized:
the source-drain auxiliary programmable single-gate Schottky barrier transistor has the structural characteristics of bilateral symmetry in the area below the programming tunneling layer, and the interchangeable electrode a and the interchangeable electrode b can be interchanged with each other, so that the bidirectional switch transmission function is realized.
3. Non-volatile of conductivity type after power failure:
the programmable floating gate of the source-drain auxiliary programmable single-gate Schottky barrier transistor provided by the invention is programmed by applying potential difference between the drain electrode and the source electrode, and the conductivity type after being programmed can be recorded and kept for a long time under power failure.
Drawings
Fig. 1 is a top view of a source-drain assisted programmable single gate schottky barrier transistor of the present invention;
fig. 2 is a cross-sectional view of a source-drain assisted programmable single gate schottky barrier transistor of the present invention along the dashed line a of fig. 1;
FIG. 3 is a top view of step one;
FIG. 4 is a cross-sectional view along the broken line A of step one;
FIG. 5 is a top view of step two;
FIG. 6 is a cross-sectional view along the broken line A of step two;
FIG. 7 is a cross-sectional view along the broken line B of step two;
FIG. 8 is a top view of step three;
FIG. 9 is a cross-sectional view along the broken line A of step three;
FIG. 10 is a cross-sectional view along the broken line B of step three;
FIG. 11 is a top view of step four;
FIG. 12 is a cross-sectional view along the broken line A of step four;
FIG. 13 is a top view of step five;
FIG. 14 is a cross-sectional view along the broken line A of step five;
FIG. 15 is a top view of step six;
FIG. 16 is a top view of step seven;
FIG. 17 is a cross-sectional view along the broken line A of step seven;
FIG. 18 is a cross-sectional view along the broken line B of step seven;
FIG. 19 is a cross-sectional view along the broken line C of step seven;
FIG. 20 is a cross-sectional view along the broken line D of step seven;
FIG. 21 is a cross-sectional view along the broken line E of step seven;
FIG. 22 is a top view of step eight;
FIG. 23 is a cross-sectional view along the broken line A of step eight;
FIG. 24 is a cross-sectional view along the broken line B of step eight;
FIG. 25 is a cross-sectional view along the broken line C of step eight;
fig. 26 is a sectional view along the broken line D of step eight;
FIG. 27 is a cross-sectional view along the broken line E of step eight;
FIG. 28 is a top view of step nine;
fig. 29 is a sectional view along the broken line a of step nine;
FIG. 30 is a cross-sectional view along the broken line B of step nine;
FIG. 31 is a cross-sectional view along the broken line C of step nine;
fig. 32 is a sectional view along the broken line D of step nine;
FIG. 33 is a cross-sectional view along the broken line E of step nine;
FIG. 34 is a top view of step ten;
fig. 35 is a cross-sectional view along the broken line a of step ten;
fig. 36 is a sectional view along the broken line B of step ten;
fig. 37 is a sectional view along the broken line C of step ten;
fig. 38 is a sectional view along the broken line D of step nine;
1. interchangeable electrode a; 2. interchangeable electrode b; 3. a semiconductor thin film region; 4. a gate electrode insulating layer; 5. a programmable floating gate; 6. a gate electrode; 7. programming tunneling layer a; 8. programming tunneling layer b; 9. a substrate insulating layer of the SOI wafer; 10. a silicon substrate of the SOI wafer; 11. an insulating dielectric layer.
Detailed Description
The invention is further described with reference to the accompanying drawings:
as shown in fig. 1 and 2, the present invention provides a source-drain auxiliary programmable single gate schottky barrier transistor, which comprises a silicon substrate 10 of an SOI wafer, a substrate insulating layer 9 of the SOI wafer above the silicon substrate 10 of the SOI wafer, and a semiconductor thin film region 3, an interchangeable electrode a1 and an interchangeable electrode b2 above the substrate insulating layer 9 of the SOI wafer; the upper and side surfaces of the semiconductor film region 3, the upper and side surfaces of the inner part regions of the interchangeable electrode a1 and the interchangeable electrode b2 are gate electrode insulating layers 4; the programmable floating gate 5, the gate electrode 6 and the insulating medium layer 11 are arranged above and on the side surface of the gate electrode insulating layer 4; the semiconductor film region 3 is made of semiconductor material, and the interchangeable electrode a1 and the interchangeable electrode b2 are made of metal, alloy or metal silicide, are respectively positioned at the left side and the right side of the semiconductor film region 3, and respectively form barrier type contact with the left side and the right side surfaces of the semiconductor film region 3, wherein the barrier type contact has a Schottky barrier; the gate electrode insulating layer 4 is made of insulating dielectric material; the programmable floating gate 5 is made of metal, alloy, polysilicon or silicon nitride material, is positioned above the center of the gate electrode insulating layer 4 and on the side surface, and is insulated from the gate electrode 6, the interchangeable electrode a1 and the interchangeable electrode b2 through the insulating medium layer 11; the gate electrode 6 is made of metal, alloy or polysilicon, is positioned on the upper surface and the side surface of the gate electrode insulating layer 4 corresponding to the upper part and the side surface of the two sides of the semiconductor film region 3, and is insulated and isolated from the gate electrode 5, the interchangeable electrode a1 and the interchangeable electrode b2 through the insulating medium layer 11; the left side and the right side above the programmable floating gate 5 are respectively contacted with the programming tunneling layer a7 and the programming tunneling layer b8; the left side of the programming tunneling layer a7 is in contact with the interchangeable electrode a 1; the right side of the programming tunneling layer b8 is in contact with the interchangeable electrode b2; the thickness between the left and right sides of the programming tunneling layer a7 is smaller than the thickness between the left and right sides of the programming tunneling layer b 8.
The programming tunneling layer a7 and the programming tunneling layer b8 are made of the same insulating material, and the thickness between the left side and the right side of the programming tunneling layer a7 is smaller than 4 nanometers; when a potential difference is applied between the interchangeable electrode b2 and the interchangeable electrode a1, an insulating layer tunneling effect occurs in the programming tunneling layer a7 and the programming tunneling layer b8, so that the resistance values of the programming tunneling layer a7 and the programming tunneling layer b8 are reduced, and the thickness between the left side and the right side of the programming tunneling layer a7 is smaller than that between the left side and the right side of the programming tunneling layer b8, as the potential difference is continuously increased between the interchangeable electrode b2 and the interchangeable electrode a1, the insulating layer tunneling effect occurs in the programming tunneling layer a7 before the programming tunneling layer b8, and after the insulating layer tunneling effect occurs in the programming tunneling layer a7, charges flowing into the programmable floating gate 5 from the interchangeable electrode a1 through the programming tunneling layer a7 are more than charges flowing out from the programmable floating gate 5 through the programming tunneling layer b8 and flowing into the interchangeable electrode b2, and the charge quantity in the programmable floating gate 5 is controlled through the process.
When a positive potential difference is applied between the interchangeable electrode b2 and the interchangeable electrode a1, the negative charge flowing from the interchangeable electrode a1 into the programmable floating gate 5 through the programming tunneling layer a7 can be made more than the negative charge flowing from the programmable floating gate 5 through the programming tunneling layer b8 and out to the interchangeable electrode b2, by increasing the net residual negative charge in the programmable floating gate 5 or decreasing the net residual positive charge in the programmable floating gate 5; when a negative potential difference is applied between the interchangeable electrode b2 and the interchangeable electrode a1, positive charges flowing from the interchangeable electrode a1 into the programmable floating gate 5 through the programming tunneling layer a7 can be made more positive than positive charges flowing from the programmable floating gate 5 through the programming tunneling layer b8 and out to the interchangeable electrode b2, and net positive charges in the programmable floating gate 5 are increased or net residual negative charges in the programmable floating gate 5 are reduced through the above-mentioned processes; the charge quantity in the programmable floating gate 5 and the type of the net residual charge in the programmable floating gate 5 are controlled through the process, and the conduction type nonvolatile programming operation of the source-drain auxiliary programmable single gate Schottky barrier transistor is realized.
The programmable floating gate 5 is a region which does not need to be externally connected with a metal lead and is formed by materials such as metal, alloy, polysilicon, silicon nitride and the like, the internal net residual charge type and the charge quantity of the programmable floating gate are changed by applying electric potential between the interchangeable electrode b2 and the interchangeable electrode a1, and the programming tunneling layer a7 and the programming tunneling layer b8 generate insulating layer tunneling effect; when the net residual charge in the programmable floating gate 5 is positive charge, an electric field effect is generated in the semiconductor film region 3 and positive charge 'holes' in the semiconductor film region 3 are blocked from flowing between the two sides of the interchangeable electrode a1 and the interchangeable electrode b2, and the programmable single gate Schottky barrier transistor is controlled to operate in an N-type mode by the process control source-drain auxiliary; when the net residual charge in the programmable floating gate 5 is negative, an electric field effect is generated in the semiconductor film region 3 and negative charge electrons in the semiconductor film region 3 are blocked from flowing between the two sides of the interchangeable electrode a1 and the interchangeable electrode b2, and the programmable single gate Schottky barrier transistor is assisted to work in a P type mode by the process control source and drain;
the source-drain auxiliary programmable single gate schottky barrier transistor has a bilateral symmetry structure in the area below the lower surfaces of the programming tunneling layer a7 and the programming tunneling layer b8, and the interchangeable electrode a1 and the interchangeable electrode b2 can be interchanged with each other after the programmable floating gate 5 is subjected to nonvolatile programming, namely, under the condition of determining the conductivity type, and the source-drain auxiliary programmable single gate schottky barrier transistor is a field effect transistor capable of realizing a bidirectional switching function.
The invention also provides a manufacturing method of the source-drain auxiliary programmable single gate Schottky barrier transistor, which comprises the following manufacturing steps:
step one: as shown in fig. 3 and 4, an SOI wafer is provided, a silicon substrate 10 of the SOI wafer is arranged at the bottom, a substrate insulating layer 9 of the SOI wafer is arranged on the silicon substrate, a semiconductor thin film is arranged on the upper surface of the substrate insulating layer 9 of the SOI wafer, and partial areas of the interchangeable electrode a1 and the interchangeable electrode b2 are formed preliminarily through photoetching, etching and deposition processes;
step two: as shown in fig. 5, 6 and 7, etching the upper, lower, left and right partial regions of the semiconductor film in the first step to expose the substrate insulating layer 9 of the SOI wafer by an etching process to form a semiconductor film region 3;
step three: as shown in fig. 8, 9 and 10, the gate electrode insulating layer 4 is preliminarily formed by a deposition process after forming insulating dielectric layers over and on the sides of the interchangeable electrode a1, the interchangeable electrode b2 and the semiconductor thin film region 3, and then performing planarization treatment;
step four: as shown in fig. 11 and 12, partial regions above and below the gate electrode insulating layer 4 preliminarily formed in the third step are etched away by an etching process, and the gate electrode insulating layer 4 is further formed;
step five: as shown in fig. 13 and 14, an insulating medium layer 11 is initially formed by depositing an insulating medium over the gate electrode insulating layer 4 formed in the fourth step and then performing planarization treatment until the upper surface of the gate electrode insulating layer 4 is exposed;
step six: as shown in fig. 15, by photolithography and etching processes, etching away the partial regions on both sides of the gate electrode insulating layer 4 until the substrate insulating layer 9 of the SOI wafer is exposed, etching away the regions corresponding to the left and right sides of the semiconductor thin film region 3 of the insulating dielectric layer 11 on both upper and lower sides of the electrode insulating layer 4 until the substrate insulating layer 9 of the SOI wafer is exposed, and reserving space for forming the partial regions of the gate electrode 6 in the etched away regions; synchronously etching away partial areas of the insulating medium layers 11 positioned on the upper side and the lower side of the electrode insulating layer 4 and corresponding to the central area of the semiconductor film area 3 until the substrate insulating layer 9 of the SOI wafer is exposed, and reserving space for the partial areas of the programmable floating gate 5;
step seven: as shown in fig. 16, 17, 18, 19, 20 and 21, by depositing a metal, alloy or metal silicide over the structure formed in the step six and planarizing to expose the gate electrode insulating layer 4, forming preliminarily a gate electrode 6 and a partial region of the programmable floating gate 5 on both upper and lower sides of the gate electrode insulating layer 4, and further forming interchangeable electrodes a1, b2;
step eight: as shown in fig. 22, 23, 24, 25, 26 and 27, an insulating medium is deposited by a deposition process, and the upper surfaces of the gate electrode 6 formed in the step seven and the partial region of the gate electrode insulating layer 4 corresponding to the gate electrode 6 are exposed by a photolithography and etching process, while the upper surfaces of the partial region of the programmable floating gate 5 formed in the step seven and the partial region of the gate electrode insulating layer 4 corresponding to the partial region of the programmable floating gate 5 are exposed, while the upper surfaces of the partial regions of the interchangeable electrode a1 and the interchangeable electrode b2 formed in the step seven are exposed, and further the interchangeable electrode a1, the interchangeable electrode b2, the programmable floating gate 5, the gate electrode 6 and the insulating medium layer 11 are formed by a planarization process after depositing a metal, an alloy or a metal silicide again by a deposition process until the insulating medium layer 11 is exposed;
step nine: as shown in fig. 28, 29, 30, 31, 32 and 33, an insulating medium is deposited by a deposition process, and the upper surfaces of the left and right side partial regions of the gate electrode 5 on the gate electrode insulating layer 4 side formed in the step eight and the partial regions of the insulating medium layer 11 corresponding to the left and right side partial regions of the gate electrode 5 on the gate electrode insulating layer 4 side are exposed by a photolithography and etching process, so that a space is reserved for the left and right side partial interconnection regions of the gate electrode 5 on the gate electrode insulating layer 4 side; simultaneously exposing the upper surfaces of the partial areas of the interchangeable electrode a1 and the interchangeable electrode b2 and the upper surface of the partial area in the center of the programmable floating gate 5 formed in the step eight, depositing metal, alloy or metal silicide again through a deposition process, and then flattening until the insulating dielectric layer 11 is exposed, thereby further forming the interchangeable electrode a1, the interchangeable electrode b2, the programmable floating gate 5, the gate electrode 6 and the insulating dielectric layer 11;
step ten: as shown in fig. 34, 35, 36, 37 and 38, an insulating medium is deposited through a deposition process, the exchangeable electrode a1, the exchangeable electrode b2 and the area right above the gate electrode insulating layer 4 formed in the step nine are etched through photoetching and etching processes until the exchangeable electrode a1, the exchangeable electrode b2 and the programmable floating gate 5 are exposed, metal, alloy or metal silicide is deposited through a deposition process again and then planarized until the insulating medium layer 11 is exposed, partial areas of the metal, alloy or metal silicide on the left side and the right side above the programmable floating gate 5 formed in the step nine are etched through etching processes until the insulating medium layer 11 is exposed, the exchangeable electrode a1, the exchangeable electrode b2 and the programmable floating gate 5 are further formed, space is reserved for the programming tunneling layer a7 and the programming tunneling layer b8, insulating material is deposited through a deposition process and planarized until the exchangeable electrode a1, the exchangeable electrode b2, the programmable floating gate 5 and the insulating medium layer 11 are exposed, and the programming tunneling layer a7 and the programming tunneling layer b8 are formed;
step eleven: as shown in fig. 1 and 2, an insulating medium is deposited by a deposition process, the interchangeable electrode a1 and the interchangeable electrode b2 formed in the step ten are etched by photolithography and etching processes, and a metal, an alloy or a metal silicide is deposited again by the deposition process and then planarized until the insulating medium layer 11 is exposed, thereby further forming the interchangeable electrode a1 and the interchangeable electrode b2.
Claims (6)
1. Source-drain assisted programmable single gate schottky barrier transistor comprising a silicon substrate (10) of an SOI wafer, characterized in that: a substrate insulating layer (9) of the SOI wafer is arranged above a silicon substrate (10) of the SOI wafer, and a semiconductor film region (3), an interchangeable electrode a (1) and an interchangeable electrode b (2) are arranged above the substrate insulating layer (9) of the SOI wafer; the upper part and the side surface of the semiconductor film region (3), the upper part and the side surface of the inner part regions of the interchangeable electrode a (1) and the interchangeable electrode b (2) are gate electrode insulating layers (4); a programmable floating gate (5), a gate electrode (6) and an insulating medium layer (11) are arranged above and on the side surface of the gate electrode insulating layer (4); the semiconductor thin film region (3) is made of semiconductor material, and the interchangeable electrode a (1) and the interchangeable electrode b (2) are made of metal, alloy or metal silicide, are respectively positioned at the left side and the right side of the semiconductor thin film region (3), and respectively form barrier type contact with the left side and the right side surfaces of the semiconductor thin film region (3) with Schottky barriers; the gate electrode insulating layer (4) is made of insulating dielectric materials; the programmable floating gate (5) is made of metal, alloy, polysilicon or silicon nitride, is positioned above the center of the gate electrode insulating layer (4) and on the side surface, and is insulated and isolated from the gate electrode (6), the interchangeable electrode a (1) and the interchangeable electrode b (2) through the insulating medium layer (11); the gate electrode (6) is made of metal, alloy or polysilicon, is positioned above two sides of the semiconductor film region (3) and is positioned on the upper surface and the side surface of the gate electrode insulating layer (4) corresponding to the sides, and is insulated and isolated from the gate electrode (5), the interchangeable electrode a (1) and the interchangeable electrode b (2) through the insulating medium layer (11); the left side and the right side above the programmable floating gate (5) are respectively contacted with a programming tunneling layer a (7) and a programming tunneling layer b (8); the left side surface of the programming tunneling layer a (7) is contacted with the interchangeable electrode a (1); the right side of the programming tunneling layer b (8) is in contact with the interchangeable electrode b (2); the thickness between the left and right sides of the programming tunneling layer a (7) is smaller than the thickness between the left and right sides of the programming tunneling layer b (8).
2. The source-drain assisted programmable single gate schottky barrier transistor of claim 1 wherein: the source-drain auxiliary programmable single-gate Schottky barrier transistor has a bilateral symmetry structure in the area below the lower surfaces of the programming tunneling layer a (7) and the programming tunneling layer b (8); the interchangeable electrode a (1) and the interchangeable electrode b (2) can be interchanged with each other after the resettable floating gate (5) is non-volatile reset, i.e. the conductivity type is determined.
3. A method of controlling a source-drain assisted programmable single gate schottky barrier transistor according to claim 1, wherein: the programming tunneling layer a (7) and the programming tunneling layer b (8) are made of the same insulating material, and the thickness between the left side and the right side of the programming tunneling layer a (7) is less than 4 nanometers; when a potential difference is applied between the interchangeable electrode b (2) and the interchangeable electrode a (1), the resistance values of the programming tunneling layer a (7) and the programming tunneling layer b (8) are reduced due to the tunneling effect of the insulating layers in the programming tunneling layer a (7) and the programming tunneling layer b (8), and the thickness between the left side and the right side of the programming tunneling layer a (7) is smaller than that between the left side and the right side of the programming tunneling layer b (8), as the potential difference is continuously increased between the interchangeable electrode b (2) and the interchangeable electrode a (1), the tunneling effect of the insulating layers occurs in the programming tunneling layer a (7) before the programming tunneling layer b (8), after the tunneling effect of the insulating layers occurs in the programming tunneling layer a (7), charges flowing into the programmable floating gate (5) from the programming tunneling layer a (7) to the programming tunneling layer b (8) are enabled to flow out to the interchangeable electrode b (2), and thus the charge amount in the programmable floating gate (5) is controlled to be more than the charge amount in the programmable floating gate (5).
4. A method of controlling a source-drain assisted programmable single gate schottky barrier transistor according to claim 3, wherein: when a positive potential difference is applied between the interchangeable electrode b (2) and the interchangeable electrode a (1), negative charges flowing from the interchangeable electrode a (1) into the programmable floating gate (5) through the programming tunneling layer a (7) are more than negative charges flowing from the programmable floating gate (5) through the programming tunneling layer b (8) and out to the interchangeable electrode b (2), and the net residual negative charge in the programmable floating gate (5) is increased or the net residual positive charge in the programmable floating gate (5) is reduced through the process;
when a negative potential difference is applied between interchangeable electrode b (2) and interchangeable electrode a (1), positive charges from interchangeable electrode a (1), pass programming tunneling layer a (7) flow into programmable floating gate (5) more than positive charges from programmable floating gate (5) pass programming tunneling layer b (8) and flow out to interchangeable electrode b (2), thereby increasing the net positive charge in programmable floating gate (5) or decreasing the net negative charge in programmable floating gate (5).
5. A method of controlling a source-drain assisted programmable single gate schottky barrier transistor according to claim 3, wherein: the programmable floating gate (5) is a region formed by materials such as metal, alloy, polysilicon, silicon nitride and the like, the internal net residual charge type and the charge quantity of the programmable floating gate are changed by applying electric potential between the interchangeable electrode b (2) and the interchangeable electrode a (1) and enabling the programming tunneling layer a (7) and the programming tunneling layer b (8) to generate insulating layer tunneling effect; when the net residual charge in the programmable floating gate (5) is positive charge, an electric field effect is generated on the semiconductor film region (3) and positive charge 'holes' in the semiconductor film region (3) are blocked from flowing between the two sides of the interchangeable electrode a (1) and the interchangeable electrode b (2), so that the source-drain auxiliary programmable single gate Schottky barrier transistor is controlled to work in an N-type mode; when the net residual charge in the programmable floating gate (5) is negative, an electric field effect is generated in the semiconductor film region (3) and negative charge electrons in the semiconductor film region (3) are blocked from flowing between the two sides of the interchangeable electrode a (1) and the interchangeable electrode b (2), so that the source-drain auxiliary programmable single gate Schottky barrier transistor is controlled to work in a P type mode.
6. A method of fabricating a source-drain assisted programmable single gate schottky barrier transistor according to claim 1, wherein:
the manufacturing steps are as follows:
step one: providing an SOI wafer, wherein the silicon substrate (10) of the SOI wafer is arranged at the bottom, the substrate insulating layer (9) of the SOI wafer is arranged on the silicon substrate, the upper surface of the substrate insulating layer (9) of the SOI wafer is a semiconductor film, and partial areas of the interchangeable electrode a (1) and the interchangeable electrode b (2) are formed preliminarily through photoetching, etching and deposition processes;
step two: etching the upper, lower, left and right partial areas of the semiconductor film in the first step until the substrate insulating layer (9) of the SOI wafer is exposed, so as to form a semiconductor film area (3);
step three: forming insulating dielectric layers above and on the side surfaces of the interchangeable electrode a (1), the interchangeable electrode b (2) and the semiconductor film region (3) through a deposition process, and then performing planarization treatment to initially form a gate electrode insulating layer (4);
step four: etching partial areas above and below the gate electrode insulating layer (4) preliminarily formed in the third step through an etching process to further form the gate electrode insulating layer (4);
step five: depositing an insulating medium above the gate electrode insulating layer (4) formed in the fourth step through a deposition process, and performing planarization treatment until the upper surface of the gate electrode insulating layer (4) is exposed, so as to initially form an insulating medium layer (11);
step six: etching partial areas on two sides of the gate electrode insulating layer (4) until the substrate insulating layer (9) of the SOI wafer is exposed through photoetching and etching processes, etching areas, corresponding to the left and right sides of the semiconductor thin film region (3), of the insulating dielectric layers (11) on the upper side and the lower side of the electrode insulating layer (4) until the substrate insulating layer (9) of the SOI wafer is exposed, wherein the etched areas are reserved for forming partial areas of the gate electrode (6); synchronously etching away partial areas of the insulating medium layers (11) positioned on the upper side and the lower side of the electrode insulating layer (4) and corresponding to the central area of the semiconductor film area (3) until the substrate insulating layer (9) of the SOI wafer is exposed, and reserving space for the partial areas of the programmable floating gate (5);
step seven: depositing metal, alloy or metal silicide above the structure formed in the step six and flattening the metal silicide until the gate electrode insulating layer (4) is exposed, initially forming partial areas of the gate electrode (6) and the programmable floating gate (5) which are positioned on the upper side and the lower side of the gate electrode insulating layer (4), and further forming an interchangeable electrode a (1) and an interchangeable electrode b (2);
step eight: depositing an insulating medium through a deposition process, exposing the gate electrode (6) formed in the step seven and the upper surface of a partial area of the gate electrode insulating layer (4) corresponding to the gate electrode (6) through a photoetching and etching process, exposing the partial area of the programmable floating gate (5) formed in the step seven and the upper surface of a partial area of the gate electrode insulating layer (4) corresponding to the partial area of the programmable floating gate (5), exposing the upper surfaces of the interchangeable electrode a (1) and the partial area of the interchangeable electrode b (2) formed in the step seven, depositing metal, alloy or metal silicide through the deposition process again and then flattening until the insulating medium layer (11) is exposed, and further forming the interchangeable electrode a (1), the interchangeable electrode b (2), the programmable floating gate (5), the gate electrode (6) and the insulating medium layer (11);
step nine: depositing an insulating medium through a deposition process, exposing the upper surfaces of the left and right side partial areas of the gate electrode (5) positioned at one side of the gate electrode insulating layer (4) formed in the step eight and the partial areas of the insulating medium layer (11) corresponding to the left and right side partial areas of the gate electrode (5) positioned at one side of the gate electrode insulating layer (4) through photoetching and etching processes, and reserving a space for the left and right side partial interconnection areas of the gate electrode (5) positioned at one side of the gate electrode insulating layer (4); simultaneously exposing the upper surfaces of the partial areas of the interchangeable electrode a (1) and the interchangeable electrode b (2) formed in the step eight and the upper surface of the partial area in the center of the programmable floating gate (5), depositing metal, alloy or metal silicide again through a deposition process, and then flattening until the insulating dielectric layer (11) is exposed, so as to further form the interchangeable electrode a (1), the interchangeable electrode b (2), the programmable floating gate (5), the gate electrode (6) and the insulating dielectric layer (11);
step ten: depositing an insulating medium through a deposition process, etching away the regions, which correspond to the upper part of the interchangeable electrode a (1), the interchangeable electrode b (2) and the gate electrode insulating layer (4) formed in the step nine, until the interchangeable electrode a (1), the interchangeable electrode b (2) and the programmable floating gate (5) are exposed, depositing metal, alloy or metal silicide through the deposition process again and then flattening until the insulating medium layer (11) is exposed, etching away partial regions of the metal, alloy or metal silicide, which are positioned on the left side and the right side above the programmable floating gate (5) formed in the step nine, until the insulating medium layer (11) is exposed through the etching process, further forming the interchangeable electrode a (1), the interchangeable electrode b (2) and the programmable floating gate (5), reserving spaces for the programming tunneling layer a (7) and the programming tunneling layer b (8), depositing insulating materials through the deposition process and flattening until the interchangeable electrode a (1), the interchangeable electrode b (2), the programmable tunneling layer (5) and the insulating medium layer (11) are exposed, and forming the programming layer a (7) and the programming layer (8);
step eleven: depositing an insulating medium through a deposition process, etching the interchangeable electrode a (1) and the interchangeable electrode b (2) formed in the step ten through a photoetching and etching process, depositing metal, alloy or metal silicide through the deposition process again, and then flattening until the insulating medium layer (11) is exposed, so as to further form the interchangeable electrode a (1) and the interchangeable electrode b (2).
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| CN1401140A (en) * | 2000-08-14 | 2003-03-05 | 矩阵半导体公司 | Dense arrays and charge storage devices, and methods for making same |
| KR20140116264A (en) * | 2013-03-21 | 2014-10-02 | 한양대학교 산학협력단 | 2-Terminal Switching Device Having Bipolar Switching Property and Resistance Memory Cross-Point Array Having the Same |
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