JP3194871B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a dynamic random access memory and a nonvolatile memory.

[0002]

BACKGROUND OF THE INVENTION Semiconductor integrated circuit device having a built-in microcomputer, RAM as a memory unit of the microcomputer (R andom A ccess M emory)
And has a ROM (R ead O nly M emory ). The RAM is mounted S (S Tatic) RAM, the memory cell (memory element) of the six MOS
It is composed of an FET (6 MOS configuration). The ROM mask ROM, EP (E rasable P rog
rammable) ROM or EEP (E lectri
cally E rasable P rogrammab
le) ROM is mounted. EEPROM is FLO
TOX (Flo ating Gate T unnel
Ox ide) memory cell structures are used.

[0005] The semiconductor integrated circuit device having the above-described structure uses 6 SRAM memory cells as a RAM.
Because of the MOS structure, the memory cell area increases and the degree of integration decreases. Therefore, as a RAM of this type of semiconductor integrated circuit device, D (Dynam) is used instead of the SRAM.
ic) There is a proposal to use a RAM. For example, published by Nikkei McGraw-Hill, Nikkei Micro Devices, July 1987, pp. 71-73. In the DRAM of the proposed semiconductor integrated circuit device, the memory cell is changed to a memory cell selecting M.
It is composed of a series circuit of an OSFET and an information storage capacitor. The information storage capacitor has a so-called planar structure in which an n-type semiconductor region (lower electrode), a dielectric film, and a plate electrode (upper electrode) formed on the main surface of the semiconductor substrate are sequentially stacked.

The semiconductor integrated circuit device has a feature that the number of elements of a DRAM memory cell is small, so that the area of the memory cell can be reduced and the degree of integration can be improved.

[0005] The semiconductor integrated circuit device may be an EEP.
Since the memory cells of the DRAM are formed by using a part of the manufacturing process of the memory cell having the FLOTOX structure of the ROM, the manufacturing process can be reduced. This semiconductor integrated circuit device has a DRAM, an EEPR
The MIS and the MISFET constituting the peripheral circuit are mounted, and the method of manufacturing these elements is as follows.

First, a gate insulating film is formed on a main surface portion of a semiconductor substrate in a floating gate electrode forming region of a memory cell having a FLOTOX structure of an EEPROM.

Next, a part of the gate insulating film is removed,
A tunnel silicon oxide film having a thickness smaller than that of the gate insulating film is formed.

Next, a floating gate electrode is formed on the gate insulating film and the tunnel silicon oxide film.

Next, a gate insulating film is formed on the floating gate electrode. Using this process, a dielectric film (silicon oxide film) of an information storage capacitor of a memory cell of a DRAM and a gate insulating film of a MISFET of a peripheral circuit are formed by the same manufacturing process as that process.

Next, a control gate electrode is formed on the floating gate electrode of the FLOTOX memory cell with a gate insulating film interposed therebetween. Utilizing this process, a plate electrode (upper electrode) is formed on the dielectric film of the information storage capacitor of the memory cell of the DRAM and a gate electrode is formed on the gate insulating film of the MISFET of the peripheral circuit by the same manufacturing process as that process. Form.

[0011]

As described above, the dielectric film of the information storage capacitor element is, as described above, a gate insulating film between the floating gate electrode and the control gate electrode of the memory cell having the FLOTOX structure and the peripheral circuit. MISF
It is formed by the same manufacturing process as the gate insulating film of ET. Since a relatively high voltage required for writing, reading, and erasing information is applied to the control gate electrode of the FLOTOX memory cell, the gate insulating film below the control gate electrode is formed with a small thickness. Can not do. Since an operating voltage of about 5 [V] is normally applied to the gate electrode of the MISFET of the peripheral circuit,
The gate insulating film below the gate electrode cannot be formed with a small thickness. Therefore, the dielectric film of the information storage capacitor formed in the same manufacturing process as the gate insulating film is formed to have substantially the same thickness as the gate insulating film. For this reason, the amount of charge stored in the information storage capacitance element of the memory cell of the DRAM decreases, and the area occupied by the information storage dose element increases to increase the charge amount. As a result,
Since the area occupied by the RAM increases, the degree of integration of the semiconductor integrated circuit device decreases.

In order to increase the amount of charge of the information storage capacitor of the memory cell of the DRAM, FLOTO
It is necessary to form a dielectric film in a different manufacturing process from the gate insulating film of the X structure and the gate insulating film of the MISET of the peripheral circuit. Therefore, in order to improve the degree of integration, the number of manufacturing steps of the semiconductor integrated circuit device increases.

Further, in the semiconductor integrated circuit device,
No consideration is given to improving the characteristics of the edge circuit .

[0014] The challenges of the present invention, dynamic memory (D
In a semiconductor integrated circuit device provided with
Integration that can optimize the characteristics of circuit elements
It is to provide a circuit device .

Another object of the present invention is to manufacture the above-described improved characteristics.
An object of the present invention is to provide a technology that can be realized without increasing the number of processes .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

Information storage capacitor and memory cell selection
Dynamic memory element having MISFET,
A first MISFET and a second MI
Semiconductor integrated circuit having SFET and one semiconductor substrate
Device, a gate insulating film of the first MISFET
Film thickness of MISFET for memory cell selection
And the gate of the second MISFET
The thickness of the insulating film depends on the memory cell selecting MISFET.
Different from (thick or thin) the gate insulating film
And Also, information storage capacitor and memory cell selection
Dynamic storage element having a MISFET for
MISFET and second M
Semiconductor integrated circuit with ISFET and one semiconductor substrate
Memory device selecting MISF
Sequentially forming a gate insulating film of ET;
The gate insulating film of the MISFET is changed to the memory cell selecting M
Thickness different from the gate insulating film of ISFET (thick or
Forming the first MISFE
The gate insulating film of T is used as a memory cell selection MISFET
It is formed in the same manufacturing process as the process of forming the gate insulating film .

According to the above-described means, the first M
Of each gate insulating film of the ISFET and the second MISFET
The film thickness can be changed, and multiple MISFE
Optimal peripheral circuit characteristics when T has different operating voltages
Semiconductor integrated circuit devices can be provided.
At the same time, the first MISFET and the memory cell selecting M
The thickness of each gate insulating film with the ISFET should be substantially the same.
As a result, the first MISFET and the memory cell selecting MI
Form each gate insulating film with SFET by the same process
Inexpensive semiconductors by reducing the number of manufacturing processes
An integrated circuit device can be provided . Hereinafter, the configuration of the present invention, the present invention is <br/> described together with an embodiment applied to a semiconductor integrated circuit device having a built-in microcomputer.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment I) A semiconductor integrated circuit device incorporating a microcomputer according to Embodiment 1 of the present invention is shown in FIG.
(A) and FIG. 1 (b) (a cross-sectional view of a main part showing each element).

As shown in FIGS. 1 (a) and 1 (b),
The semiconductor integrated circuit device is constituted by a p-type semiconductor substrate 1 made of one common single crystal silicon. That is, although the semiconductor substrate 1 is illustrated separately in FIG. 1A and FIG. 1B for drawing, it is actually integrally configured.

As shown in FIG. 1A, the main surface of the semiconductor substrate 1 has an R
The storage elements of the AM and the ROM are configured. The RAM is composed of a DRAM, and its memory cell (dynamic storage element) DM is described. ROM is EE
A PROM, an EPROM, and a mask ROM are configured, and a memory cell (nonvolatile storage element) FM of a FLOTOX structure of an EEPROM and a memory cell (nonvolatile storage element) EM of an EPROM are described. Since the memory cell of the mask ROM has substantially the same structure as the element (n-channel MISFET) shown in FIG. 1B, it is not shown or described here. Also,
As shown in FIG. 1B, a complementary MISFET (CM) constituting a peripheral circuit is formed on a main surface of another region of the semiconductor substrate 1.
OS). CMOS is an n-channel MI
SFET Qn ₁ , Qn ₂ , p-channel MISFET Q
It is configured by combining each of n ₁ and Qn ₂ . Each of the p-channel MISFETs Qp ₁ and Qn ₂ is formed on the main surface of an n ~ -type well region 2 provided on the main surface of the semiconductor substrate 1.

The semiconductor element formed on the main surface of the semiconductor substrate 1 is electrically separated from other regions by the field insulating film 3 and the p-type channel stopper region 4. The semiconductor element formed on the main surface of the well region 2 is the field region 2
The semiconductor element formed on the main surface is electrically isolated from other regions by the field insulating film 3. Field insulating film 3 is formed of a silicon oxide film in which the main surfaces of semiconductor substrate 1 and well region 2 are selectively oxidized. The channel stopper region 4 is located on the main surface of the semiconductor substrate 1 and below the field insulating film 3.

FIG. 1A shows a memory cell DM of a DRAM.
As shown on the left side of FIG.
It is composed of a series circuit of ds and an information storage capacitive element C.

The information storage capacitor C is formed by sequentially superposing an n-type semiconductor region (lower electrode) 7, a dielectric film 8, and a plate electrode (upper electrode) 9. The information storage capacitance element C has a so-called planar structure (MOS structure).

The semiconductor region 7 is formed on the main surface of the semiconductor substrate 1.

The dielectric film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of the semiconductor region 7 (semiconductor substrate 1). The dielectric film 8 has substantially the same thickness as a tunnel insulating film (silicon oxide film) 8 of a memory cell FM of an EEPROM described later.
For example, it is formed with a thin film thickness of about 100 [Å].
Each of the dielectric film 8 and the tunnel insulating film 8 is a MISFET Qds for selecting a memory cell and a MISFET of a peripheral circuit.
The gate insulating films Qn ₁ , Qn ₂ , Qn ₁ , and Qn ₂ are formed to be thinner than the respective gate insulating films 6 or 12. That is, since the dielectric film 8 of the information storage capacitor C is formed to be thin, the charge storage amount of the information storage capacitor C can be increased and the area of the memory cell DM can be reduced. I have.

The plate electrode 9 is formed on the dielectric film 8. The plate electrode 9 is formed of, for example, a polycrystalline silicon film into which an impurity (P, As or B) for reducing a resistance value is introduced. The plate electrode 9 is, for example, 3000 to 4
It is formed with a thickness of about 000 [Å]. This plate electrode 9 is formed of the first-layer gate electrode material in the manufacturing process. An interlayer insulating film 10 is provided on the surface of the plate electrode 9.

The memory cell selection MISFET Qds is
Mainly, semiconductor substrate 1, gate insulating film 12, gate electrode 1
3. It comprises a pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19, which are a source region and a drain region. That is, the memory cell selecting MISFET Qds
Is composed of an n-channel MISFET.

The semiconductor substrate 1 is used as a channel forming region.

Gate insulating film 12 is formed of a silicon oxide film obtained by oxidizing the main surface of semiconductor substrate 1. As described above, the gate insulating film 12 is formed to be thicker than the dielectric film 8 of the information storage capacitor C, for example, to have a thickness of about 250 [Å]. In other words, the gate insulating film 12 can ensure a withstand voltage between the semiconductor substrate 1 and the gate electrode 13 in a normal operation range (for example, when the voltage between the semiconductor substrate 1 and the gate electrode 13 is 5 [V]). It is configured as follows.

The gate electrode 13 is formed on the gate insulating film 12. The gate electrode 13 is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. The gate electrode 13 is, for example, 3000 to 4000 [Å].
It is formed with a film thickness of about. The gate electrode 13 is formed of the second-layer gate electrode material in the manufacturing process. The gate electrode 13 is provided with a single-layer high-melting-point metal film or a high-melting-point metal silicide film, or a high-melting-point metal film or a high-melting-point metal silicide film on a polycrystalline silicon film in order to reduce the resistance value. It may be formed of a composite film. The gate electrode 13 is formed integrally with the word line (WL) 13.

The n-type semiconductor region 15 having a low impurity concentration is provided between the n + -type semiconductor region 19 having a high impurity concentration and a channel forming region. This semiconductor region 15 is a so-called L
Constitute a MISFET of the DD (L ightly D oped D rain ) structure. The semiconductor region 15 is configured to be self-aligned with the gate electrode 13. The n + -type semiconductor region 19 having a high impurity concentration is self-aligned with the gate electrode 13 with the sidewall spacer 18 interposed therebetween.

This memory cell selecting MISFET Qds
One semiconductor region 19 is integrally formed (connected) with the semiconductor region 7 which is the lower electrode of the information storage capacitor C. In the other semiconductor region 19 of the memory cell selecting MISFET Qds, the connection hole 2 formed in the interlayer insulating film 21 is formed.
2, a wiring 23 is connected. The wiring 23 is used as a complementary data line (DL). The wiring 23 is formed of, for example, aluminum, aluminum alloy to which Si or Cu is added. Si reduces the alloy spike phenomenon. Cu reduces stress migration.

Although not shown, a final passivation film is formed on the memory cell DM thus configured.

The memory cell FM of the EEPROM is shown in FIG.
As shown in the center of FIG. 7A, a field effect transistor Qf having a FLOTOX structure and a MISFET for selecting a memory cell are used.
It is composed of a series circuit with Qfs. That is, the memory cell FM has a two-transistor structure.

The field effect transistor Qf is configured to have information "1" or "0". The field effect transistor Qf mainly includes a semiconductor substrate 1, a semiconductor region 7, a gate insulating film 6, a tunnel insulating film 8, a floating gate electrode 9, a gate insulating film 11, a control gate electrode 13, and a pair of a source region and a drain region. It comprises an n-type semiconductor region 15 and a pair of n + -type semiconductor regions 19.

The semiconductor substrate 1 is used as a channel forming region.

The semiconductor region 7 is formed integrally with a semiconductor region 19 used as a drain region, and extends to the main surface of the semiconductor substrate 1 below the tunnel insulating film 8.

Gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the main surface of semiconductor substrate 1. The gate insulating film 6 is formed to be thicker than the dielectric film 8 of the information storage capacitor C, for example, about 500 [Å] thick. That is, the gate insulating film 6 is connected to the semiconductor region 7 and the floating gate electrode in a normal information writing operation and erasing operation range (for example, the voltage between the semiconductor region 7 and the control gate electrode 13 is 17 to 20 [V]). 9 is ensured.

The tunnel insulating film 8 is formed of a silicon oxide film obtained by removing a part of the gate insulating film 6 below the floating gate electrode 9 and oxidizing the removed surface of the main surface of the semiconductor substrate 1. The tunnel insulating film 8 is formed with a thin film thickness, for example, about 100 [Å] similarly to the dielectric film 8. Thus, the tunnel insulating film 8 having a small thickness is formed.
Since the amount of tunnel current per unit area can be increased, the time required for the information writing operation and the erasing operation of the memory cell FM can be reduced.

The floating gate electrode 9 is made of a first-layer gate electrode material, like the plate electrode 9 of the information storage capacitor C.

Gate insulating film 11 is formed of a silicon oxide film obtained by oxidizing the surface of floating gate electrode 9.
The gate insulating film 11 is configured to secure a withstand voltage between the floating gate electrode 9 and the control gate electrode 13 in the information writing operation, the reading operation, and the erasing operation range. The gate insulating film 11 is, for example, 30
It is formed with a relatively thick film thickness of about 0 to 400 [Å].

The control gate electrode 13 is provided on the gate insulating film 11. Control gate electrode 1
3 is a memory cell selection MI of the DRAM memory cell DM.
Like the gate electrode 13 of the SFET Qds, it is made of a second-layer gate electrode material.

The field effect transistor Qf has an LDD structure.

The memory cell selection MISFET Qfs is
Basically, it is composed of a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19 which are a source region and a drain region.

Each of the gate insulating film 6 and the gate electrode 9 is
Each of the field effect transistors Qf is configured in substantially the same manufacturing process. MISFET for memory cell selection
Qfs has an LDD structure. Semiconductor region 1 which is the source region of memory cell selecting MISFET Qfs
Reference numeral 9 is integrally formed with a semiconductor region 19 which is a drain region of the field effect transistor Qf.

The shunt wiring 13 is provided on the gate electrode 9 of the memory cell selecting MISFET Qfs with an interlayer insulating film 11 interposed. This shunt wiring 13
Indicates that the interlayer insulating film 11 is provided for each memory cell selecting MISFET Qfs or every predetermined number in the direction in which the word line extends.
Is connected to the gate electrode 9 through a connection hole (not shown) formed in the substrate. That is, the shunt wiring 13 is
The resistance value of the gate electrode 9 of the memory cell selection MISFET Qfs and the word line integrally formed with the gate electrode 9 can be reduced. In addition, the memory cell selecting MISFET Q
fs has a two-layer gate structure composed of the gate electrode 9 and the shunt wiring 13 as in the case of the field effect transistor Qf. Thus, the field effect transistor Q
f, when each of the memory cell selecting MISFETs Qfs is configured with a two-layer gate structure, the gate-to-gate dimension of both can be defined only by the processing dimension without requiring a mask alignment margin in the manufacturing process. That is, the space between the field effect transistor Qf and the memory cell selecting MISFETfs can be reduced, and the occupied area of the memory cell FM can be reduced.

Field effect transistor Q of memory cell FM
A wiring 23 is connected to a semiconductor region 19 which is a source region of f through a connection hole 22. This wiring 23 is used as a source wiring (SL). A wiring 23 is connected through a connection hole 22 to a semiconductor region 19 which is a drain region of the memory cell selecting MISFET Qfs of the memory cell FM. This wiring 23 is used as a data line (DL).

The memory cell EM of the EPROM is shown in FIG.
As shown on the right side of (a), it is composed of a field effect transistor. The memory cell EM mainly includes a semiconductor substrate 1, a gate insulating film 6, a floating gate electrode 9, a gate insulating film 11, a control gate electrode 13, and a pair of n-type semiconductor regions 16 serving as a source region and a drain region.
And a pair of n + -type semiconductor regions 19.

This memory cell EM is stored in the EEPROM.
The memory cell FM has a two-layer gate structure and an LDD structure, similarly to the field effect transistor Qf of the memory cell FM.
The n-type semiconductor region 16 having a low impurity concentration of the field effect transistor which is the memory cell EM has the M of the LDD structure.
Low impurity concentration n such as ISFETs Qds, Qf, Qfs
It has a higher impurity concentration than the type semiconductor region 15. Further, the semiconductor region 16 is provided with another MISFET Qd
It has a lower impurity concentration than the n + -type semiconductor region 19 having a high impurity concentration such as s, Qf, Q, and s. The semiconductor region 16 is configured to increase the electric field intensity near the drain region of the field effect transistor to increase the amount of generated hot carriers. That is, the semiconductor region 16 increases the amount of generated hot electrons injected into the floating gate electrode 9 of the memory cell EM,
The information writing operation time can be reduced. Further, the semiconductor region 16 is configured to reduce the resistance values of the source region and the drain region near the channel formation region, reduce the transmission conductance, and shorten the information read time.

A wiring 23 is connected through a connection hole 22 to a semiconductor region 19 which is a source region of a field effect transistor which is a memory cell EM. The wiring 23 is used as a source wiring (SL). A connection hole 22 is formed in a semiconductor region 19 which is a drain region of the field effect transistor.
The wiring 23 is connected through the connection. The wiring 23 is used as a data line (DL).

The peripheral circuit CMOS, that is, n-channel MISFETs Qn ₁ and Qn ₂ , p-channel MISFET Q
Each of p ₁ and Qp ₂ is configured as shown in FIG. 1B.

The n-channel MISFET Qn ₁ includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 serving as source and drain regions, and a pair of n + -type semiconductor regions 19. .

The n-channel MISFET Qn ₂ includes a semiconductor substrate 1, a gate insulating film 12, a gate electrode 13, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n + -type semiconductor regions 19. .

The p-channel MISFET Qp ₁ includes a well region 2, a gate insulating film 6, a gate electrode 9, a pair of p-type semiconductor regions 17 serving as a source region and a drain region, and a pair of p + -type semiconductor regions 20. .

The p-channel MISFET Qp ₂ includes a well region 2, a gate insulating film 12, a gate electrode 13, a pair of p-type semiconductor regions 17 serving as source and drain regions, and a pair of p + -type semiconductor regions 20. .

Each of the n-channel MISFET Qn ₁ and the p-channel MISFET Qp ₁ is connected to the memory cell F
The gate insulating film 6 and the gate electrode 9 are formed by the same manufacturing process as the gate insulating film 6 and the floating gate electrode 9 of the M field effect transistor Qf and the like. That is, in each of the n-channel MISFET Qn ₁ and the p-channel MISFET Qp ₁ , the gate electrode 9 is formed of the first-layer gate electrode material.

On the other hand, the n-channel MISFET Q
Each of the n ₂ and p-channel MISFETs Qp ₂ has the gate insulating film 12 and the gate electrode 13 formed by the same structure process as the gate insulating film 12 and the gate electrode 13 of the memory cell selecting MISFET Qds of the memory cell DM. ing. That is, the n-channel MISFET Q
In each of the n ₂ and p-channel MISFETs Qp ₂ , the gate electrode 13 is formed of the gate electrode material of the second layer.

The MISFETs Qn ₁ , Qn ₂ , Qp ₁ ,
Each of Qp ₂ has an LDD structure. A wiring 23 is connected to each semiconductor region 19 of the n-channel MISFETs Qn ₁ and Qn ₂ . p-channel MISFET
A wiring 23 is connected to each of the semiconductor regions 20 of Qp ₁ and Qp ₂ .

As described above, the DRAM memory cell DM
(Dynamic storage element), memory cell FM (nonvolatile storage element) having FLOTOX structure, and MIS of peripheral circuit
In a semiconductor integrated circuit device provided with FETs (Qn ₁ , Qn ₂ , Qp ₁ , Qp ₂ ), the dielectric film 8 of the information storage capacitor C of the memory cell DM and the field effect transistor Qf of the memory cell FM The tunnel insulating film 8 is
By making the film thickness smaller than the gate insulating film 6 or 12 of the ISFET, the amount of charge stored in the information storage capacitor C can be improved and the area occupied by the memory cell DM can be reduced. And the amount of tunnel current that can flow through the tunnel insulating film 8 can be increased.
The information writing time of M can be shortened, and the M
Since the withstand voltage of the gate insulating film 6 or 12 of the ISFET can be improved, the electrical reliability can be improved.

Next, a method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 2 (a) and 2 (b) to 9 (a) and 9 (b). ) Will be described briefly.

First, a p ~ type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, the p-channel MI of the peripheral circuit CMOS
In the SFET Qp ₁ and Qp ₂ formation regions, an n 形成 -type well region 2 is formed on the main surface of the semiconductor substrate 1. Also, n ~
CMOS n channel MISFE of the entire region of the main surface of the semiconductor substrate 1 different from the mold well region 2 or the peripheral circuit.
A p-type well region may be formed in the TQn ₁ and Qn ₂ formation regions.

Next, a field insulating film 3 is formed on each of the main surfaces of the semiconductor substrate 1 and the well region 2 between the semiconductor element forming regions. The field insulating film 3 is formed of a silicon oxide film in which the respective main surfaces of the semiconductor substrate 1 and the well region 2 are selectively oxidized. The p-type channel stopper region 4 is formed under the field insulating film 3 on the main surface of the semiconductor substrate 1 by substantially the same manufacturing process as the step of forming the field insulating film 3.

Next, as shown in FIGS. 2A and 2B, a gate insulating film 6A is formed on each of the main surfaces of the semiconductor substrate 1 and the well region 2 in the semiconductor element formation region. This gate insulating film 6A is made of a field effect transistor or M
Used as a part of the gate insulating film of the ISFET. The gate insulating film 6A is formed of a silicon oxide film in which the main surfaces of the semiconductor substrate 1 and the well region 2 are oxidized.

Next, as shown in FIGS. 3A and 3B, in the area for forming the information storage capacitor C of the memory cell DM of the DRAM and the area for forming the field effect transistor Qf of the memory cell FM of the EEPROM. An n-type semiconductor region 7 is formed on the main surface of the semiconductor substrate 1 by the same manufacturing process.
The semiconductor region 7 forms a lower electrode (one electrode) in a region where the information storage capacitor C is formed. Further, the semiconductor region 7 is formed in the field effect transistor Qf formation region to allow a tunnel current to flow between the drain region (19) and the floating gate electrode (9). The semiconductor region 7 is formed by introducing an n-type impurity such as As or P into the main surface of the semiconductor substrate 1 through the gate insulating film 6A. The semiconductor region 7 has, for example, 10 ¹⁵ [atoms]
/ Cm ² ] is introduced by ion implantation at an energy of about 60 to 100 [KeV]. When introducing this n-type impurity, a photoresist film (not shown) is used as a mask for introduction.

Next, the gate insulating film 6A is selectively removed in the region for forming the information storage capacitor C of the memory cell DM of the DRAM and the region for forming the field effect transistor Qf of the memory cell FM of the EEPROM. The gate insulating film 6A in the region for forming the field effect transistor Qf removes a part under the region for forming the floating gate electrode (9).

Next, as shown in FIGS. 4A and 4B, in the region where the gate insulating film 6A has been removed,
The dielectric film 8 and the tunnel insulating film 8 are formed in the same manufacturing process on the main surface of the semiconductor substrate 1 (actually, the semiconductor region 7). The dielectric film 8 is formed on the main surface of the semiconductor region 7 in the information storage capacitor C forming region. The tunnel insulating film 8 is formed on the main surface of the semiconductor region 7 in the field effect transistor Qf formation region. Each of the dielectric film 8 and the tunnel insulating film 8 is formed of a silicon oxide film in which the main surface of the semiconductor region 7 is oxidized, and has a small thickness as described above. By the process of forming the dielectric film 8 and the tunnel insulating film 8, FIG.
As shown in FIG. 4A and FIG. 4B, the gate insulating film 6A
Is grown to form a gate insulating film 6. Since the thickness of the dielectric film 8 or the thickness of the tunnel insulating film 8 is added to the gate insulating film 6A, the gate insulating film 6 is formed with a large thickness as described above.

Next, on the dielectric film 8, the tunnel insulating film 8
A first-layer gate electrode layer 9 is deposited on the entire surface of the substrate including the upper portion, the gate insulating film 6, and the like. The first-layer gate electrode layer 9 is formed of, for example, a polycrystalline silicon film deposited by CVD. After the polycrystalline silicon film is deposited, an n-type impurity, for example, P for reducing the resistance value is introduced (ion implantation or thermal diffusion).

Next, a predetermined patterning is applied to the first gate electrode layer 9, as shown in FIGS. 5A and 5B.
As shown in (1), each of the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 is formed in the same manufacturing process. The plate electrode 9 is formed on the dielectric film 8 in the information storage capacitor C forming region of the memory cell DM of the DRAM. The floating gate electrode 9 is an EEPR
It is formed on the tunnel insulating film 8 and the gate insulating film 6 in the OM field-effect transistor Qf formation region and on the gate insulating film 6 in the field-effect transistor forming region of the EPROM, respectively. Each floating gate electrode 9 is patterned only in the gate width direction. The gate electrode 9
Memory cell selecting MISFETQfs formation region of the EEPROM, n-channel MISFET Qn ₁ forming region of the CMOS, it is formed on the gate insulating film 6 of each of the p-channel MISFET Qp ₁ forming region. By the step of forming the plate electrode 9, the semiconductor region (lower electrode) 7, the dielectric film 8, and the plate electrode (upper electrode) 9 are sequentially overlapped, and the information storage capacitor C of the memory cell DM of the DRAM is formed. Is completed.

Next, an insulating film covering the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 is formed. This insulating film is formed of a silicon oxide film in which the respective surfaces of the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 are oxidized.

Next, while the insulating film on the plate electrode 9 is left, the insulating film on the floating gate electrode 9 and the gate electrode 9 and the first gate electrode layer 9 are formed. The gate insulating film 6 in the non-existing region is selectively removed.

Next, an oxidation treatment is performed on the entire surface of the substrate, and FIG.
As shown in FIGS. 6A and 6B, the interlayer insulating film 10 on the surface of the plate electrode 9, the gate insulating film 11 on the surface of the floating gate electrode 9, the insulating film 11 on the surface of the gate electrode 9, and the semiconductor substrate 1 And a gate insulating film 12 is formed on the main surface of the well region 2 and on the main surface of the well region 2, respectively. Each of these interlayer insulating film 10, gate insulating film 11, insulating film 11, and gate insulating film 12 is formed by the same manufacturing process. The interlayer insulating film 10 is formed with a large thickness of, for example, about 2000 to 3000 [Å]. Each of the gate insulating film 11 and the insulating film 11 is formed to a thickness of, for example, about 300 to 400 [Å]. The gate insulating film 12 is formed with a thickness of, for example, about 250 [Å]. The interlayer insulating film 10 on the surface of the plate electrode 9 is preferably thick because it basically insulates the plate electrode 9 from the word line 13 extending thereover. Formed with a thin film thickness,
Manufacturing steps may be reduced.

Next, on the interlayer insulating film 10, the gate insulating film 1
A second-layer gate electrode layer 13 is deposited on the entire surface of the substrate including the first, the insulating film 11 and the gate insulating film 12. The second gate electrode layer 13 is formed of, for example, a polycrystalline silicon film deposited by CVD. An n-type impurity is introduced into this polycrystalline silicon film in the same manner as in the first gate electrode layer 9.

Next, the first patterning is performed on the second-layer gate electrode layer 13 in each of the memory cell FM formation region of the EEPROM and the memory cell EM formation region of the EPROM. This patterning is performed by patterning the second-layer gate electrode layer 13 and sequentially patterning (overlapping) each of the interlayer insulating film 11 and the floating gate electrode 9 using the same mask. By this patterning, the control gate electrode 13 of the field effect transistor Qf and the shunt wiring 13 of the MISFET Qfs for selecting a memory cell can be formed in the memory cell FM formation region of the EEPROM. Further, the control gate electrode 13 of the field effect transistor can be formed in the memory cell EM formation region of the EPROM. The patterning is performed using anisotropic etching such as RIE. In the memory cell FM of the EEPROM, the field effect transistor Qf and the memory cell selecting MISFET Qf
By forming each of s with a two-layer gate structure in which each of s is overlapped and cut, the dimension between the gate electrodes can be defined by the processing accuracy of the mask without adding the margin for mask alignment in the manufacturing process to the dimension between the respective gate electrodes. Therefore, the area occupied by the memory cell FM can be reduced.

Next, in each of the memory cell DM forming region of the DRAM, the n-channel MISFET Qn ₂ forming region and the p-channel MISFET Qp ₂ forming region of the CMOS, the second patterning is performed on the second-layer gate electrode layer 13. Is applied. By performing this patterning, as shown in FIGS. 7A and 7B, the MISFET Qds for selecting the memory cell of the memory cell DM, the n-channel MISFET Qn ₂ , and the p-channel MISFET Q
it is possible to form the gate electrode 13 of each of the p _2.
The patterning is performed using, for example, anisotropic etching such as RIE.

Next, an oxidation process is performed on the entire surface of the substrate to form an insulating film 14 covering the surfaces of the gate electrodes 9 and 13, the floating gate electrode 9, and the control gate electrode 13.
The insulating film 14 is formed in order to increase the thickness of each of the gate insulating films 6 and 12 at the ends of the respective gate electrodes 9 and 13 and to improve the withstand voltage.

Next, a memory cell selecting MISFET Qds forming region of the DRAM memory cell DM, an EEPROM
Memory cell FM formation region, CMOS n-channel MI
In each of the SFET Qn ₁ and Qn ₂ formation regions, an n-type semiconductor region 15 is formed on the main surface of the semiconductor substrate 1. The semiconductor region 15 can be formed, for example, by introducing P of about 10 ¹³ [atoms / cm ² ] by ion implantation with energy of about 50 to 80 [KeV].

Next, the CMOS p-channel MISF
In the ETQp ₁ and Qp ₂ forming regions, a p-type semiconductor region 17 is formed on the main surface of the well region 2. Semiconductor region 17
For example, B of about 10 ¹³ [atoms / cm ² ]
It can be formed by ion implantation with energy of about 20 [KeV].

Next, as shown in FIGS. 8A and 8B, in the memory cell EM formation region of the EPROM,
An n-type semiconductor region 16 having a higher impurity concentration than the n-type semiconductor region 15 is formed on the main surface of the semiconductor substrate 1. The semiconductor region 16 is configured to increase the amount of hot carriers mainly by increasing the electric field intensity near the drain region. The semiconductor region 16 has, for example, 10 ¹⁵ [atoms]
/ Cm ² ] can be formed by ion implantation at an energy of about 60 to 100 [KeV].

The semiconductor regions 15, 16 and 17 for forming these LDD structures are respectively provided with gate electrodes 9 and 1
3, self-aligned with any of the floating gate electrode 9 and the control gate electrode 13. Each of the semiconductor regions 15, 16 and 17 may be formed in a different order, or may be formed before the insulating film 14 is formed.

Next, a sidewall spacer 18 is formed on each side wall of each of the gate electrodes 9 and 13, the floating gate electrode 9, and the control gate electrode 13.
The sidewall spacers 18 can be formed, for example, by performing anisotropic etching such as RIE on a silicon oxide film deposited by CVD.

Next, a memory cell selecting MISFET Qds forming region of a DRAM memory cell DM, an EEPROM
Memory cell FM formation area, EPROM memory cell E
M formation region, CMOS n-channel MISFETQ
In the n ₁ and Qn ₂ formation regions, an n + type semiconductor region 19 is formed on the main surface of the semiconductor substrate 1. The semiconductor region 19 is formed, for example, by applying As of about 10 ¹⁶ [atoms / cm ² ] to 60 to
It can be formed by ion implantation with energy of about 100 [KeV]. Semiconductor region 1
9 is formed in a self-aligned manner with respect to the respective gate electrodes 9, 13 floating gate electrode 9 and control gate electrode 13. By the step of forming the semiconductor region 19, the MISFET for selecting the memory cell of the memory cell DM
Qds, the field effect transistor Qf of the memory cell FM,
MISFET Qfs for memory cell selection, memory cell EM
Field effect transistor, n channel MISFET Qn
₁ and Qn ₂ are completed.

Next, as shown in FIGS. 9A and 9B, CMOS p-channel MISFETs Qp ₁ and Qp ₂
In each of the formation regions, p is added to the main surface of the well region 2.
A + type semiconductor region 20 is formed. In the semiconductor region 20, for example, B of about 10 ¹⁵ [atoms / cm ² ]
It can be formed by ion implantation with energy of about [KeV]. This semiconductor region 20
Forming the p-channel MISFET Qp
₁ and Qp ₂ are completed.

Next, an interlayer insulating film 21 and a connection hole 22 are sequentially formed, and a wiring 23 is formed as shown in FIGS. 1A and 1B. The interlayer insulating film 21 is, for example, B
It is formed of a PSG film or a single layer of the PSG film, or a composite film mainly composed of the PSG film.

Thereafter, a final passivation film (not shown) is formed on the entire surface of the substrate, thereby completing the semiconductor integrated circuit device of Example I.

As described above, a memory cell (dynamic storage element) D of a DRAM having an information storage capacitor C is provided.
In a method for manufacturing a semiconductor integrated circuit device having an EEPROM memory cell (non-volatile storage element) FM having an M and a tunnel insulating film 8, a dielectric film 8 of an information storage capacitive element C of the memory cell DM is formed. And the step of forming the tunnel insulating film 8 of the memory cell FM in the same manufacturing step, the tunnel insulating film 8 can be formed in the step of forming the dielectric film 8.
The manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the tunnel insulating film 8.

Further, the DR having the information storage capacitive element C
E having an AM memory cell DM and a tunnel insulating film 8
In a method of manufacturing a semiconductor integrated circuit device including a memory cell FM of an EPROM, a step of forming a semiconductor region 7 for forming a lower electrode of an information storage capacitor C of the memory cell DM; The step of forming the semiconductor region 7 of the transistor Qf is performed in the same manufacturing process. Thereafter, the step of forming the dielectric film 8 of the information storage capacitor C and the step of forming the tunnel insulating film 8 of the field effect transistor Qf are performed. The step of forming the semiconductor region 7 of the information storage capacitor C and the step of forming the dielectric film 8 form the tunnel insulating film 8 in the step of forming the semiconductor region 7 of the information storage capacitor C and the dielectric film 8. Therefore, the manufacturing process of the semiconductor integrated circuit device is reduced by the amount corresponding to the process of forming the semiconductor region 7 and the tunnel insulating film 8. It is possible.

A DR having an information storage capacitive element C
AM memory cell DM and floating gate electrode 9
Memory cell FM (or EP
In a method for manufacturing a semiconductor integrated circuit device including a memory cell EM (ROM), a step of forming a plate electrode (upper electrode) 9 of an information storage capacitor C of the memory cell DM; Memory cell EM)
And the step of forming the floating gate electrode 9 in the same manufacturing process,
Since the floating gate electrode 9 can be formed in the step of forming the plate electrode 9, the manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the floating gate electrode 9.

Further, a memory cell DM of a DRAM having an information storage capacitor C and a MISFET Qds for selecting a memory cell, and a memory cell FM of an EEPROM having a floating gate electrode 9 and a control gate electrode 13 (or a memory cell EM of an EPROM). Forming a data storage capacitor C plate electrode (upper electrode) 9 of the memory cell DM, and a floating gate of the memory cell FM (and / or the memory cell EM). The step of forming the electrode 9 is performed in the same manufacturing step, and the memory cell D
Gate electrode 1 of M memory cell selection MISFET Qds
3 and the step of forming the control gate electrode 13 of the memory cell FM (or the memory cell EM) are performed in the same manufacturing step, whereby the plate electrode 9 of the information storage capacitor C and the memory cell MI for selection
Since the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM can be formed in the step of forming the gate electrode 13 of the SFET Qds, the floating gate electrode 9 and the control gate electrode 13 can be formed.
Can be reduced by the amount corresponding to the step of forming the semiconductor integrated circuit device.

Further, the memory cells DM and E of the DRAM
In a method of manufacturing a semiconductor integrated circuit device having a memory cell FM of an EPROM, a semiconductor region 7, a dielectric film 8, a plate electrode 9, and a gate electrode 13 of a MISFET Qds for selecting a memory cell of the memory cell DM. Forming the semiconductor region 7, the tunnel insulating film 8, the floating gate electrode 9, and the control gate electrode 13 of the memory cell FM in the same manufacturing process. In the process of forming each of the DM semiconductor region 7, the dielectric film 8, the plate electrode 9, and the gate electrode 13, the semiconductor region 7, the tunnel insulating film 8, the floating gate electrode 9, and the control gate electrode 13 of the memory cell FM are formed. Since each of them can be formed, a corresponding amount of semiconductor integrated circuit device It is possible to further reduce the granulation step.

(Embodiment II) The present embodiment II is directed to the semiconductor integrated circuit device of the above-described embodiment I in which the DRAM
The plate electrode of the information storage capacitance element of the memory cell is formed of the gate electrode material of the second layer, and the memory cell selection M
This is a second embodiment of the present invention in which a gate electrode of an ISFET is formed of a first-layer gate electrode material.

A semiconductor integrated circuit device incorporating a microcomputer according to Embodiment II of the present invention is shown in FIG. 10 (a cross-sectional view of a principal part showing each element). Embodiment II is DRA
FIG. 10 shows a memory cell DM of a DRAM, a memory cell FM of an EEPOM, and an EPROM since the other element structures except the M memory cell are the same as those of the first embodiment.
Of the memory cell EM of FIG.

As shown in FIG. 10, D of the semiconductor integrated circuit is
The memory cell DM of the RAM is a memory cell selecting MISF.
It is composed of a series circuit of ETQds and an information storage capacitor C.

The information storage capacitive element C of the memory cell DM has a planar structure in which an n-type semiconductor region (lower electrode) 7, a dielectric film 8, and a plate electrode (upper electrode) 13 are sequentially stacked. ing. The plate electrode 13 is the second
It is formed of the gate electrode material of the layer. Dielectric film 8
Is formed with a thin film thickness similarly to the tunnel insulating film 8 of the field effect transistor Qf of the memory cell FM of the EEPROM.

The memory cell selecting MISFET Qds is
The semiconductor device includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19 serving as a source region and a drain region. The gate electrode 9 is formed of a first-layer gate electrode material.

Next, a method of manufacturing the semiconductor integrated circuit device will be briefly described with reference to FIGS. 11 to 13 (cross-sectional views showing main parts in respective manufacturing steps).

First, as in the first embodiment, a well region 2 is formed in a semiconductor substrate 1, and then a field insulating film 3 and a p-type channel stopper region 4 are sequentially formed.

Next, in the semiconductor element formation region, a gate insulating film 6A is formed on each main surface of the semiconductor substrate 1 and the well region 2.

Next, the area for forming the information storage capacitor C of the memory cell DM of the DRAM and the memory cell F of the EEPROM
An n-type semiconductor region 7 is formed on the main surface of each semiconductor substrate 1 in the M field effect transistor Qf formation region.

Next, in the field effect transistor Qf forming region of the memory cell FM of the EEPROM, a part of the gate insulating film 6A on the semiconductor region 7 is removed, and a tunnel is formed in the removed region as shown in FIG. An insulating film 8 is formed. Through the step of forming the tunnel insulating film 8, the gate insulating film 6A in other regions is grown on the gate insulating film 6. Unlike the embodiment I, the embodiment II is
The dielectric film 8 of the information storage capacitor C is formed by a process different from the process of forming the tunnel insulating film 8.

Next, a first-layer gate electrode layer 9 is formed on the entire surface of the substrate including the gate insulating film 6 and the tunnel insulating film 8. Then, the first gate electrode layer 9 is subjected to predetermined patterning to form the gate electrode 9 and the floating gate electrode 9. The gate electrode 9 is formed on each of the gate insulating films 6 in the memory cell selecting MISFET Qds forming region of the DRAM memory cell DM and the memory cell selecting MISFET Qfs forming region of the EEPROM memory cell FM. The floating gate electrode 9
Field effect transistor Q of EPROM memory cell FM
f on the gate insulating film 6 and the tunnel insulating film 8, EPRO
It is formed on each of the M memory cells EM on the gate insulating film 6. Although not shown, the gate electrode 9 includes a CMOS n-channel MISFET Qn ₁ forming region of a peripheral circuit,
It is also formed on each gate insulating film 6 in the p-channel MISFET Qp ₁ formation region.

Next, an insulating film 11A is formed on each surface of the gate electrode 9 and the floating gate electrode 9.
The insulating film 11A is formed of a silicon oxide film in which the respective surfaces of the gate electrode 9 and the floating gate electrode 9 are oxidized. Although not shown, the p-channel MISFET Qp on the main surface of the semiconductor substrate 1 in the n-channel MISFET Qn ₂ formation region of the peripheral circuit is formed by the step of forming the insulating film 11A.
_A gate insulating film used as a part of the gate insulating film (12) is formed on each of the main surfaces of the well region _{2 in the} formation region ₂ .

Next, as shown in FIG. 12, the gate insulating film 6 in the region for forming the information storage capacitor C of the memory cell DM of the DRAM is selectively removed, and the main surface of the semiconductor region 7 is exposed.

Next, a dielectric film 8 is formed on the main surface of the exposed semiconductor region 7. The dielectric film 8 is formed of, for example, a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1. The dielectric film 8 is formed in a step different from that of the tunnel insulating film 8, but is formed with a substantially similar thin film thickness. The step of forming the dielectric film 8 allows the insulating film 11 to be formed.
A is grown, and an insulating film 11 is formed on the surface of the gate electrode 9, and a gate insulating film 11 is formed on the surface of the floating gate electrode 9.
Can be formed. Further, a CMOS n-channel MISFET Qn ₂ forming region of a peripheral circuit, a p-channel M
The gate insulating film 12 can be formed by growing the gate insulating film in each of the ISFET Qp ₂ formation regions.

Next, a second gate electrode layer 13 is formed on the entire surface of the substrate including the dielectric film 8, the gate insulating film 11 (and the gate insulating film 12 not shown), and the like. And
The second gate electrode layer 13 is subjected to patterning twice, and as shown in FIG. 13, each of the plate electrode 13, the control gate electrode 13, the shunt wiring 13 (and the gate electrode 13 of the peripheral circuit) is formed. To form

Thereafter, as in the first embodiment, the insulating film 14, the semiconductor regions 15, 16, 17, the sidewall spacers 18, the semiconductor regions 19, 20, the interlayer insulating film 2 are formed.
1. The semiconductor integrated circuit device of Embodiment II is completed by sequentially forming each of the connection hole 22, the wiring 23, and the like.

The semiconductor integrated circuit device configured as described above has the following effects in addition to the effects of the first embodiment.

In the method of manufacturing a semiconductor integrated circuit device provided with a memory cell DM of a DRAM having an information storage capacitive element C and a memory cell FM of an EEPROM having a control gate electrode 13 (or a memory cell EM of an EPOM), Forming a plate electrode (upper electrode) 13 of the information storage capacitor C of the memory cell DM;
The step of forming the control gate electrode 13 of the memory cell FM (or the memory cell EM) and the step of forming the plate electrode 13 of the information storage capacitor C are performed in the same manufacturing process. Can be formed, so that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced corresponding to the step of forming the control gate electrode 13.

A memory cell DM of a DRAM having an information storage capacitor C and a MISFET Qds for selecting a memory cell and a memory cell FM of an EEPROM having a floating gate electrode 9 and a control gate electrode 13 (or a memory cell EM of an EPROM). Forming a floating gate electrode 9 of the memory cell FM, and a MISFE for selecting a memory cell of the memory cell DM.
The step of forming the gate electrode 9 of TQds is performed in the same manufacturing process to form the control gate electrode 13 of the memory cell FM and the plate electrode 13 of the information storage capacitor C of the memory cell DM. In the step of forming the gate electrode 9 of the memory cell selecting MISFET Qds and the plate electrode 13 of the information storage capacitance element C, the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM are formed in the same manufacturing process. Can be formed, so that the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the floating gate electrode 9 and the control gate electrode 13.

Further, the memory cells DM and E of the DRAM
In a method of manufacturing a semiconductor integrated circuit device having a memory cell FM of an EPROM, a semiconductor region 7, a plate electrode 13, and a gate electrode 9 of a MISFET Qds for selecting a memory cell are formed respectively in the memory cell DM. The step of forming the semiconductor region 7, the control gate electrode 13, and the floating gate electrode 9 of the memory cell FM is performed in the same manufacturing step, thereby forming the semiconductor region 7, the plate electrode 13, Since the semiconductor region 7, the control gate electrode 13, and the floating gate electrode 9 of the memory cell FM can be formed in the step of forming each of the gate electrodes 9, the manufacturing process of the semiconductor integrated circuit device is correspondingly reduced. It can be further reduced.

(Embodiment III) This embodiment is a third embodiment of the present invention in which the semiconductor element has a one-layer gate structure in the semiconductor integrated circuit device of Embodiment I.

FIG. 14 shows a semiconductor integrated circuit device incorporating a microcomputer according to Embodiment III of the present invention.
(A) and FIG. 14 (b) (a cross-sectional view of a main part showing each element).

As shown in FIGS. 14A and 14B, the information storage capacitor C of the memory cell DM of the DRAM is used.
Has a planar structure in which an n-type semiconductor region (lower electrode) 7, a dielectric film 8, and a plate electrode (upper electrode) 9 are sequentially stacked. The plate electrode 9 is formed of a first-layer gate electrode material. The dielectric film 8 is formed with a small thickness as in the first embodiment.

The memory cell selection MISFET Qds is
Semiconductor substrate 1, gate insulating film 6, gate electrode 9, a pair of n-type semiconductor regions 15 serving as a source region and a drain region
And a pair of n + -type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material. That is, the memory cell DM of the DRAM has a single-layer gate structure.

The memory cell FM of the EEPROM is shown in FIG.
(A) and FIG. 14 (b) do not show a cross-sectional structure, but as shown in FIG. 17 (a plan view of the memory cell), a field-effect transistor Qf and a memory cell selecting MISFET are shown.
It is composed of a series circuit with Qfs.

The field-effect transistor Qf includes a semiconductor substrate 1, an n-type semiconductor region 7, a gate insulating film (first gate insulating film) 6, a tunnel insulating film 8, a floating gate electrode 9, and a gate insulating film (second gate insulating film). 6.) 6, a control gate electrode 7A, a pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19, which are source and drain regions. The floating gate electrode 9 is formed of a first-layer gate electrode material. The floating gate electrode 9 is provided so as to extend in the gate width direction to a position above the control gate electrode 7A formed of an n-type semiconductor region. A gate insulating film (second gate insulating film) 6 is provided between the floating gate electrode 9 and the control gate electrode 7A. The control gate electrode (semiconductor region) 7A is formed in the same manufacturing process as the semiconductor region 7. The control gate electrode 7A is connected to a wiring 23 used as a word line WL through a connection hole 22.
It is connected to the.

The memory cell selection MISFET Qfs is
As shown in FIG. 17, the semiconductor substrate 1, the gate insulating film 6,
A pair of n-type semiconductor regions 15 and a pair of n + -type semiconductor regions 19, which are a gate electrode 9, a source region and a drain region,
It is composed of The gate electrode 9 is made of a first-layer gate electrode material. This gate electrode 9 is formed integrally with the word line (WL) 9. The memory cell selecting MISFET Qfs has substantially the same structure as the memory cell selecting MISFET Qds of the DRAM memory cell DM and the n-channel MISFET Qn of the peripheral circuit. That is, the memory cell FM of the EEPROM
Field effect transistor Qf, memory cell selecting MIS
Each of the FETs Qfs has a single-layer gate structure.

The memory cell EM of the EPROM is EE
Field effect transistor Qf of memory cell FM of PROM
It has a similar structure. That is, the memory cell EM
Denotes a semiconductor substrate 1, a gate insulating film (first gate insulating film)
6, floating gate electrode 9, gate insulating film (second
A gate insulating film) 6 and a control gate electrode (n-type semiconductor region) 7A. This memory cell (field effect transistor) EM has a single-layer gate structure.

CMOS n-channel MISF for peripheral circuits
The ETQn includes a semiconductor substrate 1, a gate insulating film 12, a gate electrode 9, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n + -type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material.

The p-channel MISFET Qp includes a well region 2, a gate insulating film 12, a gate electrode 9, a pair of p-type semiconductor regions 17 as a source region and a drain region, and a pair of p + -type semiconductor regions 20. The gate electrode 9 is formed of a first-layer gate electrode material. That is, each of the CMOS n-channel MISFET Qn and p-channel MISFET Qp has a single-layer gate structure.

Next, a method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 15 (a) and 15 (b) and FIGS.
This will be briefly described with reference to (a) and FIG. 16 (b) (a cross-sectional view of a main part for each manufacturing process).

First, as in the first embodiment, a well region 2 is formed on the main surface of a semiconductor substrate 1, and thereafter, a field insulating film 3 and a p-type channel stopper region 4 are formed.

Next, in the semiconductor element formation region, an insulating film 6A used as a part of the gate insulating film is formed on each of the main surfaces of the semiconductor substrate 1 and the well region 2.

Next, the CMOS n channel M of the peripheral circuit
ISFET Qn formation region, p-channel MISFET Qp
In each of the formation regions, the insulating film 6A is selectively removed.

Next, the n-channel MISFET Qn formation region and the p-channel MISF from which the insulating film 6A has been removed.
In each of the ETQp formation regions, a new gate insulating film 12 is formed on each main surface of the semiconductor substrate 1 and the well region 2. By the step of forming the gate insulating film 12, the insulating film 6A is grown, and the gate insulating film 6 is formed on each of the main surfaces of the semiconductor substrate 1 and the well region 2.

Next, as shown in FIGS. 15A and 15B, the area for forming the information storage capacitor C of the memory cell DM of the DRAM, the field-effect transistor Qf of the memory cell FM of the EEPROM, and the memory cell MISFE for selection
In each of the TQfs forming region and the EPROM memory cell EM forming region, an n-type semiconductor region 7 and a control gate electrode 7A are formed on the main surface of the semiconductor substrate 1. Each of the semiconductor region 7 and the control gate electrode 7A can be formed by introducing an n-type impurity by ion implantation.

Next, the area for forming the information storage capacitor C of the memory cell DM of the DRAM and the memory cell F of the EEPROM
The gate insulating film 6 is selectively removed in each of the formation regions of the M field-effect transistors Qf. Then, a dielectric film 8 and a tunnel insulating film 8 are formed on the removed main surface of the semiconductor substrate 1.

Next, a first-layer gate electrode layer 9 is formed on the entire surface of the substrate including the gate insulating films 6 and 12, the dielectric film 8, and the tunnel insulating film 8, respectively. Thereafter, by performing predetermined patterning on the first-layer gate electrode layer 9, as shown in FIGS. 16A and 16B,
Each of the plate electrode 9 and the gate electrode 9 can form the floating gate electrode 9. The plate electrode 9 forms the upper electrode of the information storage capacitor C of the memory cell DM of the DRAM. The gate electrode 9 is connected to the memory cell D
MISFET Qds for memory cell selection of M, EEPRO
MISFET Q for selecting memory cell of M memory cell FM
fs, CMOS MISFETs Qn and Qp of peripheral circuits
The respective gate electrodes are formed. The floating gate electrode 9 forms the respective floating gate electrodes of the field effect transistor Qf of the memory cell FM and the memory cell EM of the EPROM.

Next, as in the first embodiment, the semiconductor regions 15, 16, 17, the sidewall spacers 18,
Semiconductor regions 19 and 20, interlayer insulating film 21, connection hole 22,
By sequentially forming each of the wirings 23, the above-described FIG.
As shown in FIG. 4A and FIG. 14B, the semiconductor integrated circuit device is completed.

The semiconductor integrated circuit device configured as described above has the following effects in addition to the effects of the first embodiment.

Memory cells DM and EEPRO of DRAM
In a method of manufacturing a semiconductor integrated circuit device including M memory cells FM (or EPROM memory cell EM), an n-type semiconductor region (lower electrode) 7 of an information storage capacitor C of the memory cell DM is formed. The step of forming the n-type semiconductor region 7 and the control gate electrode (n-type semiconductor region) 7A of the memory cell FM is performed in the same manufacturing step, so that the semiconductor region 7 of the information storage capacitor C is formed. In the forming process, the semiconductor region 7 and the control gate electrode 7A of the memory cell FM can be formed. Therefore, the manufacturing process of the semiconductor integrated circuit device corresponds to the process of forming the semiconductor region 7 and the control gate electrode 7A. Can be reduced.

Further, the memory cells DM and EE of the DRAM
In a method of manufacturing a semiconductor integrated circuit device provided with a memory cell FM of a PROM (or a memory cell EM of an EPROM), an information storage capacitor C plate electrode (upper electrode) 9 and a memory cell selecting MIS of the memory cell DM are provided.
By performing the same manufacturing process as the step of forming the gate electrode 9 of the FET Qds and the step of forming the floating gate electrode 9 of the field effect transistor Qf of the memory cell FM, the plate electrode 9 of the information storage capacitor C is formed. In addition, in the step of forming the gate electrode 9 of the memory cell selecting MISFET Qds, the floating gate electrode 9 of the memory cell FM can be formed. Therefore, the semiconductor integrated circuit device corresponds to the step of forming the floating gate electrode 9. Manufacturing process can be reduced.

Since the semiconductor integrated circuit device has a single-layer gate structure, the number of conductive layers is small, and the manufacturing process of the semiconductor integrated circuit device can be simplified.

(Embodiment IV) The present embodiment IV is directed to the semiconductor integrated circuit device of the above-described embodiment I, in which the DRAM
14 is a fourth embodiment of the present invention in which the information storage capacitance element of the memory cell is configured in a stacked structure.

A semiconductor integrated circuit device incorporating a microcomputer according to Embodiment IV of the present invention is shown in FIG. 18 (a cross-sectional view of a principal part showing each element).

As shown in FIG. 18, the memory cell DM of the DRAM is composed of a series circuit of a MISFET Qds for memory cell selection and an information storage capacitor C having a stacked structure.

The memory cell selecting MISFET Qds is
As in the case of Embodiment III, the gate electrode 9 is formed of a gate electrode 9 formed of a first-layer gate electrode material.

The information storage capacitive element C is constituted by sequentially superposing a plate electrode (lower electrode) 13, a dielectric film 26, and a plate electrode 27 on each other. Plate electrode 1
3 is a data line 2 of the memory cell selecting MISFET Qds.
3 is connected to the semiconductor region 19 on the side not connected. This connection is made through connection holes 25 formed in the interlayer insulating film 24 and defined by the sidewall spacers 18. The plate electrode 13 is formed of a second-layer gate electrode material, for example, a polycrystalline silicon film. The dielectric film 26 is formed by a single layer of a silicon oxide film, a silicon nitride film, a tantalum oxide film, or a composite film thereof formed by an insulating film forming method such as CVD or sputtering. The plate electrode 27 is formed of a third-layer gate electrode material, for example, a polycrystalline silicon film. The second-layer gate electrode material;
Although not shown, each of the gate electrode materials of the layer is used as a wiring or a resistance element in another region.

Memory cells FM and EPRO of EEPROM
Each of the M memory cells EM and the CMOS (not shown) of the peripheral circuit has a single-layer gate structure, as in Embodiment III.

Although the manufacturing method of the semiconductor integrated circuit device of the present embodiment is omitted, basically, after forming a semiconductor element having a single-layer gate structure such as a memory cell selecting MISFET Qds of a DRAM memory cell DM, Memory cell DM
Is formed.

The semiconductor integrated circuit device configured as described above can provide the same effects as those of the first embodiment.

As described above, the invention made by the present inventor has been specifically described based on the above embodiment.
It is needless to say that the present invention is not limited to the above-described embodiment, but may be variously modified without departing from the gist thereof.

For example, according to the present invention, the memory cell of the EEPROM has a one-transistor structure (the field-effect transistor Qf).
Only).

[0147] Further, the present invention is that the memory cells of the EEPROM MNOS (M etal N itride O xide S emiconducto
r) It may be composed of a field effect transistor having a structure.

[0148]

The effects which can be obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.

[0149] In the semiconductor integrated circuit device in which example Bei dynamic memory element, the balance between performance and manufacturing cost
The semiconductor integrated circuit device according to the present invention can be provided .

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device incorporating a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 3 is a fragmentary cross-sectional view showing a step of each manufacturing step of the semiconductor integrated circuit.

FIG. 4 is a fragmentary cross-sectional view showing a step of each manufacturing step of the semiconductor integrated circuit.

FIG. 5 is a cross-sectional view of a main part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 6 is a cross-sectional view of a main part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 7 is a cross-sectional view of a main part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 8 is a cross-sectional view of a main part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 9 is a cross-sectional view of a main part showing each manufacturing step of the semiconductor integrated circuit.

FIG. 10 is a sectional view of a main part of a semiconductor integrated circuit device incorporating a microcomputer according to Embodiment II of the present invention;

FIG. 11 is a fragmentary cross-sectional view showing a step of each manufacturing step of the semiconductor integrated circuit device.

FIG. 12 is an essential part cross sectional view showing the manufacturing step of the semiconductor integrated circuit device;

FIG. 13 is a fragmentary cross-sectional view showing a step of each manufacturing step of the semiconductor integrated circuit device.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor integrated circuit device incorporating a microcomputer according to Embodiment III of the present invention;

FIG. 15 is a fragmentary cross-sectional view showing a step of each manufacturing step of the semiconductor integrated circuit device.

FIG. 16 is a fragmentary cross-sectional view showing a step of each manufacturing step of the semiconductor integrated circuit device.

FIG. 17 is a plan view showing a memory cell of an EEPROM of the semiconductor integrated circuit.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor integrated circuit device incorporating a microcomputer according to Embodiment IV of the present invention;

[Explanation of symbols]

DM, FM, EM: memory cell, Qds, Qfs: MISFET for selecting memory cell, C: capacitor for storing information,
Qf: electric field transistor, Qn, Qp: MISFET,
6, 11, 12 ... gate insulating film, 7, 15, 16, 1
7, 19, 20: semiconductor region, 8: dielectric film, tunnel insulating film, 9: gate electrode, plate electrode, floating gate electrode, 13: gate electrode, control gate electrode.

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 27/115 29/788 29/792 (56) References JP-A-57-172761 (JP, A) JP-A-52-129383 (JP, A) JP-A-55-83251 (JP, A) JP-A-56-120166 (JP, A) JP-A-59-61072 (JP, A) JP-A-63-29969 (JP, A) -151361 (JP, A) JP-A-56-2666 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/8238 H01L 21/8242 H01L 21/8247 H01L 27/092 H01L 27/115 H01L 29/788 H01L 29/792

Claims (9)

(57) [Claims] 1. A dynamic storage element having an information storage capacitance element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in a peripheral circuit thereof.
A semiconductor memory device comprising: a first memory;
The thickness of the gate insulating film of the computing-gate storage elements is substantially identical to the insulating film of the memory cell selecting MISFET, the thickness of the gate insulating film of the second floating gate type memory device for selecting said memory cell Absolute MISFET
A semiconductor memory device characterized by being thinner than an edge film . 2. The semiconductor memory device according to claim 1,
Thus, the floating gate type storage element is
The semiconductor memory which is a memory element using a flow
apparatus. 3. A dynamic storage element having an information storage capacitance element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in a peripheral circuit thereof.
A method for manufacturing a semiconductor memory device comprising a storage element, comprising: a gate insulating film of a first floating gate type storage element;
Forming a gate electrode after forming said memory cell selecting MISFET and a second Floating
Forming a gate insulating film and a gate electrode of the memory gate type storage element, and a thickness of the gate insulating film of the memory cell selecting MISFET.
The gate of the first floating gate type storage element is
A method for manufacturing a semiconductor memory device, wherein the thickness is larger than the thickness of the insulating film . 4. The manufacturing of the semiconductor memory device according to claim 3.
The method, wherein the memory cell selecting MISFET and a
Gate insulating film with 2 floating gate type storage elements
And forming a gate electrode at the same time . 5. A dynamic storage element having an information storage capacity element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in peripheral circuits thereof.
A method for manufacturing a semiconductor memory device comprising a storage element, comprising: a gate insulating film of a first floating gate type storage element;
Forming the memory cell selecting MISFET and the second floating transistor.
For forming a gate insulating film with a floating gate type storage element
And the first floating gate type storage element and the memory
MISFET for selecting recell and second floating gate
Method of manufacturing a semiconductor memory device characterized by a step of forming a gate electrode of the preparative storage element. 6. A dynamic storage element having an information storage capacity element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in a peripheral circuit thereof.
A method of manufacturing a semiconductor memory device and a憶素Ko, the gate insulating film of the memory cell selecting MISFET and
It includes a step of sequentially forming a gate electrode, and forming a gate electrode with a gate insulating film of the first floating gate storage element after the formation of thicker than the gate insulating film of the memory cell selecting MISFET, the memory A gate insulating film of a MISFET for cell selection and
Forming a second floating gate by forming a gate electrode ;
A method for manufacturing a semiconductor storage device, comprising forming a gate insulating film and a gate electrode of a gating type storage element . 7. A dynamic storage element having an information storage capacitance element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in peripheral circuits thereof.
A method of manufacturing a semiconductor memory device having a memory element , wherein a gate insulating film of the memory cell selecting MISFET is formed.
Forming a gate insulating film of a first floating gate type storage element
From the gate insulating film of the memory cell selecting MISFET.
Forming the memory cell selecting MISFET and the first floating layer.
Gate type storage element, second floating gate type
Forming a gate electrode of the memory element, forming a gate insulating film of the memory cell selecting MISFET.
Forming the second floating gate type
A method for manufacturing a semiconductor storage device, comprising forming a gate insulating film of a storage element . 8. A dynamic storage element having an information storage capacitance element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in a peripheral circuit thereof.
A method of manufacturing a semiconductor memory device including a憶素Ko, sequentially forming a gate insulating film and a gate electrode of said memory cell selecting MISFET, the gate insulating film of the first floating-gate storage elements wherein and forming a gate electrode after forming thinner than the gate insulating film of the memory cell selecting MISFET, the second flow by forming a gate insulating film and a gate electrode of said memory cell selecting MISFET Tin
A method for manufacturing a semiconductor storage device, comprising forming a gate insulating film and a gate electrode of a gating type storage element . 9. A dynamic storage element having an information storage capacitance element and a memory cell selection MISFET, and a plurality of floating gate type storage elements formed in a peripheral circuit thereof.
A method of manufacturing a semiconductor memory device including a憶素Ko, forming a gate insulating film of the memory cell selecting MISFET, for the memory cell select gate insulating film of the first floating gate storage element a step of thinner than the gate insulating film of MISFET, said memory cell selecting MISFET, first Floating
Gate type storage element, second floating gate type
Forming a gate electrode of a storage element , and forming a gate insulating film of the memory cell selecting MISFET by the second floating gate.
A method for manufacturing a semiconductor memory device, comprising forming a gate insulating film of a type memory element .