JP2605082B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a dynamic random access memory and a nonvolatile memory. It is.

[Conventional technology]

A semiconductor integrated circuit device incorporating a microcomputer has a RAM ( R andom) as a storage unit of the microcomputer.
And a A ccess Memory) and ROM (R ead O nly M emory ). The RAM is mounted S (S Tatic) RAM, the memory cell (memory element) of the six ROSFET (sixth MOS
Configuration). Mask ROM, EP as ROM
(E rasable P rogrammable) ROM or EEP (E lectrical
ly E rasable P rogrammable) ROM is mounted. E
EPROM is FLOTOX (Floating Gate T unnel O xide ) memory cell structures are used.

In the semiconductor integrated circuit device configured as described above, since the memory cells of the SRAM used as the RAM are configured with the 6MOS structure, the memory cell area increases and the degree of integration decreases. Therefore, there is a proposal to use a D (Dynamic) RAM instead of the SRAM as the RAM of this type of semiconductor integrated circuit device. For example,
Published by Nikkei McGraw-Hill, Nikkei Micro Device, 1987
July, pp. 71-73. The DRAM of the proposed semiconductor integrated circuit device uses a memory cell for selecting a memory cell.
It consists of a series circuit of an SFET and an information storage capacitor. The information storage capacitor has a so-called planar structure in which an n-type semiconductor region (lower electrode), a dielectric film, and a plate electrode (upper electrode) formed on the main surface of the semiconductor substrate are sequentially stacked.

This semiconductor integrated circuit device has a feature that since the number of elements of the DRAM memory cell is small, the memory cell area can be reduced and the degree of integration can be improved.

Further, the semiconductor integrated circuit device has a feature that the number of manufacturing steps can be reduced because a DRAM memory cell is formed by using a part of the manufacturing process of the memory cell having the FLOTOX structure of the EEPROM. This semiconductor integrated circuit device has a DRAM, an EEPROM, and MISFETs constituting peripheral circuits as described above, and the method of manufacturing these elements is as follows.

First, a gate insulating film is formed on a main surface portion of a semiconductor substrate in a floating gate electrode formation region of a memory cell having a FLOTOX structure of an EEPROM.

Next, a part of the gate insulating film is removed to form a tunnel silicon oxide film having a smaller thickness than the gate insulating film.

Next, a floating gate electrode is formed on the gate insulating film and the tunnel silicon oxide film.

Next, a gate insulating film is formed on the floating gate electrode. Using this process, the dielectric film (silicon oxide film) of the information storage capacitor element of the memory cell of the DRAM, the peripheral circuit, and the gate insulating film of the MISFET are formed by the same manufacturing process as that process.

Next, a control gate electrode is formed on the floating gate electrode of the memory cell having the FLOTTOX structure with a gate insulating film interposed. Using this process, a plate electrode (upper electrode) is formed on the dielectric film of the information storage capacitor element of the DRAM memory cell and a gate electrode is formed on the gate insulating film of the MISFET of the peripheral circuit by the same manufacturing process as that process. Form.

[Problems to be solved by the invention]

As described above, the dielectric film of the information storage capacitor element has the same manufacturing process as the gate insulating film between the floating gate electrode and the control gate electrode of the FLOTOX structure memory cell and the gate insulating film of the MISFET of the peripheral circuit. Is formed by Since a relatively high voltage necessary for writing, reading, and erasing information is applied to the control gate electrode of the FLOTOX memory cell, the gate insulating film below the control gate electrode is formed with a small thickness. Can not do. Also, since an operating voltage of about 5 [V] is normally applied to the gate electrode of the MISFET of the peripheral circuit,
The gate insulating film below the gate electrode cannot be formed with a small thickness. Therefore, the dielectric film of the information storage capacitor formed in the same manufacturing process as the gate insulating film is formed to have substantially the same thickness as the gate insulating film. Therefore, the amount of charge stored in the information storage capacitor of the memory cell of the DRAM decreases, and the area occupied by the information storage capacitor increases to increase the charge. As a result, RA
Since the area occupied by M increases, the degree of integration of the semiconductor integrated circuit device decreases.

In order to increase the charge amount of the information storage capacitor of the memory cell of the DRAM, a dielectric film is formed in a different manufacturing process from the gate insulating film of the FLOTOX structure and the gate insulating film of the MISFET of the peripheral circuit. There is a need to. Therefore, in order to improve the degree of integration, the number of manufacturing steps of the semiconductor integrated circuit device increases.

An object of the present invention is to provide a semiconductor integrated circuit device having a dynamic memory (DRAM) and a nonvolatile memory,
It is an object of the present invention to provide a technology capable of improving the degree of integration.

Another object of the present invention is to provide a technique capable of achieving the above object by reducing the area of a dynamic memory element and optimizing the characteristics of a nonvolatile memory element and elements of peripheral circuits. Is to do.

Another object of the present invention is to provide a technique capable of reducing the number of manufacturing steps of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

A DRAM section composed of a plurality of dynamic memory elements having information storage capacitance elements in which a dielectric film is interposed on a semiconductor area on which one electrode is formed and the other electrode is formed on a predetermined area of a main surface of a semiconductor substrate The ROM portion composed of a plurality of nonvolatile memory elements in which a floating gate electrode is formed with a tunnel insulating film through which a current flows using a tunnel phenomenon is provided in another predetermined region of the semiconductor substrate main surface. A method for manufacturing a semiconductor integrated circuit device comprising: a step of forming another upper electrode of an information storage capacitive element of a dynamic memory element in the DRAM part on a part of the semiconductor substrate main surface; and And the step of forming the floating gate electrode of the nonvolatile memory element in the above were performed in the same manufacturing process.

[Action]

According to the above-described means, since the floating gate electrode can be formed in the step of forming the upper electrode of the information storage capacitor, the manufacturing of the semiconductor integrated circuit device is equivalent to the step of forming the floating gate electrode. The number of steps can be reduced.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device incorporating a microcomputer.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Example of the invention)

(Embodiment I) A semiconductor integrated circuit device incorporating a microcomputer according to Embodiment I of the present invention is shown in FIG. 1A and FIG. 1B (a cross-sectional view of a principal part showing each element).

As shown in FIGS. 1A and 1B, the semiconductor integrated circuit device includes a single p ^- type semiconductor substrate 1 made of single-crystal silicon. That is, the semiconductor substrate 1 is illustrated separately in FIG. 1A and FIG. 1B for drawing, but is actually configured integrally.

On the main surface of the semiconductor substrate 1, as shown in FIG. 1A, RAM and ROM storage elements constituting the storage of the microcomputer are formed. The RAM is composed of a DRAM, and its memory cell (dynamic storage element) DM is described. The ROM is composed of an EEPROM, an EPROM, and a mask ROM, and describes a memory cell (non-volatile storage element) FM of a FLOTOX structure of the EEPROM and a memory cell (non-volatile storage element) EM of the EPROM, respectively. Since the memory cells of the mask ROM have substantially the same structure as the elements (n-channel MISFETs) shown in FIG. 1B, they are not shown or described here. As shown in FIG. 1B, a complementary MISFET (CMOS) constituting a peripheral circuit is formed on the main surface of the other region of the semiconductor substrate 1. The CMOS is configured by combining n-channel MISFETs Qn ₁ and Qn ₂ and p-channel MISFETs Qp ₁ and Qp ₂ . Each of the p-channel MISFETs Qp ₁ and Qp ₂ is formed on the main surface of the n ⁻ -type well region 2 provided on the main surface of the semiconductor substrate 1.

The semiconductor element formed on the main surface of the semiconductor substrate 1 is electrically separated from other regions by the field insulating film 3 and the p-type channel stopper region 4. The semiconductor element formed on the main surface of the well region 2 is electrically isolated from other regions by the field insulating film 3. Field insulating film 3
Is formed of a silicon oxide film in which the respective main surfaces of the semiconductor substrate 1 and the well region 2 are selectively oxidized. The channel stopper region 4 is located on the main surface of the semiconductor substrate 1 and below the field insulating film 3.

As shown on the left side of FIG. 1A, the memory cell DM of the DRAM includes a series circuit of a MISFET Qds for selecting a memory cell and a capacitance element C for storing information.

The information storage capacitor C is formed by sequentially stacking an n-type semiconductor region (lower electrode) 7, a dielectric film 8, and a plate electrode (upper electrode) 9. The information storage capacitor C has a so-called planar structure (MOS structure).

The semiconductor region 7 is formed on the main surface of the semiconductor substrate 1.

Dielectric film 8 is formed of a silicon oxide film obtained by oxidizing the main surface of semiconductor region 7 (semiconductor substrate 1). The dielectric film 8 is formed to have substantially the same thickness as a tunnel insulating film (silicon oxide film) 8 of a memory cell FM of an EEPROM described later, for example, a thin film having a thickness of about 100 [100]. Each of the dielectric film 8 and the tunnel insulating film 8 is thinner than the respective gate insulating films 6 or 12 of the MISFETs Qds for memory cell selection and the MISFETs Qn ₁ , Qn ₂ , Qp ₁ , and Qp ₂ of the peripheral circuit. Is formed. That is, since the dielectric film 8 of the information storage capacitor C is formed with a small thickness, the amount of charge storage of the information storage capacitor C can be increased and the area of the memory cell DM can be reduced. ing.

The plate electrode 9 is formed on the dielectric film 8. The plate electrode 9 is formed of, for example, a polycrystalline silicon film into which an impurity (P, As or B) for reducing a resistance value is introduced. The plate electrode 9 is formed with a film thickness of, for example, about 3000 to 4000 [Å]. This plate electrode 9 is formed of the first-layer gate electrode material in the manufacturing process.
An interlayer insulating film 10 is provided on the surface of the plate electrode 9.

The MISFET Qds for memory cell selection mainly includes a semiconductor substrate 1, a gate electrode film 12, a gate electrode 13, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n ⁺
It is composed of a type semiconductor region 19. That is, the memory cell selecting MISFET Qds is formed of an n-channel MISFET.

The semiconductor substrate 1 is used as a channel formation region.

Gate insulating film 12 is formed of a silicon oxide film obtained by oxidizing the main surface of semiconductor substrate 1. As described above, the gate insulating film 12 is formed to have a thickness larger than that of the dielectric film 8 of the information storage capacitor C, for example, about 250 [Ｃ].
In other words, the gate insulating film 12 can secure a withstand voltage between the semiconductor substrate 1 and the gate electrode 13 in a normal operation range (for example, when the voltage between the semiconductor substrate 1 and the gate electrode 13 is 5 [V]). It is configured as follows.

The gate electrode 13 is formed on the gate insulating film 12. The gate electrode 13 is formed of, for example, a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. Gate electrode 13
Is formed with a film thickness of, for example, about 3000 to 4000 [Å]. The gate electrode 13 is formed of a second-layer gate electrode material in the manufacturing process. The gate electrode 13 is provided with a single-layer high-melting-point metal film or a high-melting-point metal silicide film, or a high-melting-point metal film or a high-melting-point metal silicide film on a polycrystalline silicon film in order to reduce the resistance value. It may be formed of a composite film. The gate electrode 13 is formed integrally with the word line (WL) 13.

The low impurity concentration n-type semiconductor region 15 is
It is provided between the n ⁺ type semiconductor region 19 and the channel formation region. The semiconductor region 15 is so-called LDD (L ightly D oped
Constituting a MISFET of D rain) structure. The semiconductor region 15 is configured to be self-aligned with the gate electrode 13. The high impurity concentration n ⁺ type semiconductor region 19 is
And is self-aligned to gate electrode 13.

One semiconductor region 1 of this memory cell selecting MISFETQds
Numeral 9 is integrally formed (connected) with the semiconductor region 7 which is the lower electrode of the information storage capacitor C. For memory cell selection
A wiring 23 is connected to the other semiconductor region 19 of the MISFET Qds through a connection hole 22 formed in the interlayer insulating film 21.
The wiring 23 is used as a complementary data line (DL). wiring
23 is formed of, for example, aluminum or an aluminum alloy to which Si or Cu is added. Si reduces the alloy spike phenomenon. Cu reduces stress migration.

Although not shown, a final passivation film is formed on the memory cell DM configured as described above.

As shown in the central part of FIG. 1A, the memory cell FM of the EEPROM is composed of a series circuit of a field effect transistor Qf having a FLOTOX structure and a MISFET Qfs for selecting a memory cell. That is, the memory cell FM has a two-transistor structure.

The field effect transistor Qf is configured to have information “1” or “0”. The field effect transistor Qf mainly includes a semiconductor substrate 1, a semiconductor region 7, a gate insulating film 6, a tunnel insulating film 8, a floating gate electrode 9, a gate insulating film 11, a control gate electrode 13, a source region and a drain region. N-type semiconductor region 15 and a pair of
It is composed of an n ⁺ type semiconductor region 19.

The semiconductor substrate 1 is used as a channel forming region.

The semiconductor region 7 is formed integrally with a semiconductor region 19 used as a drain region, and extends to the main surface of the semiconductor substrate 1 below the tunnel insulating film 8.

Gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the main surface of semiconductor substrate 1. The gate insulating film 6
The information storage capacitor C is formed to have a thickness larger than that of the dielectric film 8, for example, about 500 [Å]. That is, the gate insulating film 6 has a normal information writing operation and erasing operation range (for example, the semiconductor region 7 and the control gate electrode).
13 with a voltage of 17 to 20 [V]), the dielectric strength between the semiconductor region 7 and the floating gate electrode 9 can be ensured.

The tunnel insulating film 8 is formed of a silicon oxide film obtained by removing a part of the gate insulating film 6 below the floating gate electrode 9 and oxidizing the removed surface of the main surface of the semiconductor substrate 1. The tunnel insulating film 8 is formed with a thin film thickness, for example, about 100 [Å] similarly to the dielectric film 8. Since the tunnel insulating film 8 having a small thickness can increase the amount of tunnel current per unit area, the time required for the information writing operation and the erasing operation of the memory cell FM can be reduced.

The floating gate electrode 9 is made of a first-layer gate electrode material, like the plate electrode 9 of the information storage capacitor C.

Gate insulating film 11 is formed of a silicon oxide film obtained by oxidizing the surface of floating gate electrode 9. Gate insulating film
Numeral 11 is configured so that a dielectric strength between the floating gate electrode 9 and the control gate electrode 13 can be ensured in the information writing operation, the reading operation, and the erasing operation range. The gate insulating film 11 is formed with a relatively thick film thickness of, for example, about 300 to 400 [Å].

The control gate electrode 13 is provided on the gate insulating film 11. The control gate electrode 13 is made of a second-layer gate electrode material, like the gate electrode 13 of the MISFET Qds for selecting a memory cell of the memory cell DM of the DRAM.

This field effect transistor Qf has an LDD structure.

The MISFET Qfs for memory cell selection basically includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 as a source region and a drain region, and a pair of n-type semiconductor regions 15.
It is composed of an n ⁺ type semiconductor region 19.

Each of the gate insulating film 6 and the gate electrode 9 is formed by substantially the same manufacturing process as that of each of the field-effect transistors Qf. The MISFETQfs for selecting a memory cell has an LDD structure. The semiconductor region 19 that is the source region of the memory cell selection MISFET Qfs is formed integrally with the semiconductor region 19 that is the drain region of the field effect transistor Qf.

A shunt wiring 13 is provided on the gate electrode 9 of the memory cell selecting MISFET Qfs with an interlayer insulating film 11 interposed. The shunt wiring 13 is connected to the gate electrode 9 through connection holes (not shown) formed in the interlayer insulating film 11 for each memory cell selecting MISFET Qfs or for each predetermined number in the direction in which the word line extends. I have. That is, the shunt wiring 13 can reduce the resistance value of the gate electrode 9 of the memory cell selection MISFET Qfs and the word line integrally formed therewith. MISFETQf for memory cell selection
s is the gate electrode 9 like the field effect transistor Qf.
And a two-layer gate structure including the shunt wiring 13. As described above, when each of the field-effect transistor Qf and the MISFET Qfs for selecting a memory cell has a two-layer gate structure, the dimension between both gates is defined only by the processing dimension without requiring a mask alignment allowance in a manufacturing process. can do. That is, the space between the field effect transistor Qf and the memory cell selecting MISFET Qfs can be reduced, and the area occupied by the memory cell FM can be reduced.

A wiring 23 is connected through a connection hole 22 to a semiconductor region 19 that is a source region of the field-effect transistor Qf of the memory cell FM. This wiring 23 is used as a source wiring (SL). A wiring 23 is connected through a connection hole 22 to a semiconductor region 19 that is a drain region of the MISFET Qfs for selecting a memory cell of the memory cell FM. This wiring 23 is a data line (DL)
Used as

As shown on the right side of FIG. 1A, the memory cell EM of the EPROM is constituted by a field effect transistor. The memory cell EM mainly includes a semiconductor substrate 1, a gate insulating film 6, a floating gate electrode 9, a gate insulating film 11, a control gate electrode 13, a pair of n-type semiconductor regions 16 serving as a source region and a drain region, and a pair of n-type semiconductor regions. ^{+ The} semiconductor region 19 is provided.

This memory cell EM has a two-layer gate structure similarly to the field effect transistor Qf of the memory cell FM of the EEPROM, and
It has an LDD structure. The low impurity concentration n-type semiconductor region 16 of the field effect transistor which is the memory cell EM.
Have a higher impurity concentration than the low impurity concentration n-type semiconductor region 15 such as the MISFETs Qds, Qf, and Qfs having the LDD structure. The semiconductor region 16 has a lower impurity concentration than the n ⁺ -type semiconductor region 19 having a high impurity concentration, such as the other MISFETs Qds, Qf, and Qfs. The semiconductor region 16 is configured to increase the electric field intensity near the drain region of the field effect transistor to increase the amount of generated hot carriers. That is, the semiconductor region 16 is configured to increase the amount of hot electrons injected into the floating gate electrode 9 of the memory cell EM and to reduce the time required for writing information. Further, the semiconductor region 16 is configured so that the resistance values of the source region and the drain region near the channel formation region can be reduced, the transmission conductance can be reduced, and the information reading time can be shortened.

A wiring 23 is connected through a connection hole 22 to a semiconductor region 19 that is a source region of a field-effect transistor that is a memory cell EM. The wiring 23 is used as a source wiring (SL). A wiring 23 is connected to a semiconductor region 19 as a drain region of the field effect transistor through a connection hole 22. The wiring 23 is used as a data line (DL).

CMOS of the peripheral circuit, that is, n-channel MISFETs Qn ₁ , Qn ₁
Each of the n ₂ and p-channel MISFETs Qp ₁ and Qp ₂ is configured as shown in FIG. 1B.

The n-channel MISFET Qn ₁ includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n ⁺ -type semiconductor regions 19.
It is composed of

The n-channel MISFET Qn ₂ includes a semiconductor substrate 1, a gate insulating film 12, a gate electrode 13, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n ⁺ -type semiconductor regions 19.
It is composed of

The p-channel MISFET Qp ₁ includes a well region 2, a gate insulating film 6, a gate electrode 9, a pair of p-type semiconductor regions 17 and a pair of p ⁺ -type semiconductor regions 20 which are a source region and a drain region.
It is composed of

The p-channel MISFET Qp ₂ includes a well region 2, a gate insulating film 12, a gate electrode 13, a pair of p-type semiconductor regions 17 and a pair of p ⁺ -type semiconductor regions 20 which are a source region and a drain region.
It is composed of

Each of the n-channel MISFET Qn ₁ and the p-channel MISFET Qp ₁ has the same gate insulating film 6 and gate electrode 9 as the gate insulating film 6 such as the field effect transistor Qf of the memory cell FM and the floating gate electrode 9 in the same manufacturing process. Each is formed. That is, n-channel MISFETQ
In each of the n ₁ and p-channel MISFETs Qp ₁ , a gate electrode 9 is formed of a first-layer gate electrode material.

On the other hand, the n-channel MISFETQn ₂ and the p-channel MISFETQ
The respective p _2, MISF for memory cell selection of the memory cell DM
Each of the gate insulating film 12 and the gate electrode 13 is formed by the same manufacturing process as the gate insulating film 12 and the gate electrode 13 of the ETQds. That is, the n-channel MISFETQn ₂ ,
The respective p-channel MISFET Qp _2, the gate electrode 13 is formed in the gate electrode material of the second layer.

Each of the MISFETs Qn ₁ , Qn ₂ , Qp ₁ , and Qp ₂ has an LDD structure. The wiring 23 is connected to the respective semiconductor regions 19 of the n-channel MISFETs Qn ₁ and Qn ₂ . p-channel MISF
A wiring 23 is connected to each of the semiconductor regions 20 of ETQp ₁ and Qp ₂ .

As described above, a semiconductor including the DRAM memory cell DM (dynamic storage element), the FLOTOX structure memory cell FM (nonvolatile storage element), and the MISFETs (Qn ₁ , Qn ₂ , Qp ₁ , Qp ₂ ) of the peripheral circuit In the integrated circuit device, the dielectric film 8 of the information storage capacitor C of the memory cell DM and the memory cell FM
The tunnel insulating film 8 of the field effect transistor Qf of FIG.
By configuring the MISFET with a film thickness smaller than that of the gate insulating film 6 or 12, the charge storage amount of the information storage capacitor C can be improved and the area occupied by the memory cell DM can be reduced. Since the degree of integration can be improved and the amount of tunnel current that can flow through the tunnel insulating film 8 can be increased, the time for writing information to the memory cell FM of the EEPROM can be reduced, and the gate of the MISFET can be reduced. Since the withstand voltage of the insulating film 6 or 12 can be improved, electrical reliability can be improved.

Next, a method for manufacturing the semiconductor integrated circuit device will be described.
A brief description will be given with reference to FIGS. 2A and 2B to 9A and 9B (cross-sectional views of main parts shown in respective manufacturing steps).

First, a p ^- type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, the CMOS p-channel MISFETs Qp ₁ and Qp ₂
In the formation region, an n ⁻ -type well region 2 is formed on the main surface of the semiconductor substrate 1. In addition, the entire region of the main surface of the semiconductor substrate 1 different from the n ⁻ -type well region 2 or the CMOS of the peripheral circuit
To the n-channel MISFET Qn ₁ and Qn ₂ forming region p ^- may be formed -type well region.

Next, a field insulating film 3 is formed on the main surfaces of the semiconductor substrate 1 and the well region 2 between the semiconductor element forming regions.
To form The field insulating film 3 is formed of a silicon oxide film in which the respective main surfaces of the semiconductor substrate 1 and the well region 2 are selectively oxidized. The p-type channel stopper region 4 is formed under the field insulating film 3 on the main surface of the semiconductor substrate 1 by substantially the same manufacturing process as the step of forming the field insulating film 3.
To form

Next, as shown in FIGS. 2A and 2B, a gate insulating film 6A is formed on the respective main surfaces of the semiconductor substrate 1 and the well region 2 in the semiconductor element formation region. This gate region film 6A is used as a part of a gate insulating film of a field effect transistor or MISFET. The gate insulating film 6A is formed of a silicon oxide film in which the main surfaces of the semiconductor substrate 1 and the well region 2 are oxidized.

Next, as shown in FIGS. 3A and 3B, the area for forming the information storage capacitor C of the memory cell DM of the DRAM and the EEPROM
In the region where the field effect transistor Qf of the memory cell FM is formed, the n-type semiconductor region 7 is formed on the main surface of the semiconductor substrate 1 by the same manufacturing process. The semiconductor region 7 forms a lower electrode (one electrode) in a region where the information storage capacitor C is formed. The semiconductor region 7 is formed in the field effect transistor Qf formation region to allow a tunnel current to flow between the drain region (19) and the floating gate electrode (9). The semiconductor region 7 is formed by introducing an n-type impurity such as As or P into the main surface of the semiconductor substrate 1 through the gate insulating film 6A. The semiconductor region 7 is, for example, 10
It is formed by introducing As at about ¹⁵ [atoms / cm ² ] by ion implantation at an energy of about 60 to 100 [KeV].
When introducing this n-type impurity, a photoresist film (not shown) is used as a mask for introduction.

Next, the gate insulating film 6A is selectively removed in the formation region of the information storage capacitor C of the memory cell DM of the DRAM and the formation region of the field effect transistor Qf of the memory cell FM of the EEPROM. The gate insulating film 6A in the field effect transistor Qf formation region removes a part under the floating gate electrode (9) formation region.

Next, as shown in FIGS. 4A and 4B, in a region where the gate insulating film 6A is removed, a dielectric film 8 and a tunnel insulating film are formed on the main surface of the semiconductor substrate 1 (actually, the semiconductor region 7). The film 8 is formed in the same manufacturing process. The dielectric film 8 is formed on the main surface of the semiconductor region 7 in the information storage capacitor C forming region. The tunnel insulating film 8 is a field effect transistor
It is formed on the main surface of the semiconductor region 7 in the Qf formation region. Each of the dielectric film 8 and the tunnel insulating film 8 is formed of a silicon oxide film in which the main surface of the semiconductor region 7 is oxidized, and has a small thickness as described above. In the process of forming the dielectric film 8 and the tunnel insulating film 8, as shown in FIGS. 4A and 4B, the gate insulating film 6A is grown to form the gate insulating film 6. Since the thickness of the dielectric film 8 or the thickness of the tunnel insulating film 8 is added to the gate insulating film 6A, the gate insulating film 6 is formed with a large thickness as described above.

Next, the first gate insulating layer 9 is formed on the entire surface of the substrate including the dielectric film 8, the tunnel insulating film 8, the gate insulating film 6, and the like.
Is deposited. The first gate electrode layer 9 is, for example,
It is formed of a polycrystalline silicon film deposited by CVD. After the polycrystalline silicon film is deposited, an n-type impurity, for example, P for reducing the resistance value is introduced (ion implantation or thermal diffusion).

Next, predetermined patterning is performed on the first-layer gate electrode layer 9, and as shown in FIGS. 5A and 5B,
Each of the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 is formed in the same manufacturing process. The plate electrode 9 is formed on the dielectric film 8 in a region where the information storage capacitor C of the memory cell DM of the DRAM is formed. The floating gate electrode 9 is connected to the field effect transistor Qf of the EEPROM.
EP on the tunnel insulating film 8 and the gate insulating film 6 in the formation region
Gate insulating film 6 in the field effect transistor formation region of ROM
Formed on each of the above. Each floating gate electrode 9 is patterned only in the gate width direction.
The gate electrode 9 is a MISFETQfs for selecting a memory cell of the EEPROM.
Forming region, n-channel MISFET Qn ₁ forming region of the CMOS, is formed on the p-channel MISFET Qp ₁ forming region of each of the gate insulating film 6. In the step of forming the plate electrode 9, the semiconductor region (lower electrode) 7, the dielectric film 8, and the plate electrode (upper electrode) 9 are sequentially superimposed on each other. Is completed.

Next, an insulating film covering the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 is formed.
This insulating film is formed of a silicon oxide film in which the respective surfaces of the plate electrode 9, the floating gate electrode 9, and the gate electrode 9 are oxidized.

Next, in a state where the insulating film on the plate electrode 9 is left, the insulating film on the floating gate electrode 9 and the gate electrode 9 and the gate in the region where the first gate electrode layer 9 is not formed are formed. The insulating film 6 is selectively removed.

Next, an oxidation treatment is performed on the entire surface of the substrate, and FIG.
As shown in FIG. B, an interlayer insulating film is formed on the surface of the plate electrode 9.
10. A gate insulating film on the surface of the floating gate electrode 9.
11, an insulating film 11 is formed on the surface of the gate electrode 9, and a gate insulating film 12 is formed on the main surface of the semiconductor substrate 1 and the main surface of the well region 2, respectively. These interlayer insulating film 10, gate insulating film 11,
Each of the insulating film 11 and the gate insulating film 12 is formed by the same manufacturing process. The interlayer insulating film 10 is, for example, 2000 to 3000 [Å]
It is formed with a film thickness as large as about. Gate insulating film 11, insulating film
Each of the layers 11 is formed to a thickness of, for example, about 300 to 400 [Å]. The gate insulating film 12 is formed with a thickness of, for example, about 250 [Å]. The interlayer insulating film 10 on the surface of the plate electrode 9 is preferably thick because it basically insulates the plate electrode 9 from the word line 13 extending thereover, but is similar to the gate insulating film 11 and the like. May be formed with a thin film thickness to reduce the number of manufacturing steps.

Next, on the interlayer insulating film 10, on the gate insulating film 11,
A second-layer gate electrode layer 13 is deposited on the entire surface of the substrate including the upper and gate insulating films 12. The second gate electrode layer 13 is formed of, for example, a polycrystalline silicon film deposited by CVD. This polycrystalline silicon film has n as in the case of the first gate electrode layer 9.
Type impurities have been introduced.

Next, in each of the memory cell FM formation region of the EEPROM and the memory cell EM formation region of the EPROM, the second-time gate electrode layer 13 is subjected to a first patterning. In this patterning, the second-layer gate electrode layer 13 is patterned, and the interlayer insulating film 11 and the floating gate electrode 9 are sequentially patterned (overcut) using the same mask. With this patterning,
In the memory cell FM formation region of the EEPROM, the control gate electrode 13 of the field effect transistor Qf and the shunt wiring 13 of the MISFET Qfs for selecting a memory cell can be formed. Further, in the memory cell EM formation region of the EPROM, the control gate electrode 13 of the field effect transistor is formed.
Can be formed. The patterning is, for example,
This is performed using anisotropic etching such as RIE. In the memory cell FM of the EEPROM, the field effect transistor Qf and the MISFET Qfs for memory cell selection are formed in a double-layer gate structure in which each is overlapped, so that the dimension between the respective gate electrodes is not added to the size of the mask alignment margin in the manufacturing process. Since the dimension between the gate electrodes can be defined by the processing accuracy of the mask, the occupied area of the memory cell FM can be reduced.

Next, the memory cell DM formation region of the DRAM, n-channel MISFET Qn ₂ forming region of the CMOS, in each of the p-channel MISFET Qp ₂ forming region is subjected to a second round of patterning the second layer of the gate electrode layer 13. By performing this patterning, as shown in FIGS. 7A and 7B, the MISFET Qds for selecting the memory cell of the memory cell DM and the n-channel M
Gate electrodes 13 of ISFETQn ₂ and p-channel MISFEQp ₂ can be formed. The patterning is performed using anisotropic etching such as RIE.

Next, an oxidation process is performed on the entire surface of the substrate to form the gate electrodes 9 and 1.
3. An insulating film 14 covering the surfaces of the floating gate electrode 9 and the control gate electrode 13 is formed. The insulating film 14 is formed in order to increase the thickness of each of the gate insulating films 6 and 12 at the ends of the respective gate electrodes 9 and 13 and to improve the withstand voltage.

Next, the MISFET for selecting the memory cell of the DRAM memory cell DM
In each of the Qds formation region, the EEPROM memory cell FM formation region, and the CMOS n-channel MISFETs Qn ₁ and Qn ₂ formation region, an n-type semiconductor region 15 is formed on the main surface of the semiconductor substrate 1. In the semiconductor region 15, for example, P of about 10 ¹³ [atoms / cm ² ] is set to 50 to 8
It can be formed by ion implantation with energy of about 0 [KeV].

Next, a p-type semiconductor region 17 is formed on the main surface of the well region 2 in the CMOS p-channel MISFETs Qp ₁ and Qp ₂ formation region. The semiconductor region 17 can be formed, for example, by introducing B of about 10 ¹³ [atoms / cm ² ] by ion implantation with energy of about 10 to 20 [KeV].

Next, as shown in FIGS. 8A and 8B, in the memory cell EM formation region of the EPROM, the n-type semiconductor region 16 having a higher impurity concentration than the n-type semiconductor region 15 is formed on the main surface of the semiconductor substrate 1. To form The semiconductor region 16 is configured to increase the amount of hot carriers mainly by increasing the electric field strength near the drain region. The semiconductor region 16 can be formed, for example, by introducing As of about 10 ¹⁵ [atoms / cm ² ] by ion implantation at an energy of about 60 to 100 [KeV].

Semiconductor regions 15, 1 for forming these LDD structures
Each of 6 and 17 is formed by self-alignment with any one of the gate electrodes 9 and 13, the floating gate electrode 9 and the control gate electrode 13. Semiconductor regions 15, 16, 17
May be interchanged in the order in which they are formed, or may be formed before the insulating film 14 is formed.

Next, a sidewall spacer 18 is formed on each side wall of each of the gate electrodes 9, 13, the floating gate electrode 9, and the control gate electrode 13. The sidewall spacers 18 can be formed, for example, by performing anisotropic etching such as RIE on a silicon oxide film deposited by CVD.

Next, the MISFET for selecting the memory cell of the DRAM memory cell DM
Qds formation area, EEPROM memory cell FM formation area, EPROM memory cell EM formation area, CMOS n-channel MISFET Qn ₁ , Q
In the n ₂ formation region, an n ⁺ semiconductor region 19 is formed on the main surface of the semiconductor substrate 1. The semiconductor region 19 is, for example, 10 ¹⁶ [atoms /
cm ² ] can be formed by ion implantation at an energy of about 60 to 100 [KeV]. The semiconductor region 19 is formed by self-alignment with the respective gate electrodes 9 and 13, the floating gate electrode 9, and the control gate electrode 13. The MISF for selecting the memory cell of the memory cell DM is formed by the process of forming the semiconductor region 19.
ETQds, the field effect transistor Qf of the memory cell FM, the MISFET Qfs for memory cell selection, the field effect transistor of the memory cell EM, and the n-channel MISFETs Qn ₁ and Qn ₂ are completed.

Next, as shown in FIGS. 9A and 9B, the CMOS p
In each of the formation regions of the channel MISFETs Qp ₁ and Qp ₂ , a p ⁺ type semiconductor region 20 is formed on the main surface of the well region 2. For example, the semiconductor region 20 contains B of about 10 ¹⁵ [atoms / cm ² ] for 10 to 2 times.
It can be formed by ion implantation with energy of about 0 [KeV]. By the step of forming the semiconductor region 20, each of the p-channel MISFETs Qp ₁ and Qp ₂ is completed.

Next, each of the interlayer insulating film 21 and the connection hole 22 is sequentially formed,
As shown in FIGS. 1A and 1B, a wiring 23 is formed. The interlayer insulating film 21 is formed of, for example, a single layer of a BPSG film or a PSG film, or a composite film mainly including the same.

Thereafter, a final passivation film (not shown) is formed on the entire surface of the substrate, whereby the semiconductor integrated circuit device of Example I is completed.

As described above, the manufacture of the semiconductor integrated circuit device including the DRAM memory cell (dynamic storage element) DM having the information storage capacitive element C and the EEPROM memory cell (nonvolatile storage element) FM having the tunnel insulating film 8 is manufactured. In the method, the step of forming the dielectric film 8 of the information storage capacitive element C of the memory cell DM and the step of forming the tunnel insulating film 8 of the memory cell FM are performed in the same manufacturing step, thereby achieving the dielectric constant. In the process of forming the body film 8, the tunnel insulating film 8 is formed.
Can be formed, so that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced corresponding to the step of forming the tunnel insulating film 8.

Also, a memory cell DM of a DRAM having a capacitance element C for storing information and a memory cell of an EEPROM having a tunnel insulating film 8 are provided.
Forming a semiconductor region 7 for forming a lower electrode of an information storage capacitor C of the memory cell DM in a method of manufacturing a semiconductor integrated circuit device provided with FM;
The step of forming the semiconductor region 7 of the FM field effect transistor Qf is performed in the same manufacturing process, and thereafter, the step of forming the dielectric film 8 of the information storage capacitor C and the step of forming the tunnel of the field effect transistor Qf are performed. The step of forming the insulating film 8 and the step of forming the dielectric film 8 are performed in the same manufacturing process, thereby forming the semiconductor region 7 of the field effect transistor Qf and the tunnel insulating film in the step of forming the dielectric film 8 and the semiconductor region 7 of the information storage capacitor C. 8 can be formed, so that the semiconductor region 7 can be formed.
In addition, the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the process of forming the tunnel insulating film 8.

Further, in the method for manufacturing a semiconductor integrated circuit device provided with a memory cell DM of a DRAM having an information storage capacitor C and a memory cell FM of an EEPROM having a floating gate electrode 9 (or a memory cell EM of an EPROM), The step of forming the plate electrode (upper electrode) 9 of the information storage capacitive element C of the cell DM and the step of forming the floating gate electrode 9 of the memory cell FM (and the memory cell EM) are performed in the same manufacturing process. Thereby, the floating gate electrode 9 can be formed in the step of forming the plate electrode 9 of the information storage capacitive element C.
The manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the floating gate electrode 9.

The information storage capacitor C and the memory cell selection MI
It has a memory cell DM of a DRAM having SFETQds and a floating gate electrode 9 and a control gate electrode 13.
EEPROM memory cell FM (or EPROM memory cell E)
M) in a method of manufacturing a semiconductor integrated circuit device comprising:
Forming a plate electrode (upper electrode) 9 of the information storage capacitive element C of the memory cell DM;
Forming the floating gate electrode 9 of the memory cell EM (or the memory cell EM) and the step of forming the gate electrode 13 of the MISFET Qds for selecting the memory cell of the memory cell DM; Memory cell E
By performing the step of forming the control gate electrode 13 of (M) in the same manufacturing step, the plate electrode 9 of the information storage capacitor C and the MISFET Qds
Since the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM can be formed in the step of forming the gate electrode 13 of the first embodiment, the semiconductor integrated circuit corresponds to the step of forming the floating gate electrode 9 and the control gate electrode 13. The number of manufacturing steps of the circuit device can be reduced.

Furthermore, DRAM memory cells DM and EEPROM memory cells
In a method of manufacturing a semiconductor integrated circuit device having an FM, a semiconductor region 7, a dielectric film 8, a plate electrode 9, and a memory cell selecting MI of an information storage capacitive element C of the memory cell DM.
The step of forming each of the gate electrodes 13 of the SFET Qds and the step of forming each of the semiconductor region 7, the tunnel insulating film 8, the floating gate electrode 9, and the control gate electrode 13 of the memory cell FM are performed in the same manufacturing process. In the step of forming each of the semiconductor region 7, the dielectric film 8, the plate electrode 9, and the gate electrode 13 of the memory cell DM,
A semiconductor region 7 of the memory cell FM, a tunnel insulating film 8,
Floating gate electrode 9, control gate electrode
Since each of the thirteen can be formed, the manufacturing process of the semiconductor integrated circuit device can be further reduced correspondingly.

(Embodiment II) The present embodiment II is directed to the semiconductor integrated circuit device according to the embodiment I, wherein the plate electrode of the information storage capacitor of the memory cell of the DRAM is formed of the gate electrode material of the second layer. This is a second embodiment of the present invention in which the gate electrode of the selection MISFET is formed of the first-layer gate electrode material.

A semiconductor integrated circuit device incorporating a microcomputer according to a second embodiment of the present invention is shown in FIG. In the present embodiment II, the other element structures except the memory cells of the DRAM are the same as those of the above-mentioned embodiment I.
Figure 10 shows DRAM memory cells DM, EEPROM memory cells FM and
Only the memory cell EM of the EPROM is shown.

As shown in FIG. 10, the memory cell DM of the DRAM of the semiconductor integrated circuit device is composed of a series circuit of a memory cell selecting MISFET Qds and an information storage capacitor C.

The information storage capacitive element C of the memory cell DM has a planar structure in which an n-type semiconductor region (lower electrode) 7, a dielectric film 8, and a plate electrode (upper electrode) 13 are sequentially stacked. The plate electrode 13 is formed of a second-layer gate electrode material. The dielectric film 8 is a tunnel insulating film 8 of the field effect transistor Qf of the memory cell FM of the EEPROM.
It is formed with a thin film thickness in the same manner as described above.

The MISFET Qds for selecting a memory cell includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n ⁺ -type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material.

Next, a method for manufacturing the semiconductor integrated circuit device will be described.
A brief description will be given with reference to FIGS. 11 to 13 (cross-sectional views of main parts shown in respective manufacturing steps).

First, as in the first embodiment, after the well region 2 is formed in the semiconductor substrate 1, the field insulating film 3 and the p-type channel stopper region 4 are sequentially formed.

Next, in the semiconductor element formation region, the semiconductor substrate 1,
A gate insulating film 6A is formed on each main surface of well region 2.

Next, the area for forming the information storage capacitor C of the memory cell DM of the DRAM and the field effect transistor of the memory cell FM of the EEPROM
An n-type semiconductor region 7 is formed on the main surface of each semiconductor substrate 1 in the Qf formation region.

Next, the field effect transistor of the EEPROM memory cell FM
In the Qf formation region, a part of the gate insulating film 6A on the semiconductor region 7 is removed, and a tunnel insulating film 8 is formed in the removed region as shown in FIG. Through the step of forming the tunnel insulating film 8, the gate insulating film 6A in other regions is grown on the gate insulating film 6. Unlike the first embodiment, the second embodiment is different from the first embodiment in that the dielectric film 8 of the information storage capacitor C is formed by a process different from the process of forming the tunnel insulating film 8.
To form

Next, a first-layer gate electrode layer 9 is formed on the entire surface of the substrate including the gate insulating film 6 and the tunnel insulating film 8. Then, predetermined patterning is performed on the first gate electrode layer 9 to form the gate electrode 9 and the floating gate electrode 9. The gate electrode 9 is formed on each of the gate insulating films 6 in the memory cell selection MISFETQds formation region of the DRAM memory cell DM and the memory cell selection MISFETQfs formation region of the EEPROM memory cell FM. The floating gate electrode 9 is formed on the gate insulating film 6 and the tunnel insulating film 8 of the field effect transistor Qf of the memory cell FM of the EEPROM,
Are formed on the gate insulating film 6 of the memory cell EM. Although not shown, the gate electrode 9 is connected to a peripheral circuit.
CMOS n-channel MISFET Qn ₁ formation region, p-channel MISFE
TQp also formed on the _first gate insulating film of each of the formation region 6.

Next, an insulating film 11A is formed on each surface of the gate electrode 9 and the floating gate electrode 9. The respective surfaces of the insulating film 11A gate electrode 9 and floating gate electrode 9 are formed of oxidized silicon oxide films. The step of forming the insulating film 11A, although not shown, the n main surface of the channel MISFET Qn ₂ forming region of the semiconductor substrate 1 in the peripheral circuit, the gate husband on the principal surface of the well region 2 of the p-channel MISFET Qp ₂ forming region s A gate insulating film used as a part of the insulating film (12) is formed.

Next, as shown in FIG. 12, the gate insulating film 6 in the region for forming the information storage capacitor C of the memory cell DM of the DRAM is selectively removed, and the main surface of the semiconductor region 7 is exposed.

Next, a dielectric film 8 is formed on the exposed main surface of the semiconductor region 7. The dielectric film 8 is formed of, for example, a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1. The dielectric film 8 is formed in a step different from that of the tunnel insulating film 8, but is formed with a substantially similar thin film thickness. By forming the dielectric film 8, the insulating film 11A can be grown to form the insulating film 11 on the surface of the gate electrode 9 and the gate insulating film 11 on the surface of the floating gate electrode 9. Also, CMOS n-channel MISFETQn of the peripheral circuit
₂ formation regions, in each of the p-channel MISFET Qp ₂ forming region, the gate insulating film is grown, it is possible to form the gate insulating film 12.

Next, a second-layer gate electrode layer 13 is formed on the entire surface of the substrate including the dielectric film 8, the gate insulating film 11, and the gate insulating film 12 (not shown). Then, the second gate electrode layer 13 is subjected to patterning twice, and as shown in FIG. 13, the plate electrode 13 and the control gate electrode 1 are formed.
3. Wiring 13 for shunt (and gate electrode 13 for peripheral circuit)
To form each.

Thereafter, similarly to the embodiment I, the insulating film 14, the semiconductor regions 15, 16, 17, the sidewall spacers 18, the semiconductor region
The semiconductor integrated circuit device of Example II is completed by sequentially forming each of 19, 20, the interlayer insulating film 21, the connection hole 22, and the wiring 23.

The semiconductor integrated circuit device configured as described above has the following effects in addition to the effects of the first embodiment.

In a method of manufacturing a semiconductor integrated circuit device including a DRAM memory cell DM having an information storage capacitor C and an EEPROM memory cell FM (or EPROM memory cell EM) having a control gate electrode 13, the memory cell DM The step of forming the plate electrode (upper electrode) 13 of the information storage capacitor C and the step of forming the control gate electrode 13 of the memory cell FM (or memory cell EM) in the same manufacturing process. Since the control gate electrode 13 can be formed in the step of forming the plate electrode 13 of the information storage capacitive element C, the manufacturing process of the semiconductor integrated circuit device is equivalent to the step of forming the control gate electrode 13. Can be reduced.

The information storage capacitor C and the memory cell selection MI
It has a memory cell DM of a DRAM having SFETQds and a floating gate electrode 9 and a control gate electrode 13.
EEPROM memory cell FM (or EPROM memory cell E)
M) in a method of manufacturing a semiconductor integrated circuit device comprising:
Forming a floating gate electrode 9 of the memory cell FM; and a memory cell selecting MISF of the memory cell DM.
This is performed in the same manufacturing process as the process of forming the gate electrode 9 of ETQds, and the control gate electrode 13 of the memory cell FM is used.
And the step of forming the plate electrode 13 of the information storage capacitive element C of the memory cell DM in the same manufacturing process, whereby the memory cell selecting MISFET Qds
Gate electrode 9 and plate electrode of information storage capacitance element
Since the floating gate electrode 9 and the control gate electrode 9 of the memory cell FM can be formed in the step of forming the memory cell FM, the step of forming the floating gate electrode 9 and the control gate electrode 13 is equivalent to the step of forming the floating gate electrode 9 and the control gate electrode 13. The number of manufacturing steps can be reduced.

Further, the DRA memory cell DM and the EEPROM memory cell F
Forming a semiconductor region 7, a plate electrode 13, and a gate electrode 9 of a MISFET Qds for selecting a memory cell in a method of manufacturing a semiconductor integrated circuit device having M; Memory cell FM
And the step of forming each of the semiconductor region 7, the control gate electrode 13, and the floating gate electrode 9 are performed in the same manufacturing process to form the semiconductor region 7, the plate electrode 13, and the gate electrode 9 of the memory cell DM. In this step, each of the semiconductor region 7, the control gate electrode 13, and the floating gate electrode 9 of the memory cell FM can be formed, so that the manufacturing process of the semiconductor integrated circuit device can be further reduced correspondingly. .

(Embodiment III) Embodiment III is a third embodiment of the present invention in which the semiconductor element has a single-layer gate structure in the semiconductor integrated circuit device of Embodiment I.

A semiconductor integrated circuit device incorporating a microcomputer according to Embodiment III of the present invention is shown in FIG. 14A and FIG. 14B (a cross-sectional view of a main part showing each element).

As shown in FIGS. 14A and 14B, the information storage capacitor C of the memory cell DM of the DRAM includes an n-type semiconductor region (lower region) 7, a dielectric film 8, and a plate electrode (upper electrode) 9. Are successively overlapped with each other in a planar structure.
The plate electrode 9 is formed of a first-layer gate electrode material. The dielectric film 8 is formed with a small film thickness as in the first embodiment.

The MISFET Qds for selecting a memory cell includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 serving as a source region and a drain region, and a pair of n ⁺ -type semiconductor regions 19. The gate electrode 9 is formed of a first-layer gate electrode material. That is, the memory cell DM of the DRAM has a single-layer gate structure.

The cross-sectional structure of the memory cell FM of the EEPROM is not shown in FIGS. 14A and 14B, but as shown in FIG. 17 (a plan view of the memory cell), the field-effect transistor Qf It is composed of a series circuit with MISFETQfs.

The field-effect transistor Qf includes a semiconductor substrate 1, an n-type semiconductor region 7, a gate insulating film (first gate insulating film) 6, a tunnel insulating film 8, a floating gate electrode 9, a gate insulating film (second gate insulating film) 6, Control gate electrode
7A, a pair of n-type semiconductor regions 15 and a pair of n ⁺ -type semiconductor regions 19 which are a source region and a drain region. The floating gate electrode 9 is formed of a first-layer gate electrode material. Floating gate electrode 9
Are provided so as to extend over the control gate electrode 7A formed of the n-type semiconductor region in the gate width direction.
Floating gate electrode 9 and control gate electrode
A gate insulating film (second gate insulating film) 6 is provided between the gate insulating film 7A and the gate insulating film 7A. Control gate electrode (semiconductor area)
7A is formed in the same manufacturing process as the semiconductor region 7. The control gate electrode 7A is connected through a connection hole 22 to a wiring 23 used as a word line WL.

MISFTQfs for memory cell selection, as shown in FIG.
The semiconductor device includes a semiconductor substrate 1, a gate insulating film 6, a gate electrode 9, a pair of n-type semiconductor regions 15 and a pair of n ⁺ -type semiconductor regions 19 which are a source region and a drain region. The gate electrode 9 is made of a first-layer gate electrode material. This gate electrode 9 is formed integrally with the word line (WL) 9. The memory cell selecting MISFETQfs has substantially the same structure as the memory cell selecting MISFETQds of the memory cell DM of the DRAM and the n-channel MISFETQn of the peripheral circuit. That is, each of the field-effect transistor Qf of the memory cell FM of the EEPROM and the MISFET Qfs for selecting a memory cell has a single-layer gate structure.

The memory cell EM of the EPROM is the memory cell FM of the EEPROM.
And has a structure similar to that of the field effect transistor Qf. That is, the memory cell EM includes a semiconductor substrate 1, a gate insulating film (first gate insulating film) 6, a floating gate electrode 9, a gate insulating film (second gate insulating film) 6, and a control gate electrode (n-type semiconductor region) 7A. It is composed of This memory cell (field effect transistor) EM has a single-layer gate structure.

The CMOS n-channel MISFET Qn of the peripheral circuit includes a semiconductor substrate 1, a gate insulating film 12, a gate electrode 9, a pair of n-type semiconductor regions 15 as a source region and a drain region, and a pair of n ⁺
It is composed of a type semiconductor region 19. The gate electrode 9 is the first
It is composed of the gate electrode material of the layer.

p-channel MISFETQp is well region 2, gate insulating film
12, a gate electrode 9, a pair of p-type semiconductor regions 17 and a pair of p ⁺ -type semiconductor regions 20, which are a source region and a drain region. The gate electrode 9 is formed of a first-layer gate electrode material. In other words, CMOS n-channel MISF
Each of ETQn and p-channel MISFTQp has a single-layer gate structure.

Next, a method for manufacturing the semiconductor integrated circuit device will be described.
A brief description will be given with reference to FIGS. 15A and 15B and FIGS. 16A and 16B (cross-sectional views of main parts shown in respective manufacturing steps).

First, a well region 2 is formed in a main surface portion of a semiconductor substrate 1 and then a field insulating film 3 and a p-type channel stopper region 4 are formed in the same manner as in the first embodiment.

Next, in the semiconductor element formation region, the semiconductor substrate 1,
An insulating film 6A used as a part of the gate insulating film is formed on each main surface of the well region 2.

Next, the insulating film 6A is selectively removed in each of the CMOS n-channel MISFETQn formation region and the p-channel MISFETQp formation region of the peripheral circuit.

Next, the n-channel MISFET from which the insulating film 6A has been removed
In each of the Qn formation region and the p-channel MISFET Qp formation region, a new gate insulating film 12 is formed on each of the main surfaces of the semiconductor substrate 1 and the well region 2. By the step of forming the gate insulating film 12, the insulating film 6A is grown, and the gate insulating film 6A is formed on the respective main surfaces of the semiconductor substrate 1 and the well region 2.
To form

Next, as shown in FIGS. 15A and 15B, a region for forming an information storage capacitor C of a memory cell DM of a DRAM, a region for forming a field effect transistor Qf and a MISFET Qfs for selecting a memory cell of a memory cell FM of an EEPROM. In each of the memory cell EM formation regions of the EPROM, an n-type semiconductor region 7 and a control gate electrode 7A are formed on the main surface of the semiconductor substrate 1. Each of the semiconductor region 7 and the control gate electrode 7A can be formed by introducing an n-type impurity by ion implantation.

Next, the area for forming the information storage capacitor C of the memory cell DM of the DRAM and the field-effect transistor of the memory cell FM of the EEPORM
In each of the Qf forming regions, the gate insulating film 6 is selectively removed. Then, a dielectric film 8 and a tunnel insulating film 8 are formed on the removed main surface of the semiconductor substrate 1.

Next, a first-layer gate electrode layer 9 is formed on the entire surface of the substrate including the gate insulating films 6 and 12, the dielectric film 8, and the tunnel insulating film 8. Thereafter, the first gate electrode layer 9 is subjected to a predetermined patterning, so that
As shown in FIG. A and FIG. 16B, each of the plate electrode 9, the gate electrode 9, and the floating gate electrode 9 can be formed. The plate electrode 9 is a DRAM memory cell DM.
The upper electrode of the information storage capacitor C is formed. The gate electrode 9 is a MISFET for selecting a memory cell of the memory cell DM.
MISFETQ for memory cell selection of Qds, EEPROM memory cell FM
fs, the gate electrodes of the CMOS MISFETs Qn and Qp of the peripheral circuit are formed. The floating gate electrode 9 forms the respective floating gate electrodes of the field effect transistor Qf of the memory cell FM and the memory cell EM of the EPROM.

Next, as in the first embodiment, the semiconductor regions 15, 16, 1
7, by sequentially forming each of the sidewall spaces 18, the semiconductor regions 19 and 20, the interlayer insulating film 21, the connection hole 22, and the wiring 23, as shown in FIG. 14A and FIG. The circuit device is completed.

The semiconductor integrated circuit device configured as described above has the following effects in addition to the effects of the first embodiment.

In a method of manufacturing a semiconductor integrated circuit device including a DRAM memory cell DM and an EEPORM memory cell FM (or an EPROM memory cell EM), an n-type semiconductor region (lower portion) of an information storage capacitor C of the memory cell DM The step of forming the electrode 7 and the step of forming the n-type semiconductor region 7 and the control gate electrode (n-type semiconductor region) 7A of the memory cell FM are performed in the same manufacturing process, whereby the information storage capacitor element is formed. In the step of forming the semiconductor region 7 of C, the semiconductor region 7 of the memory cell FM and the control gate electrode 7A
Can be formed, the manufacturing configuration of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the semiconductor region 7 and the control gate electrode 7A.

In addition, the DRAM memory cell DM and the EEPROM memory cell FM
(Or a memory cell EM of an EPROM) in the manufacturing method of the semiconductor integrated circuit device, wherein the plate electrode (upper electrode) 9 of the information storage capacitor C of the memory cell DM and the gate electrode 9 of the MISFETQds for memory cell selection. And the step of forming the floating gate electrode 9 of the field effect transistor Qf of the memory cell FM are performed in the same manufacturing process, so that the plate electrode 9 of the information storage capacitive element C and the memory cell In the step of forming the gate electrode 9 of the MISFET Qds, the floating gate electrode 9 of the memory cell FM can be formed.
The number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

Further, since the semiconductor integrated circuit device has a single-layer gate structure, the number of conductive layers is small, and the manufacturing process of the semiconductor integrated circuit device can be simplified.

(Example IV) Example IV is a fourth example of the present invention in which, in the semiconductor integrated circuit device of Example I, the information storage capacitor of the memory cell of the DRAM is configured in a stacked structure.

A semiconductor integrated circuit device incorporating a microcomputer according to Embodiment IV of the present invention is shown in FIG. 18 (a cross-sectional view of a principal part showing each element).

As shown in FIG. 18, the memory cell DM of the DRAM includes a series circuit of a MISFET Qds for selecting a memory cell and an information storage capacitor C having a stacked structure.

The MISFET Qds for memory cell selection is composed of a gate electrode 9 formed of a first-layer gate electrode material, as in the case of Example III.

The information storage capacitor C is a plate electrode (lower electrode)
13, the dielectric film 26 and the plate electrode 27 are sequentially superposed. Plate electrode 13 is for memory cell selection
The MISFET Qds is connected to the semiconductor region 19 on the side not connected to the data line 23. This connection is made through connection holes 25 formed in the interlayer insulating film 24 and defined by the sidewall spacers 18. The plate electrode 13 is formed of a second-layer gate electrode material, for example, a polycrystalline silicon film. The dielectric film 26 is formed by a single layer of a silicon oxide film, a silicon nitride film, a tantalum oxide film, or a composite film thereof formed by an insulating film forming method such as CVD or sputtering. The plate electrode 27 is formed of a third-layer gate electrode material, for example, a polycrystalline silicon film. The second-layer gate electrode material,
Although not shown, each of the third-layer gate electrode materials is used as a wiring or a resistance element in another region.

Each of the memory cell FM of the EEPORM, the memory cell EM of the EPROM, and the CMOS (not shown) of the peripheral circuit has a single-layer gate structure, as in the embodiment III.

Although the method of manufacturing the semiconductor integrated circuit device of this embodiment is omitted, basically, after forming a semiconductor element having a single-layer gate structure such as MISFETQds for selecting a memory cell of a memory cell DM of a DRAM, An information storage capacitor C is formed.

The semiconductor integrated circuit device configured as described above can provide the same effects as those of the first embodiment.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. Of course.

For example, in the present invention, the EEPORM memory cell may have a one-transistor structure (only the field-effect transistor Qf).

Further, the present invention is that the memory cells of the EEPROM MNOS (M etal
N itride O xide S emicanductor) may be constituted by a field effect transistor structure.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device including a dynamic memory element and a nonvolatile memory element, the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views of a main part of a semiconductor integrated circuit device incorporating a microcomputer according to a first embodiment of the present invention. FIGS. 2A and 2B to 9A and FIG. FIG. 9B is a cross-sectional view of a main part showing each manufacturing process of the semiconductor integrated circuit device. FIG. 10 is a cross-sectional view of a main part of a semiconductor integrated circuit device incorporating a microcomputer according to Embodiment II of the present invention. FIGS. 11 to 13 are cross-sectional views showing the main parts of the semiconductor integrated circuit device in each manufacturing process. FIGS. 14A and 14B incorporate a microcomputer which is Embodiment III of the present invention. FIG. 15A and FIG. 15B and FIG. 16A and FIG. 16B are main part cross-sectional views showing respective manufacturing steps of the semiconductor integrated circuit device, FIG. 17 is a plan view showing an EEPROM memory cell of the semiconductor integrated circuit device, and FIG. FIG. 14 is a cross-sectional view of a main part of a semiconductor integrated circuit device including a microcomputer according to a fourth embodiment; In the figure, DM, FM, EM: memory cell, Qds, Qfs: MISFET for memory cell selection, C: capacitance element for information storage, Qf: field effect transistor, Qn, Qp: MISFET, 6, 11 , 12 ... gate insulating film, 7,15,16,17,19,20 ... semiconductor region, 8 ...
A gate electrode, a plate electrode, a floating gate electrode; 13, a gate electrode and a control gate electrode.

Claims (2)

(57) [Claims] 1. A dynamic memory device comprising a plurality of dynamic storage elements having an information storage capacitor in which a dielectric film is interposed on a semiconductor region on which one electrode is to be formed and the other electrode is formed.
A ROM section comprising a plurality of nonvolatile memory elements having a floating gate electrode formed with a DRAM section provided in a predetermined area portion of the semiconductor substrate main surface and a tunnel insulating film through which a current flows using a tunnel phenomenon is provided. A method of manufacturing a semiconductor integrated circuit device provided in another predetermined area portion of a main surface of a semiconductor substrate, wherein the other upper electrode of a capacitance element for storing information of a dynamic memory element in the DRAM section is provided on the main surface of the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, wherein the step of forming a part and the step of forming a floating gate electrode of a nonvolatile memory element in the ROM section are performed in the same manufacturing step. 2. The method according to claim 1, wherein each of an upper electrode of said information storage capacitor element and a floating gate electrode of said nonvolatile storage element is formed of a polycrystalline silicon film. A method for manufacturing a semiconductor integrated circuit device.