JP2877463B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a nonvolatile semiconductor memory device (EEPROM) using an electrically rewritable memory transistor having a floating gate and a control gate.

(Prior Art) An EEPROM using an electrically rewritable memory transistor having a floating gate and a control gate is known. In particular, multiple memory transistors are connected to their sources,
A NAND-type EEPROM in which a drain diffusion layer is connected in series so as to be shared by adjacent ones to form a NAND cell has attracted attention as a device that can be highly integrated.

FIG. 9 is a plan view showing a memory cell structure of an example of such an EEPROM, and FIGS. 10 and 11 are sectional views taken along lines AA 'and BB' of FIG. 9, respectively. A plurality of floating gates 4 (41, 42,...) made of a first-layer polycrystalline silicon film and control gates 6 (61, 62,...) made of a second-layer polycrystalline silicon film are stacked on a p-type silicon substrate 1. , And the select transistors S (S1, S2) provided on the drain side and the source side, respectively, of the memory transistor M (M1, M2,...) Constitute a NAND cell. The gate structure of the selection transistor S is basically the same as that of the memory transistor M,
The gate electrode 9 is formed of a first-layer polycrystalline silicon film and the gate electrode 11 is formed of a second-layer polycrystalline silicon film. However, in the memory transistor M, the first gate insulating film 3 is thin enough to allow a tunnel current to flow, whereas the first gate insulating film 8 in the select transistor S is thin.
Is formed thicker than this. After forming the gate electrode of each part, ion implantation is performed using this as a mask,
A high concentration n-type layer 12 serving as a source / drain diffusion layer is formed. Thereafter, the entire surface is covered with an interlayer insulating film such as a CVD oxide film, and contacts the common source line 16 which contacts the n-type layer which is a common source diffusion layer of the memory cell, and the n-type layer which is a drain diffusion layer of each memory cell. Bit line 14
Are arranged. FIG. 9 shows two sets of NAND cells adjacent to each other in the direction orthogonal to the bit lines.
The floating gates 4 are independent of each other, and the control gates 6 are commonly arranged in a direction orthogonal to the bit lines to become word lines. Similarly, the gate electrode of the selection transistor S is also continuously arranged to form a selection gate line.

The operation of this NAND cell type EEPROM is as follows. The data write operation is performed in order from the memory transistor M4 farthest from the bit line. A high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory transistor M4, and the memory transistor located on the bit line side from the high voltage Vpp
An intermediate potential VppM (= about 10 V) is applied to the control gates of M1 to M3 and the gate electrode of the selection transistor S1, and 0 V or the intermediate potential is applied to the bit lines according to data. When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory transistor M4, and the potential is injected from the drain to the floating gate. As a result, the threshold value of the selected memory transistor M4 shifts in the positive direction. This state is, for example, “1”. When an intermediate potential is applied to the bit line, electron injection does not occur, so that the threshold value does not change and remains negative. This state is "0".

For data erasing, if the memory transistor M4 is described, the control gate of the memory transistor M4 is set to the ground potential, and the control gates of the memory transistors M1 to M3 on the bit line side and the gate electrode of the selection transistor S1 are connected to a positive high potential. To a positive high potential. At this time, the data is transmitted to the drain of the high-potential memory transistor M4 of the bit line, an electric field opposite to that at the time of writing is applied to the insulating film below the floating gate, and electrons in the floating gate are emitted. As a result, the threshold value of the memory transistor M4 moves in the negative direction.

In the data read operation, a current flows through the selected memory transistor with the control gate of the selected memory transistor set to 0 V and the control gates of the other memory transistors and the gate electrode of the selected transistor set to the power supply potential Vcc (= 5 V). This is performed by detecting whether or not. When the threshold voltage of the selected memory transistor is negative, current flows from the bit line to the common source line, and "0" is output. When the threshold voltage of the memory cell is positive, no current flows, thereby detecting "1".

Note that, depending on how the voltage is applied, batch erasing is also possible.

In such an EEPROM, the portions of the select transistors S1 and S2 provided at both ends of the NAND cell are a major factor that hinders high integration of the memory cell. That is, the first selection transistor S1 on the bit line side functions to select one of the plurality of NAND cells connected to the bit line. Therefore, for example, when erasing data, the gate electrode of the first selection transistor S1 of the unselected NAND cell is grounded so that the high potential applied to the bit line is not transmitted to the memory transistor in the unselected NAND cell. Is done. Therefore, in the selection transistor S1 of this non-selected NAND cell, it is necessary to prevent the punch-through between the drain and the source from occurring, so that the first selection transistor S1
Is usually set longer than that of the memory transistor. In addition, since the first selection transistor S1 on the bit line side uses a stacked gate structure similar to that of the memory transistor for the gate electrode, a step at the bit line contact becomes large, and as a result, the bit line near the contact portion becomes large. The distance between d and the gate electrode 11 (d shown in FIG. 10) is reduced, and a short circuit is likely to occur. In order to prevent this short circuit, it is necessary to sufficiently separate the bit line contact portion and the gate electrode, which also hinders the high integration of the memory cell.

On the other hand, the second selection transistor S2 on the common source line side
Has a function of preventing the intermediate potential applied to the bit line from being transmitted to the common source side at the time of data writing, and therefore requires a sufficient gate length. Further, to reduce the resistance of the common source, a common source line 16 made of Al or the like is used.
Is arranged in contact with the source diffusion layer, a margin is required between the contact portion and the control gate adjacent thereto, and it is difficult to reduce the distance between the common source line and the control gate.

In the case of NOR-type EEPROMs, the select transistor also functions to prevent unnecessary transmission of high potential, so its gate length must be longer than a certain level, which hinders high integration of memory cells. doing.

(Problems to be Solved by the Invention) As described above, in the conventional EEPROM, there is a problem that the portion of the selection transistor that functions to prevent unnecessary transmission of high potential hinders high integration of memory cells. there were.

An object of the present invention is to provide an EEPROM that solves such a problem and enables high integration.

[Configuration of the Invention] (Means for Solving the Problems) An EEPROM according to the present invention is a memory cell having a memory transistor having a structure in which a charge storage layer and a control gate are stacked, and a selection transistor connected in series with the memory transistor. The structure is characterized in that the select transistor has a structure in which a channel region is continuously formed along the bottom surface of the concave portion formed in the substrate and the side surface of the opposing inner wall.

(Operation) According to the present invention, since the selection transistor has a buried gate structure, punch-through breakdown voltage is improved. Further, the area occupied by the select transistor portion can be reduced, and the effective gate length can be increased as compared with the conventional case. Also,
If the concave portion of the select transistor is provided on the drain side to which the bit line is contacted, the gate electrode is buried in the concave portion on the drain side. Therefore, the distance between the bit line contact portion and the select transistor is made smaller than before. Also, a short circuit accident between the gate electrode and the bit line is reliably prevented. As described above, sufficiently high integration of memory cells can be achieved while reliably preventing punch-through and the like.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a plan view showing a NAND cell type EEPROM of the first embodiment. FIG. 2 and FIG. 3 are A-
It is A 'and BB' sectional drawing. Parts corresponding to FIGS. 9 to 11 which are conventional examples are denoted by the same reference numerals. As is clear from the figure, in this embodiment, the NA
A recess 7 is formed on the drain side of the first select transistor S1 on the bit line side of the ND cell, and a channel region is formed along the inner wall of the recess 7. The concave portions 7 are formed separately in the word line direction, that is, separated for each memory cell.

4 (a) to 4 (d) are cross-sectional views showing a manufacturing process corresponding to the cross section of FIG. With reference to this, a specific manufacturing process will be described. Using a p-type silicon substrate (or an n-type silicon substrate with a p-type well formed) 1 and a normal LO
After forming the field oxide film 2 by the COS process, the NAND
A recess 7 is formed in the drain-side select transistor portion of the cell by selective etching (FIG. 4A). The depth of the recess 7 is, for example, about 0.5 μm. Then, the gate insulating film 8 of the select transistor is dried by
Å Form. Then, the oxide film in the memory transistor region is removed by etching, and dry oxidation is performed again at 900 ° C. to form the first gate insulating film 3 of the memory transistor which is a tunnel oxide film of about 100 °. After that, a first-layer polycrystalline silicon film serving as a floating gate (charge storage layer) of the memory transistor is deposited and doped with phosphorus, and then a separation groove (not shown) for separating the floating gate in the word line direction. To process. Then, after forming the second gate insulating films 5 and 10, a second-layer polycrystalline silicon film is deposited and doped with phosphorus. Next, the second layer polycrystalline silicon film to the first layer polycrystalline silicon film are successively selectively etched to form the memory transistor M in the NAND cell.
Control gate 6 and floating gate 4 are formed separately, and at the same time, gate electrodes 11 and 9 of the select transistor S are formed separately (fourth).
Figure (b). The second gate insulating films 5 and 10 may be a thermal oxide film, a silicon oxide film or a silicon nitride film by CVD, or a composite film thereof. The gate electrodes 9 and 11 of the selection transistor S1 and the control gate 6 of the memory transistor M are linearly and continuously patterned with memory cells adjacent in the word line direction. The gate electrodes 9 and 11 of the select transistor S1 are formed in a state of being partially buried in the concave portion 7 as shown. That is, a channel region is formed along the inner wall of the recess 7.

Thereafter, arsenic is ion-implanted to form an n-type layer 12 serving as a source and a drain (FIG. 4C). This ion implantation is performed, for example, at an acceleration voltage of 40 keV and a dose of 10 ¹⁵ / cm ² . After that, a CVD oxide film is deposited as the interlayer insulating film 13,
A contact hole is formed in the hole, and, for example, additional ions of arsenic are implanted into the contact hole. Then, a bit line 14 is provided by vapor deposition and patterning of an Al film (FIG. 4D). Although the common source diffusion layer is formed continuously in the word line direction and serves as a common source line as it is, for example, an Al wiring may be overlaid thereon.

According to this embodiment, as apparent from FIG. 3, the first select transistor S1 on the bit line side has a buried gate structure, so that the punch-through breakdown voltage is high even if the gate length is the same as that of the prior art. . Further, since the recess side wall is also used as a channel, a longer gate length can be obtained with a smaller occupied area. Further, as a result of the burying of the gate electrode, the step in the bit line contact portion is smaller than in the conventional case. Therefore, even if the layout distance between the bit line contact portion and the memory transistor is the same as the conventional one, the substantial distance between the bit line 14 and the gate electrode 11 increases due to the improvement in the coverage of the interlayer insulating film 13. , A short circuit accident between them is reliably prevented. As a result of eliminating a high step at the bit line contact portion, the reliability of the bit line is also improved. As described above, according to this embodiment, it is possible to secure the reliability and achieve high integration of the memory cells.

FIG. 5 is a plan view of a NAND cell type EEPROM according to a second embodiment of the present invention. FIG. 6 is a sectional view taken along the line AA '. In this embodiment, the second selection transistor on the common source side of the NAND cell is formed on the side wall of the concave portion forming the groove 15 that is continuous in the word line direction. Here, the groove 15 is provided commonly to two adjacent NAND cells with the common source line interposed therebetween,
Second select transistor on the source side of these NAND cells
S2 and S3 are formed on opposing side walls of the groove 15.

The specific manufacturing process of the EEPROM of this embodiment will be described with reference to FIGS. 7 (a) to 7 (d). Fig. 7 (a)-
(D) is a process sectional view corresponding to the section of FIG. 6.
After forming the field oxide film 2 as in the previous embodiment,
A groove 15 is formed in a region where the common source line is formed by reactive ion etching (FIG. 7A). The depth of the groove 15 is, for example, about 1.5 μm. Thereafter, as a gate insulating film 8 of the select transistor, an oxide film of 400 ° is formed by dry oxidation at 900 ° C., the oxide film is etched in the memory cell region, and the first gate insulating film 3 is formed again by dry oxidation at 900 ° C. A 100Å tunnel oxide film is formed. Thereafter, a first layer polycrystalline silicon film is deposited, and a second layer polycrystalline silicon film is deposited via a second gate insulating film (FIG. 7B). Before the deposition of the second-layer polycrystalline silicon film, a separation groove for separating the floating gate of the memory cell in the word line direction is formed in the first-layer polycrystalline silicon film as in the previous embodiment. . The first layer polycrystalline silicon film and the second layer polycrystalline silicon film are doped with, for example, phosphorus as an impurity. Thereafter, these laminated polycrystalline silicon films are patterned to separately form the gate electrodes 9 and 10 of the select transistor, the floating gate 4 and the control gate 6 of the memory transistor (FIG. 7 (c)). At this time, the gate electrodes 9 and 10 of the select transistor are formed only on the side wall of the groove 15 as shown in the figure. Thereafter, an n-type diffusion layer 12 serving as a source and a drain is formed by impurity ion implantation, and then a bit line 15 is provided via an interlayer insulating film 13 (FIG. 7 (d)). The common source diffusion layer is formed continuously at the bottom of the groove 15 in the word line direction and serves as a common source line as it is.

According to this embodiment, since the second selection transistor on the common source side is formed using the groove side wall, the punch-through breakdown voltage of this selection transistor is high,
Even if the effective gate length is the same as the conventional one, the occupied area is small. Therefore, also in this embodiment, improvement in reliability and high integration can be achieved.

FIG. 8 is a plan view showing a NAND cell type EEPROM of a third embodiment in which the first and second embodiments are combined.
That is, in this embodiment, the recess 7 is formed in the channel region of the first selection transistor S1 on the drain side in the same manner as in the first embodiment, and the second selection transistor S2 on the common source line side is formed in the second embodiment. Similarly to the above, it is formed on the side wall of the groove 15.

Therefore, according to this embodiment, higher integration of the EEPROM is achieved.

In the above, the embodiment of the NAND cell type EEPROM has been exclusively described. However, the present invention relates to a NOR type EEPROM in which a unit memory cell is constituted by one memory transistor and one select transistor.
The same can be applied to EPROM. In the first and third embodiments, the drain-side select transistor has its gate electrode patterned so that the channel region extends from the inner wall of the recess to the outer flat surface. It may be a structure embedded in.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, by forming a selection transistor in a state of being embedded in a concave portion or a groove,
High integration of EEPROM can be achieved while ensuring punch-through withstand voltage.

[Brief description of the drawings]

FIG. 1 is a plan view showing a NAND cell type EEPROM according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'of FIG. 1, FIG. 4 (a) to 4 (d) are cross-sectional views showing a manufacturing process, FIG. 5 is a plan view showing a NAND cell type EEPROM of the second embodiment, and FIG. 6 is a cross-sectional view taken along line AA 'of FIG. 7 (a) to 7 (d) are cross-sectional views showing a manufacturing process, FIG. 8 is a plan view showing a NAND cell type EEPROM of a third embodiment, and FIG. 9 shows a conventional NAND cell type EEPROM. FIG. 10 is a sectional view taken along the line AA 'of FIG. 9, and FIG. 11 is a sectional view taken along the line BB' of FIG. 1 ... p-type silicon substrate, 2 ... field oxide film, 3
... First gate insulating film, 4... Floating gate, 5.
Gate insulating film, 6 Control gate, 7 Recess, 8, 10
... Gate insulating film, 9 and 11, gate electrode, 12 n-type diffusion layer, 13 interlayer insulating film, 14 bit line, 15 groove.

Claims (4)

(57) [Claims] 1. A semiconductor substrate, at least one memory transistor in which a charge storage layer and a control gate are formed on the substrate via a gate insulating film, and a bottom surface of a concave portion formed in the substrate and opposed to each other. A non-volatile semiconductor memory device comprising: at least one select transistor having a channel region formed continuously along an inner wall side surface and connected in series with the memory transistor. 2. A semiconductor substrate, and a charge storage layer and a control gate are formed on the substrate via a gate insulating film, respectively, and are connected in series so that adjacent ones share a source / drain diffusion layer. NAND
A plurality of memory transistors constituting a memory cell, and a channel region is formed continuously along the bottom of the recess formed in the substrate and the side surface of the inner wall facing the drain, and the drain diffusion at one end of the plurality of memory transistors is performed. And a select transistor provided between the layer and the bit line. 3. A semiconductor substrate, and a charge storage layer and a control gate are formed on the substrate via a gate insulating film, and are connected in series so that adjacent ones share a source and drain diffusion layer. NAND
A plurality of memory transistors forming a type memory cell; a first select transistor formed on the substrate and provided between a bit line and a drain diffusion layer at one end of the memory cell; A channel region is formed on at least the inner wall of the recess formed in the memory cell, and is provided between a source diffusion layer on the other end side of the memory cell and a common source line including an impurity diffusion layer formed below the bottom of the recess. A second selection transistor connected to two memory cells adjacent to each other with the common source line interposed therebetween, wherein the second selection transistors are opposed to each other in the recess formed between the two memory cells. A non-volatile semiconductor memory device formed on each of the inner wall portions. 4. The first selection transistor according to claim 3, wherein a channel region is continuously formed along a bottom surface of the concave portion formed on the substrate and a side surface of the opposing inner wall. Nonvolatile semiconductor memory device.