JP2970858B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] relates to a semiconductor integrated circuit device, in particular, the capacitor and the MISFET on the same substrate (M etal I nsulator S emicon
when applied to a semiconductor integrated circuit device having a ductor F ield E ffect T ransistor) and a technique effective.

[Conventional technology]

2. Description of the Related Art A semiconductor integrated circuit device having an analog circuit and a digital circuit on the same substrate is known. This kind of semiconductor integrated circuit device, and a capacitive element and a resistive element to the A / D converter that performs analog processing, MOSFET that performs analog processing and digital processing (M etal O xide S emiconductor F ield
E ffect T ransistor) with a ".

The capacitive element that constitutes the A / D converter mainly includes a first electrode, a dielectric film, and an insulating film (eg, a field insulating film).
Each of the second electrodes has a laminated structure in which the second electrodes are sequentially laminated. A capacitance element having a laminated structure has smaller voltage dependency than a pn junction and a MOS capacitor, and is suitable for high-accuracy analog processing. Examples of the dielectric film of the capacitive element having the laminated structure include, for example, IED 88, pages 782 to 785 (IEDM88, pp. 782 to 78).
As described in 5), a single-layer structure formed of a silicon oxide film, a three-layer structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked, and a silicon oxide film formed on a silicon nitride film It is composed of one of two laminated layers.

When the dielectric film of the capacitive element has a single-layer structure,
The semiconductor integrated circuit device is formed by a first manufacturing method shown in FIGS. 7A to 7C (a cross-sectional view of a main part in each manufacturing process).

First, it made of single-crystal silicon p ^- type first region of a semiconductor substrate 1 of the main surface (capacitor region) in n-type well region 2, p ^-
Region (MO) different from the first region of the main surface of the semiconductor substrate 1
Each of the p-type well regions 3 is formed in the (SFET formation region).
Thereafter, using a selective oxidation method, a field insulating film (element isolation) is formed in the entire region on the main surface of the n-type well region 2 in the first region and in the inactive region on the main surface of the p-type well region 3 in the second region. An insulating film) 4 and a p-type well region 3 of a second region.
A p ⁺ type semiconductor region (channel stopper region) 5 is formed under the field insulating film 4 in the main surface portion of FIG. After this,
An insulating film 6 made of a silicon oxide film is formed on the main surface of the active region of the p-type well region 3 by using a thermal oxidation method.

Next, a polycrystalline silicon film is deposited on the entire surface of the substrate including the field insulating film 4 and the insulating film 6 by a CVD method. Impurities for reducing the resistance value are introduced into the polycrystalline silicon film during or after the deposition. Thereafter, using a photoresist film having a predetermined mask pattern as an etching mask, the polycrystalline silicon film is patterned to form a capacitive element on the field insulating film 4 in the first region as shown in FIG. 7A. The first electrode C1 is formed.

Next, the entire surface of the substrate is etched to remove the insulating film 6 on the second region, exposing the surface of the p-type well region 3 in the second region. The etching is performed by etching at a higher etching rate of the silicon oxide film than the polycrystalline silicon film. Thereafter, using a thermal oxidation method, a dielectric film C2 formed of a silicon oxide film on the first electrode C1 in the first region and a silicon oxide film on the active region of the p-type well region 3 in the second region. Each of the formed gate insulating films 14 is simultaneously formed. The silicon oxide film formed on the first electrode C1 (polycrystalline silicon) by the thermal oxidation method has a smaller leakage current than the silicon oxide film formed on the p-type well region 3 (single crystal silicon) by the thermal oxidation method. The thermal oxidation method is about 1000 to 1100
This is performed at a high temperature of about ° C. to improve the quality of the dielectric film C2 formed on the first electrode C1. Thereafter, as shown in FIG. 7B, the threshold voltage (Vth) of the MOSFET is adjusted (controlled) on the main surface of the active region of the p-type well region 3 of the second region.
A type impurity 12 (for example, boron (B)) is introduced. (B)
Is a gate insulating film on the second region using an ion implantation method.
Through 14, it is introduced into the main surface of the p-type well region 3. This p-type impurity 12 is diffused in the above-described high-temperature thermal oxidation step, and is introduced after this thermal oxidation step, that is, after the gate insulating film 14 is formed, in order to prevent the impurity profile from becoming broad.

Next, for example, a polycrystalline silicon film is deposited on the entire surface of the substrate including the dielectric film C2 and the gate insulating film 14 by a CVD method. Impurities for reducing the resistance value are introduced into the polycrystalline silicon film during or after the deposition. Thereafter, the polycrystalline silicon film is patterned to form a second electrode C3 on the dielectric film C2 and a gate electrode 15 on the gate insulating film 14 at the same time. By forming the second electrode C3, the capacitance element C
Is completed.

Next, using the gate electrode 15 as an impurity introduction mask, an n-type impurity is introduced into the main surface of the p-type well region 3 in the second region, and then a thermal diffusion process is performed to perform a pair of the source region and the drain region. The n ⁺ semiconductor region 16 is formed. By forming this n ⁺ type semiconductor region 16, an n-channel MOSFET Qn is formed as shown in FIG. 7C. Although not shown, the p-channel MOSFET is formed on the main surface of the n-type well region 2 in a third region different from each of the first region and the second region.

Next, in the case where the dielectric film of the capacitive element has a three-layer structure, the semiconductor integrated circuit device is manufactured in the second manufacturing process shown in FIGS. 8A to 8C (a cross-sectional view of a main part in each manufacturing process). Formed by the method.

First, similarly to the above-described first manufacturing method, an n-type well region 2 and a p-type well region 3 are respectively formed on a main surface of a p ⁻ type semiconductor substrate 1. Thereafter, the field insulating film 4 and the p ⁺ type semiconductor region 5 are formed. Thereafter, an insulating film 6 is formed in the active region of the p-type well region 3 in the second region.

Next, a polycrystalline silicon film is deposited on the entire surface of the substrate including the field insulating film 4 and the insulating film 6. Thereafter, a silicon oxide film formed on the polycrystalline silicon film by a thermal oxidation method,
A silicon nitride film deposited by a method and a silicon oxide film formed by applying a thermal oxidation method to the surface of the silicon nitride film are sequentially laminated. Thereafter, the upper silicon oxide film, the silicon nitride film, the lower silicon oxide film, and the polycrystalline silicon film are sequentially patterned, and in the first region, the field insulating film 4 is formed.
A first electrode C1 and a three-layer dielectric film C2 formed of a lower silicon oxide film 7, a silicon nitride film 8, and an upper silicon oxide film 9 are formed thereon.

Next, as shown in FIG. 8A, a p-type impurity for adjusting the threshold voltage of the MOSFET is formed on the main surface of the p-type well region 3 in the second region.
12 is introduced through the insulating film 6.

Next, in a first region, a photoresist film 30 covering the dielectric film C2 is formed. This photoresist film 30 is used as an etching mask. Thereafter, as shown in FIG. 8B, using the photoresist film 30 as an etching mask, the insulating film 6 on the second region is removed, and the surface of the p-type well region 3 in the second region is exposed. The photoresist film 30 is formed for the purpose of preventing the silicon oxide film 9 on the dielectric film C2 from being removed when the insulating film 6 is removed.

Next, after the photoresist film 30 is removed, a thermal oxidation method is performed to form a gate insulating film 14 in the active region of the p-type well region 3 in the second region, as shown in FIG. 8C. The growth rate of the silicon oxide film formed in p-type well region 3 (single-crystal silicon) is much higher than the growth rate of the silicon oxide film formed on the surface of silicon nitride film 8. For this reason, a silicon oxide film having an optimum thickness cannot be formed at the same time for both, so that the upper silicon oxide film 9 on the silicon nitride film 8 of the capacitor C is formed before the step of forming the gate insulating film 14. Are formed in the gate insulating film 14 by an independent manufacturing process.

Next, similarly to the above-described first manufacturing method, a second electrode C3 is formed on the dielectric film C2 in the first region, and a gate electrode 15 is formed on the gate insulating film 14 at the same time. This second electrode C3
Is formed, the capacitive element C is completed.

Next, a pair of n ⁺ -type semiconductor regions 16 as a source region and a drain region are formed in the main surface of the p-type well region 3 in the second region. By forming the n ⁺ type semiconductor region 16, the n-channel MOSFET Qn is completed as shown in FIG. 8D.

In the case where the dielectric film of the capacitive element has a three-layer structure, the semiconductor integrated circuit device is manufactured by using a third manufacturing method shown in FIGS. 9A to 9D (a cross-sectional view of a main part in each manufacturing process). Formed by

First, similarly to the above-described second manufacturing method, an n-type well region 2 and a p-type well region 3 are formed in a p ⁻ type semiconductor substrate 1. Thereafter, the field insulating film 4, the p ⁺ type semiconductor region 5, and the insulating film 6 are formed. After that, the first electrode C1 is formed on the field insulating film 4 in the first region.

Next, a thermal oxidation method is performed to form a silicon oxide film 7 on the first electrode C1.
To form Thereafter, the silicon oxide film 7 and the insulating film 6
A silicon nitride film (8) is deposited on the entire surface of the substrate including the upper surface by, for example, a CVD method, and subjected to a thermal oxidation method. As shown in FIG. 9A, a silicon oxide film (9) is formed on the silicon nitride film (8). Form.

Next, a photoresist film covering the first electrode C1 in the first region
Using the photoresist film 30 as an etching mask, the silicon oxide film (9) and the silicon nitride film (8) are sequentially patterned to form a capacitor element as shown in FIG. 9B. Each of a silicon nitride film 8 and a silicon oxide film 9 used as a C dielectric film is formed,
The insulating film 6 in the region is removed by etching to expose the surface of the p-type well region 3 in the second region. Through this step, a dielectric film C2 having a three-layer structure composed of the upper silicon oxide film 9, the silicon nitride film 8, and the lower silicon oxide film 7 is formed.
Thereafter, similarly to the above-described second manufacturing method, a gate insulating film 14 is formed on the main surface of the p-type well region 3 in the second region as shown in FIG. Introduce 12. Then, as shown in FIG. 9D, the second electrode
C3 is formed to complete the capacitive element C, and at the same time, the gate electrode 15 and the n ⁺ type semiconductor region 16 are formed in the second region, thereby completing the n-channel MOSFET Qn.

The manufacturing method when the dielectric film of the capacitive element mounted on the semiconductor integrated circuit device has a two-layer structure is substantially the same as the above-described second or third manufacturing method. Omitted.

[Problems to be solved by the invention]

As a result of studying the method of manufacturing the semiconductor integrated circuit device, the present inventors have found the following problems.

In a first manufacturing method in which a dielectric film of a capacitor mounted on the semiconductor integrated circuit device has a single-layer structure, a dielectric film C2 formed on a first electrode C1 of the capacitor C is provided.
Is a gate insulating film formed on the main surface of the p-type well region 3
Since the electrical characteristics are poor as compared with 14, the high-temperature thermal oxidation method of about 1000 to 1100 ° C. is performed to improve the quality of the dielectric film C2.
However, while the quality of the dielectric film C2 is improved, the quality of the gate insulating film 14 formed in the same step as that of the dielectric film C2 is deteriorated by the high-temperature heat treatment.

Further, the impurity 12 for adjusting the threshold voltage of the MOSFET is introduced through the gate insulating film 14 after forming the gate insulating film 14 in order to prevent the introduced impurity 12 from broadening the impurity concentration distribution due to the high-temperature thermal oxidation process. Have been. But,
The introduction of the impurity 12 causes physical damage to the gate insulating film 14 and deteriorates the film quality of the gate insulating film 14.

Further, in each of the second and third manufacturing methods when the dielectric film of the capacitive element mounted on the semiconductor integrated circuit device has a three-layer structure, the silicon nitride film of the dielectric film C2 of the capacitive element C The silicon oxide film 9 formed on the gate insulating film 8 and the gate insulating film 14 formed on the main surface of the p-type well region 3 are formed in separate steps because there is a large difference in the growth rate of the silicon oxide film. ing. That is, before the gate insulating film 14 is formed, the silicon oxide film 9 is formed on the silicon nitride film 8, and the silicon oxide film 9 is covered with an etching mask formed of the photoresist film 30, and this etching mask is used. And p in the second region
After removing the insulating film 6 in the p-type well region 3, exposing the surface of the p-type well region 3 and removing the photoresist film 30, a gate insulating film 14 is formed on the exposed surface of the p-type well region 3. Is formed. However, if the surface of the p-type well region in the second region is exposed using the photoresist film 30 as an etching mask, the exposed surface becomes
And the contaminants contained in the developer and the stripper, the contaminants are taken in during the formation of the gate insulating film 14, and the film quality of the gate insulating film 14 is deteriorated.

In addition, the silicon oxide film 9 on the dielectric film C2 of the capacitive element C
Is contaminated by forming the photoresist film 30,
The film quality of the dielectric film C2 decreases.

An object of the present invention is to improve the film quality of a dielectric film of the capacitor and a gate insulating film of the MISFET in a semiconductor integrated circuit device having a capacitor and a MISFET on the same substrate, thereby improving electrical reliability. It is to provide a technology that can do it.

Another object of the present invention is to provide a technique capable of achieving the above object and reducing the manufacturing process of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the additional drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

(1) A capacitor in which a first electrode, a dielectric film, and a second electrode are sequentially stacked on a first region of a main surface of a semiconductor substrate with an insulating film interposed therebetween, and a first element of the main surface of the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device having a MISFET having a gate electrode formed on a second region different from the region with a gate insulating film interposed therebetween, wherein a first insulating film is formed in a first region on a main surface of the semiconductor substrate; Forming a second insulating film in each of the two regions, sequentially stacking a first electrode and a dielectric film on the first insulating film in the first region, and using the dielectric film as a mask Removing the second insulating film in the second region, forming a third insulating film on the second region on the main surface of the semiconductor substrate using the dielectric film as a mask, Impurities for adjusting the threshold voltage are passed through the third insulating film in the second region on the main surface of the semiconductor substrate. And removing the third insulating film in the second region using the dielectric film as a mask, and removing the third insulating film in the second region using the dielectric film as a mask in the second region on the main surface of the semiconductor substrate. Forming a second electrode on the dielectric film and forming a gate electrode on the gate insulating film using the same conductive layer.

(2) a capacitor in which a first electrode, a dielectric film, and a second electrode are sequentially laminated on a first region of a main surface of a semiconductor substrate with an insulating film interposed therebetween; A method for manufacturing a semiconductor integrated circuit device having a MISFET having a gate electrode formed on a second region different from the region with a gate insulating film interposed therebetween, wherein a first insulating film is formed on a first region on a main surface of the semiconductor substrate; Forming each of the second insulating films on the second region;
A step of sequentially laminating a first electrode and a dielectric film on the first insulating film, and a step of forming a second region on the main surface of the semiconductor substrate.
Introducing a threshold voltage adjusting impurity through an insulating film, and using the dielectric film of the capacitor as a mask,
Removing the second insulating film on the second region; forming a gate insulating film on the second region on the main surface of the semiconductor substrate using the dielectric film as a mask; Forming a second electrode on the body film and a gate electrode on the gate insulating film with the same conductive layer.

(3) The step (1) or (2) of forming a dielectric film is a step of sequentially stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film, and removing the second insulating film. The step of removing the silicon oxide film and the second insulating film on the silicon nitride film using the silicon nitride film of the dielectric film as a mask.

[Action]

According to the above means (1), each of the second insulating film and the third insulating film formed in the second region of the main surface of the semiconductor substrate is removed by using the dielectric film without using the photoresist film. Accordingly, the surface of the semiconductor substrate on the second region can be prevented from being contaminated in the photoresist film forming step, and the film quality of the gate insulating film formed on the second region can be improved.

Further, since the gate insulating film is formed after introducing the threshold voltage adjusting impurity on the second region on the main surface of the semiconductor substrate, it is possible to prevent deterioration of the film quality of the gate insulating film due to the introduction of the impurity. it can.

In addition, after forming a dielectric film of a capacitor, a gate insulating film is formed by an independent process, a dielectric film is formed by a high-temperature heat treatment, and a gate insulating film is formed by a low-temperature heat treatment. Therefore, the quality of the dielectric film and the gate insulating film can be improved.

According to the means (2) described above, the effect of the means (1) is obtained, and a threshold voltage adjusting impurity is introduced by using the second insulating film in the second region. Since the step of forming the third insulating film can be omitted, the manufacturing process can be reduced.

According to the above means (3), since the pinholes in the silicon nitride film of the dielectric film of the capacitor can be filled with the upper silicon oxide film, the film quality of the dielectric film can be improved.

In addition, since contaminants in the silicon nitride film of the dielectric film or the surface of the capacitor element are introduced into the upper silicon oxide film and the silicon oxide film is removed, the quality of the dielectric film can be improved.

Therefore, the electrical reliability of the semiconductor integrated circuit device can be improved.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having an analog circuit and a digital circuit on the same substrate.

In all the drawings for describing the embodiments, those having the first function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Example of the invention)

FIG. 1 is a schematic cross-sectional view of a semiconductor integrated circuit device having an analog circuit and a digital circuit on the same substrate according to an embodiment of the present invention. ).

As shown in FIGS. 1 and 2, the semiconductor integrated circuit device includes a capacitive element C on a first region (left side in FIG. 1) of a main surface of ap ⁻ type semiconductor substrate 1 made of, for example, single crystal silicon. , the p ^-
MISFETQn and p-channel on a second region (right side in FIG. 1) different from the first region on the main surface of the semiconductor substrate 1.
Each of the MISFETs Qp is formed. The capacitive element C constitutes an A / D converter for performing analog processing, and the MISFETQn, MIS
Each of the FETQp performs analog processing and digital processing.

The capacitive element C is formed on an n-type well region 2 formed on a main surface of a p ^- type semiconductor substrate 1 with a field insulating film 4 interposed therebetween, and includes a first electrode C1, a dielectric film C2, a second electrode It has a laminated structure in which each of C3 is sequentially laminated.

The first electrode C1 is formed of, for example, a polycrystalline silicon film, and an impurity for reducing a resistance value is introduced into the polycrystalline silicon film. The dielectric film C2 has a three-layer structure in which an insulating film 7, an insulating film 8, and an insulating film 13 are sequentially stacked. The insulating film 7 is a silicon oxide film formed by oxidizing the surface of the first electrode C1 by a thermal oxidation method. This insulating film 7 is formed on the first electrode C1 and on the side wall thereof. The insulating film 8 is, for example, a silicon nitride film deposited by a CVD method. The insulating film 13 is a silicon oxide film formed by oxidizing the surface of the insulating film 8 by a thermal oxidation method. The second electrode C3 is formed of, for example, a polycrystalline silicon film similarly to the above-mentioned first electrode C1, and an impurity for reducing a resistance value is introduced into the polycrystalline silicon film.

The n-channel MISFET Qn is formed in the p-type well region 3 formed on the main surface of the p ⁻ -type semiconductor substrate 1 in a region surrounded by the field insulating film 4 and the p-type semiconductor region (channel stopper region) 5. It is configured on the main surface. That is, the n-channel MISFET Qn includes a p-type well region (channel forming region) 3, a gate insulating film 14, a gate electrode 15, and a pair of n ⁺ -type semiconductor regions serving as a source region and a drain region.
It consists of 16.

The p-channel MISFET Qp is the n-channel MISFET described above.
Like the Qn, it is formed on the main surface of the n-type well region 2 in a region surrounded by the field insulating film 4.
That is, the p-channel MISFET Qp is composed of an n-type well region (channel formation region) 2, a gate insulating film 14, a gate electrode
15, a pair of p ⁺ -type semiconductor regions 17 serving as a source region and a drain region.

The gate insulating film 14 is formed by p-type well regions 3 by thermal oxidation.
This is a silicon oxide film formed by oxidizing each main surface of the n-type well region 2. The gate electrode 15 is the second electrode C3 described above.
And the same conductive layer. That is, the gate electrode 15
Like the above-mentioned second electrode C3, it is formed of, for example, a polycrystalline silicon film, and an impurity for reducing the resistance value is introduced into this polycrystalline silicon film. The second electrode C3 and the gate electrode 15
Is formed of a polycrystalline silicon film in this embodiment, and tungsten silicide (WS
i _x) a refractory metal silicide film such as a film may be formed of a laminated film formed by laminating.

The n ⁺ -type semiconductor region 16 of the n-channel MISFET Qn is electrically connected to an aluminum alloy wiring 20 through a connection hole 19a formed in the insulating film 18. Similarly, the aluminum alloy wiring 20 is electrically connected to the p ⁺ type semiconductor region 17 of the p-channel MISFETQp. The first electrode C1 of the capacitor C is electrically connected to the aluminum alloy wiring 20 through a connection hole 19c formed in the insulating film 18. The second electrode C3 of the capacitor C is electrically connected to the aluminum wiring 20 through a connection hole 19b formed in the insulating film 18.

Next, a method for manufacturing the semiconductor integrated circuit device will be described.
This will be specifically described with reference to FIGS. 3A to 3F (a cross-sectional view of a main part shown in each manufacturing process).

First, a p ^- type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, an n-type impurity is introduced into the first region of the main surface of the p ⁻ -type semiconductor substrate 1 and a p-type impurity and an n-type impurity are introduced into the second region by ion implantation (or thermal diffusion), respectively. subjected to diffusion treatment, p ^- -type first region of the semiconductor substrate 1 of the main surface (capacitor region) in n-type well region 2, p ^- -type second region (MISFET formation region) of the main surface of the semiconductor substrate 1 Then, a p-type well region 3 and an n-type well region 2 are respectively formed. Thereafter, a field insulating film 4 is formed on a main surface of each of the n-type well region 2 and the p-type well region 3 serving as an inactive region by a known selective oxidation method. The p ⁺ type semiconductor region 5 is formed in the non-active region on the surface. After this,
By performing a thermal oxidation process, as shown in FIG. 3A, in the second region, an insulating film formed of a silicon oxide film on the active regions on the respective main surfaces of the n-type well region 2 and the p-type well region 3 6 is formed.

Next, for example, a polycrystalline silicon film is deposited on the entire surface of the substrate including the field insulating film 4 and the insulating film 6 by a CVD method.
An impurity (for example, an n-type impurity) that reduces the resistance value during or after the deposition is introduced into the polycrystalline silicon film.
Thereafter, a thermal oxidation process at about 900 to 1100 ° C. is performed to form a silicon oxide film (7) on the polycrystalline silicon film for about 10 to 15 minutes.
It is formed with a thickness of about [nm]. Thereafter, a silicon nitride film (8) is formed on the entire surface of the silicon oxide film (7) by, for example, a CVD method.
Is formed to a thickness of about 15 to 30 [nm]. After this, about 90
A thermal oxidation process is performed in an oxidizing atmosphere at about 0 to 1000 ° C. to form a thin silicon oxide film (9) on the silicon nitride film (8). In this thermal oxidation process, the pinholes generated on the surface of the silicon nitride film (8) are buried, and contaminants in the silicon nitride film (8) or contaminants on the surface are taken into the silicon oxide film (9). Therefore, the dielectric strength of the silicon nitride film (8) can be improved, the amount of leak current can be reduced, and the film quality of the silicon nitride film (8) can be improved.

Next, a photoresist film covering the capacitive element formation region
Using the photoresist film 30 as an etching mask, the silicon oxide film (9), the silicon nitride film (8), the silicon oxide film (7), and the polycrystalline silicon film are sequentially patterned. As shown in FIG. 3B, a first electrode C1, an insulating film 7, an insulating film 8, and an insulating film 9 are formed on the field insulating film 4. The insulating films 7 and 8 formed in this step each constitute a dielectric film C2.

Next, after the photoresist film 30 is removed, wet etching is performed, and the p-type well region 3 on the second region is removed.
The respective insulating films 6 in the n-well region 2 are removed, and as shown in FIG. 3C, the surfaces of the p-type well region 3 and the n-type well region 2 serving as the active regions in the second region are exposed. At this time, in the capacitor element forming region, the insulating film 8 of the dielectric film C2 is formed.
The upper insulating film 9 is also removed, and the insulating film 8 of the dielectric film C2 is used as an etching mask. Thereby, the silicon oxide film (insulating film 9) in which the contaminants in the silicon nitride film (insulating film 8) are taken can be removed, so that the quality of the dielectric film C2 can be improved.

Next, a thermal oxidation process is performed to form an insulating film 11 made of a silicon oxide film on each surface of the p-type well region 3 and the n-type well region 2 exposed in the second region. In this step, a thin insulating film 10 made of a silicon oxide film is formed on the insulating film 8 of the dielectric film C2, and a silicon oxide film is formed on the side wall of the first electrode C1. The formed insulating film 7 is formed.

Next, as shown in FIG. 3D, an insulating film is formed on each active region of the p-type well region 3 and the n-type well region 2 of the second region.
Through 11, for example, a p-type impurity (for example, boron (B)) 12 for adjusting (controlling) the threshold voltage (Vth) of the MISFET is introduced. This p-type impurity is introduced by an ion implantation method. In this embodiment, after the insulating film 6 is removed as described above, the insulating film 11 is formed again, and the p-type impurity 12 is introduced into the second region through the insulating film 11. The p-type impurity 12 may be introduced into the second region through the insulating film 6 without removing the layer 6. In this case, in the manufacturing process of the semiconductor integrated circuit device, the number of steps can be reduced by an amount corresponding to the step of removing the insulating film 6 and the step of forming the insulating film 11.

Next, wet etching is performed on the entire surface of the substrate, and as shown in FIG. 3E, the insulating film 11 on the second region is removed.
The surface of each active region of the p-type well region 3 and the n-type well region 2 of the second region is exposed. At this time, the insulating film 10 on the insulating film 8 of the dielectric film C2 of the capacitor is also removed, and the insulating film 8 of the dielectric film C2 is used as an etching mask.

Next, a thermal oxidation process at a low temperature of about 800 to 900 ° C. is performed to form a gate formed of a silicon oxide film on each of the p-type well region 3 and the n-type well region 2 of the second region. The insulating film 14 is formed with a thickness of about 15 to 20 [nm]. At this time, the surface of the insulating film 8 of the dielectric film C2 is also oxidized, and an insulating film 13 formed of a thin silicon oxide film is formed on the insulating film 8 to a film thickness of about 1-2 nm. It is formed with a thickness. By this step, a dielectric having a three-layer structure in which the insulating film 7 formed of a silicon oxide film, the insulating film 8 formed of a silicon nitride film, and the insulating film 13 formed of a silicon oxide film are sequentially stacked, respectively. Membrane C2
Is formed.

Next, for example, a polycrystalline silicon film is deposited on the entire surface of the substrate including the insulating film 13 and the gate insulating film 14 by a CVD method. An impurity for reducing the resistance value is introduced into the polycrystalline silicon film. Thereafter, the polycrystalline silicon film is patterned to form a second electrode C3 on the insulating film 13 in the first region and a gate electrode 15 on the gate insulating film 14 in the second region.
By this step, the first electrode C1, the dielectric film C2, the second electrode C3
Is completed.

Next, using the gate electrode 15 as an impurity introduction mask, an n-type impurity is formed on the main surface of the active region of the p-type well region 3 of the second region, and a p-type impurity is formed on the main surface of the active region of the n-type well region 2. 3F, a pair of n ⁺ -type semiconductor regions 16 that are a source region and a drain region and a pair of p ⁺ -type regions that are a source region and a drain region, as shown in FIG. 3F. A semiconductor region 17 is formed. By this step, the n-channel MISFETQn and the p-channel MISF
ETQp is completed.

Next, an insulating film 18 formed of a silicon oxide film deposited by a CVD method is formed on the entire surface of the substrate, and the insulating film 18 has connection holes 19a, 19
After forming each of b and 19c, the aluminum alloy wiring 20 is connected to each region through each of the connection holes 19a, 19b and 19c. Thereby, as shown in FIGS. 1 and 2, the capacitor C, the n-channel MISFETQn,
A semiconductor integrated circuit device having each of the channel MISFETs Qp is almost completed.

As described above, the first electrode C1 and the dielectric film C are formed on the first region of the main surface of the p ^- type semiconductor substrate 1 with the field insulating film 4 interposed therebetween.
2. A capacitive element C in which each of the second electrodes C3 is sequentially laminated, and a gate electrode 15 on a second region different from the first region on the main surface of the p ⁻ type semiconductor substrate 1 with a gate insulating film 14 interposed therebetween. Formed
In a method of manufacturing a semiconductor integrated circuit device having MISFETs Qn or Qp, a field insulating film 4 and a second region (n-type well region) are formed on a main surface of a first region (n-type well region 2) of the p ⁻ -type semiconductor substrate 1. 2, a step of forming each of the insulating films 6 on the main surface of each of the p-type well regions 3), and a step of sequentially laminating each of the first electrode C1 and the dielectric film C2 on the field insulating film 4 in the first region. Removing the insulating film 6 on the second region using the dielectric film C2 as a mask, and removing the insulating film 6 on the second region (p) using the dielectric film C2 as a mask.
Insulating film on each of the n-type well region 3 and the n-type well region 2)
Forming an insulating film 11 on the second region using the dielectric film C2 as a mask, forming a threshold voltage adjusting impurity 12 through the insulating film 11 in the second region; Removing, a step of forming a gate insulating film 14 on the second region using the dielectric film C2 as a mask, and a step of forming a second electrode C3 and the gate insulating film 14 on the dielectric film C2. Forming each of the gate electrodes 15 with the same conductive layer. As a result, each of the insulating film 6 and the insulating film 11 formed on the second region is removed by using the dielectric film C2 without using a photoresist film, so that the p-type well region 3 in the second region is removed. The surface of each active region of the n-type well region 2 can be prevented from being contaminated by the photoresist film forming process, and the film quality of the gate insulating film 14 formed on the second region can be improved. it can.

Further, since the gate insulating film 14 is formed by a low-temperature thermal oxidation process after the introduction of the threshold voltage adjusting impurity 12 into the second region, the impurity concentration distribution of the threshold voltage adjusting impurity 12 is reduced. While being able to prevent becoming broad,
Gate insulating film by introducing impurity 12 for adjusting threshold voltage
The deterioration of the film quality due to the 14 physical damages can be prevented.

After the dielectric film C2 of the capacitor C is formed, the gate insulating film 14 is formed thereon by an independent process, and the dielectric film C2 is formed.
The lower insulating film (silicon oxide film) 7 is formed by a high-temperature thermal oxidation process, and the gate insulating film 14 is formed by a low-temperature thermal oxidation process.
In addition, the film quality of the gate insulating film 14 can be improved.

In the method for manufacturing a semiconductor integrated circuit device,
The step of forming the dielectric film C2 is a step of sequentially stacking an insulating film 7 formed of a silicon oxide film, an insulating film 8 formed of a silicon nitride film, and an insulating film 13 formed of a silicon oxide film. And the step of removing the insulating film 6 includes the step of removing the dielectric film
In this step, the insulating film 9 and the insulating film 6 on the insulating film 8 are removed using the C2 insulating film 8 as a mask. Accordingly, pinholes generated in the insulating film 8 of the dielectric film C2 of the capacitor C can be buried, so that the quality of the dielectric film C2 can be improved.

In addition, contaminants in or on the insulating film 8 of the dielectric film C2 of the capacitive element C are taken into the insulating film 9 or the insulating film 10,
Since the insulating film 9 or the insulating film 10 has been removed, the dielectric film C2
Film quality can be improved.

Therefore, the electrical reliability of the semiconductor integrated circuit device can be improved.

Next, a schematic configuration of a semiconductor integrated circuit device in which an analog circuit and a digital circuit are mounted on the same substrate according to another embodiment of the present invention is shown in FIG.

The capacitive element C mounted on the semiconductor integrated circuit device shown in FIG. 4 includes a first electrode C1 and a dielectric film as in the above-described embodiment.
It has a laminated structure in which C2 and the second electrode C3 are sequentially laminated. The dielectric film C2 of the capacitive element C is composed of an insulating film 7,
The first electrode is composed of a laminated structure in which each of 8 and 13 is laminated.
It is formed along the upper surface of C1 and the side wall around the first electrode C1.

Next, a method for manufacturing the semiconductor integrated circuit device will be described.
A brief description will be given with reference to FIGS. 5A to 5D (cross-sectional views of main parts shown in respective manufacturing steps).

First, similarly to the above-described embodiment, a p-type well region 3 and an n-type well region 2 are formed on the main surface of the p ⁻ type semiconductor substrate 1.

Next, a field insulating film 4 is formed in each of the non-active regions of the n-type well region 2 of the first region, the p-type well region 3 of the second region, and the n-type well region 2, and the p-type region of the second region is formed. A p ⁺ type semiconductor region 5 is formed in a non-active region on the main surface of the type well region 3. Thereafter, a thermal oxidation process is performed to form an insulating film 6 in each of the active regions of the p-type well region 3 and the n-type well region 2 of the second region.

Next, after a first electrode C1 is formed on the field insulating film 4 in the first region, a high-temperature thermal oxidation process is performed to form an insulating film formed of a silicon oxide film on the first electrode C1 and on the side wall. 7 is formed.

Next, a silicon nitride film (8) is deposited on the entire surface of the substrate including the insulating film 7 and the insulating film 6 by, for example, a CVD method. Thereafter, a thermal oxidation treatment is performed in an oxidizing atmosphere to form a silicon oxide film (9) on the silicon nitride film (8) as shown in FIG. 5A.
To form In this thermal oxidation step, similarly to the above-described embodiment, the pinholes of the silicon nitride film (8) are buried and contaminants of the silicon nitride film (8) are taken into the silicon oxide film (9). Therefore, the film quality of the silicon nitride film (9) can be improved.

Next, a photoresist film 30 is formed to cover all of the upper surface and the side wall of the first electrode in the first region, and using the photoresist film 30 as an etching mask, the silicon oxide film (9), silicon nitride Each of the films (8) is sequentially etched to form an insulating film 8 and an insulating film 9 on the insulating film 7, respectively. Each of the insulating film 8 and the insulating film 9 formed in this step is patterned with a plane size larger than the first electrode C1 by at least an amount corresponding to a mask alignment margin in a manufacturing process. By this step, each of the insulating film 7 and the insulating film 8 constituting the dielectric film C2 is formed.

Next, after the photoresist film 30 is removed, as shown in FIG. 5B, a threshold voltage is passed through the insulating film 6 to each of the active regions of the p-type well region 3 and the n-type well region 2 of the second region. For example, a p-type impurity 12 for adjusting the voltage (Vth) is introduced. The step of introducing the p-type impurity 12 can be performed through the insulating film 11 after removing the insulating film 6 and forming the insulating film 11 again on the second region, as in the above-described embodiment. Good.

Next, as in the above-described embodiment, wet etching is performed on the entire surface of the substrate to remove the insulating film 6 on the second region.
As shown in FIG. 5C, the surfaces of the active regions of the p-type well region 3 and the n-type well region 2 of the second region are exposed. At this time, the insulating film 9 on the insulating film 8 of the dielectric film C2 is also removed, and the insulating film 8 of the dielectric film C2 is used as an etching mask. Thereby, the silicon oxide film (insulating film 9) in which the contaminants in the silicon nitride film (insulating film 8) are taken can be removed, so that the quality of the dielectric film C2 can be improved.

Next, similarly to the above-described embodiment, a low-temperature thermal oxidation treatment is performed to form a gate insulating film 14 in each of the active regions of the p-type well region 3 and the n-type well region 2 of the second region. In this thermal oxidation process, a thin insulating film 13 is also formed on the insulating film 8 of the dielectric film C2. Thereafter, similarly to the above-described embodiment, by forming the second electrode C3, the gate electrode 15, the n ⁺ -type semiconductor region 16, and the p ⁺ -type semiconductor region 17, as shown in FIG. Capacitance element C, n channel
A semiconductor integrated circuit device having MISFETQn and p-channel MISFETQp is almost completed.

As described above, according to the manufacturing method of the present embodiment, the first electrode
A high-quality dielectric film C2 composed of each of the insulating films 7, 8, and 13 can be formed on the side wall portion of C1, for example, as shown in FIG. 6A (a cross-sectional view of a main part) and FIG. 6B (FIG. 6A). As shown in the main part plan view), the second electrode C3 can be formed so as to cover the first electrode C1 (the breakdown voltage of the dielectric film C2 is not restricted by the side wall around the first electrode C1). Therefore, the degree of freedom in layout on design can be increased.

Note that the insulating film 13 above the dielectric film C2 of the capacitor C is
Dielectric film, whether or not present when completed
Since there is substantially no difference in the electrical characteristics of C2, the above embodiment has been described on the assumption that the insulating film 13 is present, but the present invention does not have to include the insulating film 13.

Further, the dielectric film C2 on the side wall around the first electrode C1 of the capacitive element C may be formed only of the insulating film (silicon oxide film) 7, as shown in FIG. In this case, an insulating film 7 and an insulating film (silicon nitride film) 8 are sequentially laminated on the upper surface of the first electrode C1, and the insulating film 8 is formed on the side wall around the first electrode C1. An insulating film 7 having a larger thickness than the insulating film 7 on the first electrode C1 is formed as an oxidation mask. The insulating film 7 on the side wall around the first electrode C1 is formed thick because the withstand voltage of the dielectric film C2 is not restricted by the side wall around the first electrode C1. Each of the first electrode C1 and the insulating film 8 of the dielectric film C2 is patterned by the same mask pattern.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

For example, the present invention is applicable to a semiconductor integrated circuit device having a MISFET and a capacitor in which the insulating film 8 of the dielectric film C2 is formed of a tantalum oxide (Ta ₂ O ₃ ) film.

The present invention also provides a stacked capacitor (stacked ca).
DRAM is a memory cell composed of a series circuit of a capacitor and the MISFET of Pacitor) Structure (D ynamic R andom A ccess M e
mory).

Further, the present invention is, MNOS (M etal N itride O xide S e
EEPROM consisting of a memory cell (two-transistor) consisting of a series circuit of a transistor with a MISFET structure
(E lectrically E rasable P rogrammable R ead O nl
(y M emory). In this case, each of the gate insulating film and the gate electrode of the transistor having the MNOS structure is the dielectric film of the above-described capacitive element,
It corresponds to each of the second electrodes.

Further, the present invention is, EPROM is a memory cell composed of a field effect transistor having a floating gate electrode and control gate electrode (E rasable P rogrammable
It can be applied to a semiconductor integrated circuit device having a R ead O nly M emory). In this case, each of the floating gate electrode, the gate insulating film, and the control gate electrode of the field effect transistor of the memory cell corresponds to each of the first electrode, the dielectric film, and the second electrode of the above-described capacitor.

Further, the present invention is, FLOTOX (Flo ating-gate T unnel
The present invention can be applied to a semiconductor integrated circuit device having an EEPROM composed of memory cells having an Oxide) structure. In this case, the FLOT
Each of the floating gate electrode, the gate insulating film, and the control electrode of the memory cell having the OX structure corresponds to each of the first electrode, the dielectric film, and the second electrode of the above-described capacitor.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a capacitor and a MISFET on the same substrate, the quality of a dielectric film of the capacitor and the quality of a gate insulating film of the MISFET can be improved.

Further, the manufacturing process of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part showing a schematic configuration of a semiconductor integrated circuit device having an analog circuit and a digital circuit on the same substrate according to an embodiment of the present invention, and FIG. FIGS. 3A to 3F are cross-sectional views of a main part showing a method of manufacturing the semiconductor integrated circuit device in each manufacturing process. FIG. 4 is a semiconductor integrated circuit device according to another embodiment of the present invention. 5A to 5D are cross-sectional views of a main part showing a method of manufacturing the semiconductor integrated circuit device for each manufacturing process, and FIG. 6A is a cross-sectional view of a main part of the semiconductor integrated circuit device. FIG. 6B is a fragmentary plan view of FIG. 6A, FIGS. 7A to 7C, FIGS. 8A to 8D, and FIGS. 9A to 9D are views of the conventional semiconductor integrated circuit. It is principal part sectional drawing which shows a method for every manufacturing process. In the figure, 1... P ^- type semiconductor substrate, 2.
3 ... p-type well region, 4 ... field insulating film, C1 ...
... first electrode, C2 ... dielectric film, C3 ... second electrode, 7,
8,13 ...... insulating film, 14 ...... gate insulating film, 15 ...... gate electrode, 16 ...... n ⁺ -type semiconductor region, 17 ...... p ⁺ -type semiconductor region,
20 …… Aluminum alloy wiring, C …… Capacitance element, Qn ……
n-channel MISFET, Qp... p-channel MISFET.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115 29/788 29/792

Claims (3)

(57) [Claims] A capacitor having a first electrode, a dielectric film, and a second electrode sequentially laminated on a first region of a main surface of the semiconductor substrate with an insulating film interposed therebetween; In a method for manufacturing a semiconductor integrated circuit device having a MISFET having a gate electrode formed on a second region different from the first region with a gate insulating film interposed therebetween, a first insulating film is formed on a first region on a main surface of the semiconductor substrate. Forming a second insulating film on the film and the second region, sequentially laminating a first electrode and a dielectric film on the first insulating film, and using the dielectric film as a mask Removing the second insulating film on the second region; forming a third insulating film on the second region on the main surface of the semiconductor substrate using the dielectric film as a mask; The third insulating film is passed through the second region of the main surface of the semiconductor substrate to adjust the threshold voltage. Introducing a substance, removing the third insulating film on the second region using the dielectric film as a mask, and removing the third insulating film on the second region from the main surface of the semiconductor substrate using the dielectric film as a mask. Forming a gate insulating film on the second region; and forming a second electrode on the dielectric film and a gate electrode on the gate insulating film with the same conductive layer. Of manufacturing a semiconductor integrated circuit device. 2. A capacitor in which a first electrode, a dielectric film, and a second electrode are sequentially stacked on a first region of a main surface of a semiconductor substrate with an insulating film interposed therebetween, and In a method for manufacturing a semiconductor integrated circuit device having a MISFET having a gate electrode formed on a second region different from the first region with a gate insulating film interposed therebetween, a first insulating film is formed on a first region on a main surface of the semiconductor substrate. Forming a second insulating film on the film and the second region, sequentially stacking a first electrode and a dielectric film on the first insulating film, and forming a second insulating film on the first surface of the semiconductor substrate. Introducing a threshold voltage adjusting impurity into the two regions through the second insulating film, and using the dielectric film as a mask;
Removing the second insulating film on the second region, forming a gate insulating film on the second region on the main surface of the semiconductor substrate using the dielectric film as a mask, Forming a second electrode on the film and a gate electrode on the gate insulating film with the same conductive layer. 3. The step of forming the dielectric film is a step of sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film, and the step of removing the second insulating film is performed by removing the dielectric film. 3. The semiconductor integrated circuit device according to claim 1, wherein the step of removing the silicon oxide film and the second insulating film on the silicon nitride film is performed using the silicon nitride film as a mask. Manufacturing method.