JP3275274B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor in which a plurality of types of field effect transistors having different withstand voltages of gate insulating films can be mixedly mounted on the same semiconductor chip.

[0002]

2. Description of the Related Art The gate insulating film of a high breakdown voltage transistor is
In order to withstand a high applied voltage, it is necessary to make the gate insulating film thicker than the gate insulating film of a normal transistor. Therefore, in order to mix both transistors on the same semiconductor chip, it is necessary to make the thicknesses of the gate insulating films of the respective transistors different from each other.

FIG. 4 shows a method of manufacturing a conventional example of a field effect transistor in which a normal transistor and a high breakdown voltage transistor are mounted on the same semiconductor chip. In this manufacturing method, as shown in FIG. 4A, a SiO ₂ film 1 as a field insulating film is formed on the surface of a Si substrate 11.
2 is selectively formed, and an SiO ₂ film 15 of the same thickness is formed by gate oxidation on the surfaces of the element active regions of both the normal transistor section 13 and the high breakdown voltage transistor section 14.

Next, the SiO 2 of the high breakdown voltage transistor section 14 is
₂ film 15 while covering with a resist (not shown), by etching the SiO ₂ film 15 of the normal-type transistor 13, as shown in FIG. 4 (b), SiO ₂ of the normal type transistor section 13 Only the film 15 is peeled off.

Next, the gate is oxidized again after removing the resist, and as shown in FIG. 4 (c), the normal transistor portion 13 and the high breakdown voltage transistor portion 14 have thicknesses meeting the respective requirements. SiO ₂ film 1 as a gate insulating film
6 and 17 are formed. Then, a gate electrode (not shown)
And a source / drain (not shown) are formed to complete a normal transistor and a high breakdown voltage transistor.

[0006]

[SUMMARY OF THE INVENTION However, in the conventional example of manufacturing the above-described method can not be formed on the temporarily SiO ₂ films 16 and 17 in a common step, SiO ₂ of the normal type transistor section 13 A lithography step, an etching step, and the like are required to peel off the film 15, and an additional oxidation step is also required after the peeling. Therefore, not only the manufacturing process is complicated, but also there is no compatibility with the manufacturing process of only the normal type transistor. Further, since the SiO ₂ film 15 of the high breakdown voltage transistor section 14 is covered with the resist, the reliability of the SiO ₂ film 17 is low due to contaminants in the resist.

[0007]

The field effect transistor according to claim 1 Means for Solving the Problems], the thickness of the gate insulating film 16 formed on the surface of the semiconductor substrate 11 is the same as each other, the gate
Gate insulating film 16 and the gate insulating film 16
First conductive layer 23 in semiconductor substrate 11 and its gate insulation
A second conductive layer on the semiconductor substrate 11 in contact with the film 16
The layer 28 is constituted capacitive elements 41 to 43 in, are connected in series between a plurality of pre Kiyo amount elements 41 to 43 of the gate electrode 25 and the channel portion 36.

[0008]

In the field effect transistor according to the first aspect, the voltage between the gate electrode 25 and the channel portion is divided by the plurality of capacitors 41 to 43 connected in series. By changing the number of 43, the voltage that can be applied between the gate electrode 25 and the channel portion 36 can be changed.

In addition , the gate electrode 25 and the channel portion 36
In order to change the voltage that can be applied between the gate insulating films 16 and 43, even if the thickness of the gate insulating film 16 on the surface of the semiconductor substrate 11 used as the insulating film of the capacitors 41 to 43 is the same, only the number thereof is changed. Since the gate insulating films 16 having the same thickness can be formed at a time in a common process,
A lithography step, an etching step, and the like for changing the thickness of the gate insulating film are unnecessary.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention in which a normal transistor and a high-breakdown-voltage transistor are applied to a field-effect transistor in which they are mounted on the same semiconductor chip will be described below with reference to FIGS.
3 will be described. Note that the same reference numerals are given to components corresponding to those in the conventional example shown in FIG.

In order to manufacture this embodiment, FIG.
As shown in the figure, the surface of the p-type Si substrate 11 has a thickness of 50n.
m and a thickness of 100 nm for the pad SiO ₂ film 21
Are sequentially formed, and the SiN film 22 is processed into a pattern of an element active region.

Then, Phos ⁺ is supplied with an acceleration energy of 100 keV and an energy of 1 × 10 ¹³ cm ⁻² in two of the element active regions to be formed in the high breakdown voltage transistor section 14 and the element isolation region therebetween. Ion implantation is performed at a dose to form an n ⁻ type diffusion layer 23.

Next, a LOCOS method is performed using the SiN film 22 as an oxidation-resistant mask, and as shown in FIG.
After forming the _second film 12, the SiN film 22 and the SiO ₂ film 21 are formed.
And peel off. Then, the SiO ₂ film 1 having a thickness of 10 nm is formed on the surface of the element active region surrounded by the SiO ₂ film 12.
6 is formed by gate oxidation. The SiO ₂ film 16
Are common to the high breakdown voltage transistor section 14 and the normal transistor section (not shown).

Next, a polycrystalline Si film having a thickness of 100 nm is deposited on the entire surface, and the polycrystalline Si film is processed in a photolithography step and an RIE step to obtain a high withstand voltage as shown in FIG. A polycrystalline Si film 25 in the region 24 of the transistor portion 14, a polycrystalline Si film 28 continuous in the regions 26 and 27, a polycrystalline Si film as a gate electrode in the normal type transistor portion, and the like are patterned.

Next, in the element active region of the Si substrate 11, both sides of the polycrystalline Si film 28 in the region 27 of the high breakdown voltage transistor portion 14 and both sides of the polycrystalline Si film as a gate electrode in the normal type transistor portion. At this time, As ⁺ ions are implanted at an acceleration energy of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . Then, annealing is performed at 900 ° C. for 30 minutes to form a diffusion layer 3 as a source and a drain.
1, 32, etc. are formed.

Thereafter, an interlayer insulating film 33 is formed on the entire surface,
A contact hole 34 reaching the polycrystalline Si film 25; and a polycrystalline Si as a gate electrode in the normal transistor portion.
A contact hole or the like reaching the film is simultaneously opened in the interlayer insulating film 33. Then, an Al electrode 35 and the like connected to the polycrystalline Si film 25 and the like via the contact hole 34 and the like are formed,
This embodiment is completed. FIG. 2 corresponds to the state of FIG.

In such a high-breakdown-voltage transistor according to the present embodiment, the polycrystalline Si film 25 serves as a gate electrode, and the portion of the region 27 below the SiO ₂ film 16 is the channel portion 3.
It is 6. Then, the diffusion layer 23 and the polycrystalline Si film 2
8 and the capacitive elements 41 to 43 connected in series with each other.
Are formed in the regions 24, 26, and 27. As shown in FIG. 3, the channel portion 36 and the polycrystalline Si film 25 serving as a gate electrode are capacitively coupled by capacitive elements 41 to 43.

The capacitance element 42 is formed by connecting the capacitance element formed by the SiO ₂ film 16 in the region 26 and the capacitance element formed by the depletion layer in series. The capacitance element 43 is also formed by the SiO ₂ film 16 in the region 27. In this case, a capacitance element and a capacitance element formed by a depletion layer are connected in series. In addition, the capacitance element 43 in the diffusion layer 31 that is the source of the high breakdown voltage transistor and the capacitance element 45 in the diffusion layer 32 that is the drain are connected to the capacitance element 43 in parallel.

Therefore, in the high breakdown voltage transistor according to the present embodiment, the capacitance element 4
1, 42 are added. In the high-breakdown-voltage transistor according to the present embodiment, the gate length and the gate width are each 1 μm, and the spread of the source and the drain below the gate electrode is about 0.1 μm.
42 = 3.5 fF, capacitance of the capacitor 43 = 2.8
fF, the capacitance of the capacitors 44 and 45 = 0.35 fF.

Therefore, even if, for example, 15 V is applied to the polycrystalline Si film 25 as the gate electrode, the regions 24, 26, 2
Only 5 V divided into three equal portions are applied to the SiO ₂ film 16 of 7, and the electric field is sufficiently low at 5 MV / cm. Therefore, by appropriately selecting the number of capacitance elements 41 to 43 and the like connected in series, the SiO ₂ film 1 having only the thickness required as a gate insulating film of a normal type transistor alone can be obtained.
Only by forming 6, a thickness required as a gate insulating film of the high breakdown voltage transistor can be substantially obtained.

In the above embodiment, three regions 2
Although the three capacitive elements 41 to 43 are connected in series using the SiO ₂ films 16 of 4, 26 and 27, for example, each SiO ₂ film 16 is polycrystalline using the SiO ₂ films 16 of five regions. By sequentially connecting the Si film and the diffusion layer, five capacitive elements can be connected in series.

In the above embodiment, the Al electrode 35 is connected to the polycrystalline Si film 25. However, if the Al electrode 35 is directly connected to the diffusion layer 23, the two capacitance elements 42, 4
Only three can be connected in series. In this case, the diffusion layer 23 becomes a gate electrode. Further, when the concentration of the diffusion layer 23 is changed, the capacitance of the depletion layer in the region 26 also changes, so that the voltage applied to the SiO ₂ film 16 can be finely adjusted.

[0023]

According to the field effect transistor of the first aspect,
By changing the number of capacitive elements, the voltage that can be applied between the gate electrode and the channel portion can be changed, so that a plurality of types of field effect transistors having different withstand voltages of the gate insulating film can be formed in the same semiconductor. Can be easily mixed on chips.

In addition , a plurality of types of field effect transistors having different withstand voltages of the gate insulating film are mixedly mounted on the same semiconductor chip, so that a lithography step, an etching step, and the like for changing the thickness of the gate insulating film are unnecessary. So
Not only is the manufacturing process simple, but it is also compatible with the manufacturing process of a single type of field effect transistor that is not mixed, and the reliability of the gate insulating film is high.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a manufacturing method according to an embodiment of the present invention in the order of steps and taken along a line II in FIG. 2;

FIG. 2 is a plan view of one embodiment in the state of FIG. 1 (c).

FIG. 3 is an equivalent circuit diagram of a high breakdown voltage transistor according to one embodiment.

FIG. 4 is a side sectional view showing a manufacturing method of a conventional example of the present invention in the order of steps.

[Explanation of symbols]

11 Si substrate 16 SiO ₂ film 23 diffusion layer 25 polycrystalline Si film 28 a polycrystalline Si film 36 channel portion 41 capacitive element 42 capacitive element 43 capacitive element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 27/088 H01L 29/78 H01L 29/788

Claims (1)

(57) [Claims] A gate insulating film formed on a surface of a semiconductor substrate having the same thickness, wherein said gate insulating film and said gate insulating film are in contact with said gate insulating film;
The first conductive layer in the semiconductor substrate and the gate insulating film
And a second conductive layer on the semiconductor substrate,
Is configured, the field effect transistors are connected in series between the plurality of front Kiyo amount element and the gate electrode and the channel portion.